1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Copyright 2018 Joyent, Inc. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/types.h> 40 #include <machine/vmm.h> 41 42 #include <err.h> 43 #include <stdio.h> 44 #include <stdlib.h> 45 #include <string.h> 46 47 #include <vmmapi.h> 48 49 #include "acpi.h" 50 #include "debug.h" 51 #include "bootrom.h" 52 #include "config.h" 53 #include "inout.h" 54 #include "pci_emul.h" 55 #include "pci_irq.h" 56 #include "pci_lpc.h" 57 #include "pctestdev.h" 58 #include "uart_emul.h" 59 60 #define IO_ICU1 0x20 61 #define IO_ICU2 0xA0 62 63 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt); 64 SET_DECLARE(lpc_sysres_set, struct lpc_sysres); 65 66 #define ELCR_PORT 0x4d0 67 SYSRES_IO(ELCR_PORT, 2); 68 69 #define IO_TIMER1_PORT 0x40 70 71 #define NMISC_PORT 0x61 72 SYSRES_IO(NMISC_PORT, 1); 73 74 static struct pci_devinst *lpc_bridge; 75 76 #define LPC_UART_NUM 4 77 static struct lpc_uart_softc { 78 struct uart_softc *uart_softc; 79 int iobase; 80 int irq; 81 int enabled; 82 } lpc_uart_softc[LPC_UART_NUM]; 83 84 static const char *lpc_uart_names[LPC_UART_NUM] = { 85 "com1", "com2", "com3", "com4" 86 }; 87 88 static const char *lpc_uart_acpi_names[LPC_UART_NUM] = { 89 "COM1", "COM2", "COM3", "COM4" 90 }; 91 92 /* 93 * LPC device configuration is in the following form: 94 * <lpc_device_name>[,<options>] 95 * For e.g. "com1,stdio" or "bootrom,/var/romfile" 96 */ 97 int 98 lpc_device_parse(const char *opts) 99 { 100 int unit, error; 101 char *str, *cpy, *lpcdev, *node_name; 102 const char *romfile, *varfile; 103 104 error = -1; 105 str = cpy = strdup(opts); 106 lpcdev = strsep(&str, ","); 107 if (lpcdev != NULL) { 108 if (strcasecmp(lpcdev, "bootrom") == 0) { 109 romfile = strsep(&str, ","); 110 if (romfile == NULL) { 111 errx(4, "invalid bootrom option \"%s\"", opts); 112 } 113 set_config_value("lpc.bootrom", romfile); 114 115 varfile = strsep(&str, ","); 116 if (varfile != NULL) { 117 set_config_value("lpc.bootvars", varfile); 118 } 119 120 error = 0; 121 goto done; 122 } 123 for (unit = 0; unit < LPC_UART_NUM; unit++) { 124 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) { 125 asprintf(&node_name, "lpc.%s.path", 126 lpc_uart_names[unit]); 127 set_config_value(node_name, str); 128 free(node_name); 129 error = 0; 130 goto done; 131 } 132 } 133 if (strcasecmp(lpcdev, pctestdev_getname()) == 0) { 134 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 135 set_config_bool(node_name, true); 136 free(node_name); 137 error = 0; 138 goto done; 139 } 140 } 141 142 done: 143 free(cpy); 144 145 return (error); 146 } 147 148 void 149 lpc_print_supported_devices(void) 150 { 151 size_t i; 152 153 printf("bootrom\n"); 154 for (i = 0; i < LPC_UART_NUM; i++) 155 printf("%s\n", lpc_uart_names[i]); 156 printf("%s\n", pctestdev_getname()); 157 } 158 159 const char * 160 lpc_bootrom(void) 161 { 162 163 return (get_config_value("lpc.bootrom")); 164 } 165 166 static void 167 lpc_uart_intr_assert(void *arg) 168 { 169 struct lpc_uart_softc *sc = arg; 170 171 assert(sc->irq >= 0); 172 173 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq); 174 } 175 176 static void 177 lpc_uart_intr_deassert(void *arg) 178 { 179 /* 180 * The COM devices on the LPC bus generate edge triggered interrupts, 181 * so nothing more to do here. 182 */ 183 } 184 185 static int 186 lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 187 uint32_t *eax, void *arg) 188 { 189 int offset; 190 struct lpc_uart_softc *sc = arg; 191 192 offset = port - sc->iobase; 193 194 switch (bytes) { 195 case 1: 196 if (in) 197 *eax = uart_read(sc->uart_softc, offset); 198 else 199 uart_write(sc->uart_softc, offset, *eax); 200 break; 201 case 2: 202 if (in) { 203 *eax = uart_read(sc->uart_softc, offset); 204 *eax |= uart_read(sc->uart_softc, offset + 1) << 8; 205 } else { 206 uart_write(sc->uart_softc, offset, *eax); 207 uart_write(sc->uart_softc, offset + 1, *eax >> 8); 208 } 209 break; 210 #ifndef __FreeBSD__ 211 case 4: 212 if (in) { 213 *eax = uart_read(sc->uart_softc, offset); 214 *eax |= uart_read(sc->uart_softc, offset + 1) << 8; 215 *eax |= uart_read(sc->uart_softc, offset + 2) << 16; 216 *eax |= uart_read(sc->uart_softc, offset + 3) << 24; 217 } else { 218 uart_write(sc->uart_softc, offset, *eax); 219 uart_write(sc->uart_softc, offset + 1, *eax >> 8); 220 uart_write(sc->uart_softc, offset + 2, *eax >> 16); 221 uart_write(sc->uart_softc, offset + 3, *eax >> 24); 222 } 223 break; 224 #endif 225 default: 226 return (-1); 227 } 228 229 return (0); 230 } 231 232 static int 233 lpc_init(struct vmctx *ctx) 234 { 235 struct lpc_uart_softc *sc; 236 struct inout_port iop; 237 const char *backend, *name; 238 char *node_name; 239 int unit, error; 240 const nvlist_t *nvl; 241 242 nvl = find_config_node("lpc"); 243 #ifndef __FreeBSD__ 244 if (nvl != NULL && nvlist_exists((nvlist_t *)nvl, "bootrom")) { 245 error = bootrom_loadrom(ctx, nvl); 246 if (error) 247 return (error); 248 } 249 #else 250 if (nvl != NULL && nvlist_exists(nvl, "bootrom")) { 251 error = bootrom_loadrom(ctx, nvl); 252 if (error) 253 return (error); 254 } 255 #endif 256 257 /* COM1 and COM2 */ 258 for (unit = 0; unit < LPC_UART_NUM; unit++) { 259 sc = &lpc_uart_softc[unit]; 260 name = lpc_uart_names[unit]; 261 262 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) { 263 EPRINTLN("Unable to allocate resources for " 264 "LPC device %s", name); 265 return (-1); 266 } 267 pci_irq_reserve(sc->irq); 268 269 sc->uart_softc = uart_init(lpc_uart_intr_assert, 270 lpc_uart_intr_deassert, sc); 271 272 asprintf(&node_name, "lpc.%s.path", name); 273 backend = get_config_value(node_name); 274 free(node_name); 275 if (uart_set_backend(sc->uart_softc, backend) != 0) { 276 EPRINTLN("Unable to initialize backend '%s' " 277 "for LPC device %s", backend, name); 278 return (-1); 279 } 280 281 bzero(&iop, sizeof(struct inout_port)); 282 iop.name = name; 283 iop.port = sc->iobase; 284 iop.size = UART_IO_BAR_SIZE; 285 iop.flags = IOPORT_F_INOUT; 286 iop.handler = lpc_uart_io_handler; 287 iop.arg = sc; 288 289 error = register_inout(&iop); 290 assert(error == 0); 291 sc->enabled = 1; 292 } 293 294 /* pc-testdev */ 295 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 296 if (get_config_bool_default(node_name, false)) { 297 error = pctestdev_init(ctx); 298 if (error) 299 return (error); 300 } 301 free(node_name); 302 303 return (0); 304 } 305 306 static void 307 pci_lpc_write_dsdt(struct pci_devinst *pi) 308 { 309 struct lpc_dsdt **ldpp, *ldp; 310 311 dsdt_line(""); 312 dsdt_line("Device (ISA)"); 313 dsdt_line("{"); 314 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func); 315 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)"); 316 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)"); 317 dsdt_line(" {"); 318 dsdt_line(" Offset (0x60),"); 319 dsdt_line(" PIRA, 8,"); 320 dsdt_line(" PIRB, 8,"); 321 dsdt_line(" PIRC, 8,"); 322 dsdt_line(" PIRD, 8,"); 323 dsdt_line(" Offset (0x68),"); 324 dsdt_line(" PIRE, 8,"); 325 dsdt_line(" PIRF, 8,"); 326 dsdt_line(" PIRG, 8,"); 327 dsdt_line(" PIRH, 8"); 328 dsdt_line(" }"); 329 dsdt_line(""); 330 331 dsdt_indent(1); 332 SET_FOREACH(ldpp, lpc_dsdt_set) { 333 ldp = *ldpp; 334 ldp->handler(); 335 } 336 337 dsdt_line(""); 338 dsdt_line("Device (PIC)"); 339 dsdt_line("{"); 340 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))"); 341 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 342 dsdt_line(" {"); 343 dsdt_indent(2); 344 dsdt_fixed_ioport(IO_ICU1, 2); 345 dsdt_fixed_ioport(IO_ICU2, 2); 346 dsdt_fixed_irq(2); 347 dsdt_unindent(2); 348 dsdt_line(" })"); 349 dsdt_line("}"); 350 351 dsdt_line(""); 352 dsdt_line("Device (TIMR)"); 353 dsdt_line("{"); 354 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))"); 355 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 356 dsdt_line(" {"); 357 dsdt_indent(2); 358 dsdt_fixed_ioport(IO_TIMER1_PORT, 4); 359 dsdt_fixed_irq(0); 360 dsdt_unindent(2); 361 dsdt_line(" })"); 362 dsdt_line("}"); 363 dsdt_unindent(1); 364 365 dsdt_line("}"); 366 } 367 368 static void 369 pci_lpc_sysres_dsdt(void) 370 { 371 struct lpc_sysres **lspp, *lsp; 372 373 dsdt_line(""); 374 dsdt_line("Device (SIO)"); 375 dsdt_line("{"); 376 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))"); 377 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 378 dsdt_line(" {"); 379 380 dsdt_indent(2); 381 SET_FOREACH(lspp, lpc_sysres_set) { 382 lsp = *lspp; 383 switch (lsp->type) { 384 case LPC_SYSRES_IO: 385 dsdt_fixed_ioport(lsp->base, lsp->length); 386 break; 387 case LPC_SYSRES_MEM: 388 dsdt_fixed_mem32(lsp->base, lsp->length); 389 break; 390 } 391 } 392 dsdt_unindent(2); 393 394 dsdt_line(" })"); 395 dsdt_line("}"); 396 } 397 LPC_DSDT(pci_lpc_sysres_dsdt); 398 399 static void 400 pci_lpc_uart_dsdt(void) 401 { 402 struct lpc_uart_softc *sc; 403 int unit; 404 405 for (unit = 0; unit < LPC_UART_NUM; unit++) { 406 sc = &lpc_uart_softc[unit]; 407 if (!sc->enabled) 408 continue; 409 dsdt_line(""); 410 dsdt_line("Device (%s)", lpc_uart_acpi_names[unit]); 411 dsdt_line("{"); 412 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))"); 413 dsdt_line(" Name (_UID, %d)", unit + 1); 414 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 415 dsdt_line(" {"); 416 dsdt_indent(2); 417 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE); 418 dsdt_fixed_irq(sc->irq); 419 dsdt_unindent(2); 420 dsdt_line(" })"); 421 dsdt_line("}"); 422 } 423 } 424 LPC_DSDT(pci_lpc_uart_dsdt); 425 426 static int 427 pci_lpc_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 428 int coff, int bytes, uint32_t val) 429 { 430 int pirq_pin; 431 432 if (bytes == 1) { 433 pirq_pin = 0; 434 if (coff >= 0x60 && coff <= 0x63) 435 pirq_pin = coff - 0x60 + 1; 436 if (coff >= 0x68 && coff <= 0x6b) 437 pirq_pin = coff - 0x68 + 5; 438 if (pirq_pin != 0) { 439 pirq_write(ctx, pirq_pin, val); 440 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin)); 441 return (0); 442 } 443 } 444 return (-1); 445 } 446 447 static void 448 pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 449 int baridx, uint64_t offset, int size, uint64_t value) 450 { 451 } 452 453 static uint64_t 454 pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 455 int baridx, uint64_t offset, int size) 456 { 457 return (0); 458 } 459 460 #define LPC_DEV 0x7000 461 #define LPC_VENDOR 0x8086 462 463 static int 464 pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl) 465 { 466 467 /* 468 * Do not allow more than one LPC bridge to be configured. 469 */ 470 if (lpc_bridge != NULL) { 471 EPRINTLN("Only one LPC bridge is allowed."); 472 return (-1); 473 } 474 475 /* 476 * Enforce that the LPC can only be configured on bus 0. This 477 * simplifies the ACPI DSDT because it can provide a decode for 478 * all legacy i/o ports behind bus 0. 479 */ 480 if (pi->pi_bus != 0) { 481 EPRINTLN("LPC bridge can be present only on bus 0."); 482 return (-1); 483 } 484 485 if (lpc_init(ctx) != 0) 486 return (-1); 487 488 /* initialize config space */ 489 pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV); 490 pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR); 491 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE); 492 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA); 493 494 lpc_bridge = pi; 495 496 return (0); 497 } 498 499 char * 500 lpc_pirq_name(int pin) 501 { 502 char *name; 503 504 if (lpc_bridge == NULL) 505 return (NULL); 506 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1); 507 return (name); 508 } 509 510 void 511 lpc_pirq_routed(void) 512 { 513 int pin; 514 515 if (lpc_bridge == NULL) 516 return; 517 518 for (pin = 0; pin < 4; pin++) 519 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1)); 520 for (pin = 0; pin < 4; pin++) 521 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5)); 522 } 523 524 static const struct pci_devemu pci_de_lpc = { 525 .pe_emu = "lpc", 526 .pe_init = pci_lpc_init, 527 .pe_write_dsdt = pci_lpc_write_dsdt, 528 .pe_cfgwrite = pci_lpc_cfgwrite, 529 .pe_barwrite = pci_lpc_write, 530 .pe_barread = pci_lpc_read 531 }; 532 PCI_EMUL_SET(pci_de_lpc); 533