1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Copyright 2018 Joyent, Inc. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/types.h> 40 #include <machine/vmm.h> 41 42 #include <stdio.h> 43 #include <stdlib.h> 44 #include <string.h> 45 46 #include <vmmapi.h> 47 48 #include "acpi.h" 49 #include "debug.h" 50 #include "bootrom.h" 51 #include "inout.h" 52 #include "pci_emul.h" 53 #include "pci_irq.h" 54 #include "pci_lpc.h" 55 #include "pctestdev.h" 56 #include "uart_emul.h" 57 58 #define IO_ICU1 0x20 59 #define IO_ICU2 0xA0 60 61 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt); 62 SET_DECLARE(lpc_sysres_set, struct lpc_sysres); 63 64 #define ELCR_PORT 0x4d0 65 SYSRES_IO(ELCR_PORT, 2); 66 67 #define IO_TIMER1_PORT 0x40 68 69 #define NMISC_PORT 0x61 70 SYSRES_IO(NMISC_PORT, 1); 71 72 static struct pci_devinst *lpc_bridge; 73 74 static const char *romfile; 75 76 #define LPC_UART_NUM 2 77 static struct lpc_uart_softc { 78 struct uart_softc *uart_softc; 79 const char *opts; 80 int iobase; 81 int irq; 82 int enabled; 83 } lpc_uart_softc[LPC_UART_NUM]; 84 85 static const char *lpc_uart_names[LPC_UART_NUM] = { "COM1", "COM2" }; 86 87 static bool pctestdev_present; 88 89 /* 90 * LPC device configuration is in the following form: 91 * <lpc_device_name>[,<options>] 92 * For e.g. "com1,stdio" or "bootrom,/var/romfile" 93 */ 94 int 95 lpc_device_parse(const char *opts) 96 { 97 int unit, error; 98 char *str, *cpy, *lpcdev; 99 100 error = -1; 101 str = cpy = strdup(opts); 102 lpcdev = strsep(&str, ","); 103 if (lpcdev != NULL) { 104 if (strcasecmp(lpcdev, "bootrom") == 0) { 105 romfile = str; 106 error = 0; 107 goto done; 108 } 109 for (unit = 0; unit < LPC_UART_NUM; unit++) { 110 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) { 111 lpc_uart_softc[unit].opts = str; 112 error = 0; 113 goto done; 114 } 115 } 116 if (strcasecmp(lpcdev, pctestdev_getname()) == 0) { 117 if (pctestdev_present) { 118 EPRINTLN("More than one %s device conf is " 119 "specified; only one is allowed.", 120 pctestdev_getname()); 121 } else if (pctestdev_parse(str) == 0) { 122 pctestdev_present = true; 123 error = 0; 124 free(cpy); 125 goto done; 126 } 127 } 128 } 129 130 done: 131 if (error) 132 free(cpy); 133 134 return (error); 135 } 136 137 void 138 lpc_print_supported_devices() 139 { 140 size_t i; 141 142 printf("bootrom\n"); 143 for (i = 0; i < LPC_UART_NUM; i++) 144 printf("%s\n", lpc_uart_names[i]); 145 printf("%s\n", pctestdev_getname()); 146 } 147 148 const char * 149 lpc_bootrom(void) 150 { 151 152 return (romfile); 153 } 154 155 static void 156 lpc_uart_intr_assert(void *arg) 157 { 158 struct lpc_uart_softc *sc = arg; 159 160 assert(sc->irq >= 0); 161 162 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq); 163 } 164 165 static void 166 lpc_uart_intr_deassert(void *arg) 167 { 168 /* 169 * The COM devices on the LPC bus generate edge triggered interrupts, 170 * so nothing more to do here. 171 */ 172 } 173 174 static int 175 lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 176 uint32_t *eax, void *arg) 177 { 178 int offset; 179 struct lpc_uart_softc *sc = arg; 180 181 offset = port - sc->iobase; 182 183 switch (bytes) { 184 case 1: 185 if (in) 186 *eax = uart_read(sc->uart_softc, offset); 187 else 188 uart_write(sc->uart_softc, offset, *eax); 189 break; 190 case 2: 191 if (in) { 192 *eax = uart_read(sc->uart_softc, offset); 193 *eax |= uart_read(sc->uart_softc, offset + 1) << 8; 194 } else { 195 uart_write(sc->uart_softc, offset, *eax); 196 uart_write(sc->uart_softc, offset + 1, *eax >> 8); 197 } 198 break; 199 #ifndef __FreeBSD__ 200 case 4: 201 if (in) { 202 *eax = uart_read(sc->uart_softc, offset); 203 *eax |= uart_read(sc->uart_softc, offset + 1) << 8; 204 *eax |= uart_read(sc->uart_softc, offset + 2) << 16; 205 *eax |= uart_read(sc->uart_softc, offset + 3) << 24; 206 } else { 207 uart_write(sc->uart_softc, offset, *eax); 208 uart_write(sc->uart_softc, offset + 1, *eax >> 8); 209 uart_write(sc->uart_softc, offset + 2, *eax >> 16); 210 uart_write(sc->uart_softc, offset + 3, *eax >> 24); 211 } 212 break; 213 #endif 214 default: 215 return (-1); 216 } 217 218 return (0); 219 } 220 221 static int 222 lpc_init(struct vmctx *ctx) 223 { 224 struct lpc_uart_softc *sc; 225 struct inout_port iop; 226 const char *name; 227 int unit, error; 228 229 if (romfile != NULL) { 230 error = bootrom_loadrom(ctx, romfile); 231 if (error) 232 return (error); 233 } 234 235 /* COM1 and COM2 */ 236 for (unit = 0; unit < LPC_UART_NUM; unit++) { 237 sc = &lpc_uart_softc[unit]; 238 name = lpc_uart_names[unit]; 239 240 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) { 241 EPRINTLN("Unable to allocate resources for " 242 "LPC device %s", name); 243 return (-1); 244 } 245 pci_irq_reserve(sc->irq); 246 247 sc->uart_softc = uart_init(lpc_uart_intr_assert, 248 lpc_uart_intr_deassert, sc); 249 250 if (uart_set_backend(sc->uart_softc, sc->opts) != 0) { 251 EPRINTLN("Unable to initialize backend '%s' " 252 "for LPC device %s", sc->opts, name); 253 return (-1); 254 } 255 256 bzero(&iop, sizeof(struct inout_port)); 257 iop.name = name; 258 iop.port = sc->iobase; 259 iop.size = UART_IO_BAR_SIZE; 260 iop.flags = IOPORT_F_INOUT; 261 iop.handler = lpc_uart_io_handler; 262 iop.arg = sc; 263 264 error = register_inout(&iop); 265 assert(error == 0); 266 sc->enabled = 1; 267 } 268 269 /* pc-testdev */ 270 if (pctestdev_present) { 271 error = pctestdev_init(ctx); 272 if (error) 273 return (error); 274 } 275 276 return (0); 277 } 278 279 static void 280 pci_lpc_write_dsdt(struct pci_devinst *pi) 281 { 282 struct lpc_dsdt **ldpp, *ldp; 283 284 dsdt_line(""); 285 dsdt_line("Device (ISA)"); 286 dsdt_line("{"); 287 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func); 288 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)"); 289 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)"); 290 dsdt_line(" {"); 291 dsdt_line(" Offset (0x60),"); 292 dsdt_line(" PIRA, 8,"); 293 dsdt_line(" PIRB, 8,"); 294 dsdt_line(" PIRC, 8,"); 295 dsdt_line(" PIRD, 8,"); 296 dsdt_line(" Offset (0x68),"); 297 dsdt_line(" PIRE, 8,"); 298 dsdt_line(" PIRF, 8,"); 299 dsdt_line(" PIRG, 8,"); 300 dsdt_line(" PIRH, 8"); 301 dsdt_line(" }"); 302 dsdt_line(""); 303 304 dsdt_indent(1); 305 SET_FOREACH(ldpp, lpc_dsdt_set) { 306 ldp = *ldpp; 307 ldp->handler(); 308 } 309 310 dsdt_line(""); 311 dsdt_line("Device (PIC)"); 312 dsdt_line("{"); 313 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))"); 314 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 315 dsdt_line(" {"); 316 dsdt_indent(2); 317 dsdt_fixed_ioport(IO_ICU1, 2); 318 dsdt_fixed_ioport(IO_ICU2, 2); 319 dsdt_fixed_irq(2); 320 dsdt_unindent(2); 321 dsdt_line(" })"); 322 dsdt_line("}"); 323 324 dsdt_line(""); 325 dsdt_line("Device (TIMR)"); 326 dsdt_line("{"); 327 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))"); 328 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 329 dsdt_line(" {"); 330 dsdt_indent(2); 331 dsdt_fixed_ioport(IO_TIMER1_PORT, 4); 332 dsdt_fixed_irq(0); 333 dsdt_unindent(2); 334 dsdt_line(" })"); 335 dsdt_line("}"); 336 dsdt_unindent(1); 337 338 dsdt_line("}"); 339 } 340 341 static void 342 pci_lpc_sysres_dsdt(void) 343 { 344 struct lpc_sysres **lspp, *lsp; 345 346 dsdt_line(""); 347 dsdt_line("Device (SIO)"); 348 dsdt_line("{"); 349 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))"); 350 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 351 dsdt_line(" {"); 352 353 dsdt_indent(2); 354 SET_FOREACH(lspp, lpc_sysres_set) { 355 lsp = *lspp; 356 switch (lsp->type) { 357 case LPC_SYSRES_IO: 358 dsdt_fixed_ioport(lsp->base, lsp->length); 359 break; 360 case LPC_SYSRES_MEM: 361 dsdt_fixed_mem32(lsp->base, lsp->length); 362 break; 363 } 364 } 365 dsdt_unindent(2); 366 367 dsdt_line(" })"); 368 dsdt_line("}"); 369 } 370 LPC_DSDT(pci_lpc_sysres_dsdt); 371 372 static void 373 pci_lpc_uart_dsdt(void) 374 { 375 struct lpc_uart_softc *sc; 376 int unit; 377 378 for (unit = 0; unit < LPC_UART_NUM; unit++) { 379 sc = &lpc_uart_softc[unit]; 380 if (!sc->enabled) 381 continue; 382 dsdt_line(""); 383 dsdt_line("Device (%s)", lpc_uart_names[unit]); 384 dsdt_line("{"); 385 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))"); 386 dsdt_line(" Name (_UID, %d)", unit + 1); 387 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 388 dsdt_line(" {"); 389 dsdt_indent(2); 390 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE); 391 dsdt_fixed_irq(sc->irq); 392 dsdt_unindent(2); 393 dsdt_line(" })"); 394 dsdt_line("}"); 395 } 396 } 397 LPC_DSDT(pci_lpc_uart_dsdt); 398 399 static int 400 pci_lpc_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 401 int coff, int bytes, uint32_t val) 402 { 403 int pirq_pin; 404 405 if (bytes == 1) { 406 pirq_pin = 0; 407 if (coff >= 0x60 && coff <= 0x63) 408 pirq_pin = coff - 0x60 + 1; 409 if (coff >= 0x68 && coff <= 0x6b) 410 pirq_pin = coff - 0x68 + 5; 411 if (pirq_pin != 0) { 412 pirq_write(ctx, pirq_pin, val); 413 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin)); 414 return (0); 415 } 416 } 417 return (-1); 418 } 419 420 static void 421 pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 422 int baridx, uint64_t offset, int size, uint64_t value) 423 { 424 } 425 426 static uint64_t 427 pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 428 int baridx, uint64_t offset, int size) 429 { 430 return (0); 431 } 432 433 #define LPC_DEV 0x7000 434 #define LPC_VENDOR 0x8086 435 436 static int 437 pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 438 { 439 440 /* 441 * Do not allow more than one LPC bridge to be configured. 442 */ 443 if (lpc_bridge != NULL) { 444 EPRINTLN("Only one LPC bridge is allowed."); 445 return (-1); 446 } 447 448 /* 449 * Enforce that the LPC can only be configured on bus 0. This 450 * simplifies the ACPI DSDT because it can provide a decode for 451 * all legacy i/o ports behind bus 0. 452 */ 453 if (pi->pi_bus != 0) { 454 EPRINTLN("LPC bridge can be present only on bus 0."); 455 return (-1); 456 } 457 458 if (lpc_init(ctx) != 0) 459 return (-1); 460 461 /* initialize config space */ 462 pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV); 463 pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR); 464 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE); 465 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA); 466 467 lpc_bridge = pi; 468 469 return (0); 470 } 471 472 char * 473 lpc_pirq_name(int pin) 474 { 475 char *name; 476 477 if (lpc_bridge == NULL) 478 return (NULL); 479 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1); 480 return (name); 481 } 482 483 void 484 lpc_pirq_routed(void) 485 { 486 int pin; 487 488 if (lpc_bridge == NULL) 489 return; 490 491 for (pin = 0; pin < 4; pin++) 492 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1)); 493 for (pin = 0; pin < 4; pin++) 494 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5)); 495 } 496 497 struct pci_devemu pci_de_lpc = { 498 .pe_emu = "lpc", 499 .pe_init = pci_lpc_init, 500 .pe_write_dsdt = pci_lpc_write_dsdt, 501 .pe_cfgwrite = pci_lpc_cfgwrite, 502 .pe_barwrite = pci_lpc_write, 503 .pe_barread = pci_lpc_read 504 }; 505 PCI_EMUL_SET(pci_de_lpc); 506