1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * This file and its contents are supplied under the terms of the 32 * Common Development and Distribution License ("CDDL"), version 1.0. 33 * You may only use this file in accordance with the terms of version 34 * 1.0 of the CDDL. 35 * 36 * A full copy of the text of the CDDL should have accompanied this 37 * source. A copy of the CDDL is also available via the Internet at 38 * http://www.illumos.org/license/CDDL. 39 * 40 * Copyright 2014 Pluribus Networks Inc. 41 * Copyright 2018 Joyent, Inc. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/param.h> 48 #include <sys/linker_set.h> 49 50 #include <ctype.h> 51 #include <errno.h> 52 #include <pthread.h> 53 #include <stdio.h> 54 #include <stdlib.h> 55 #include <string.h> 56 #include <strings.h> 57 #include <assert.h> 58 #include <stdbool.h> 59 60 #include <machine/vmm.h> 61 #include <vmmapi.h> 62 63 #include "acpi.h" 64 #include "bhyverun.h" 65 #include "debug.h" 66 #include "inout.h" 67 #include "ioapic.h" 68 #include "mem.h" 69 #include "pci_emul.h" 70 #include "pci_irq.h" 71 #include "pci_lpc.h" 72 73 #define CONF1_ADDR_PORT 0x0cf8 74 #define CONF1_DATA_PORT 0x0cfc 75 76 #define CONF1_ENABLE 0x80000000ul 77 78 #define MAXBUSES (PCI_BUSMAX + 1) 79 #define MAXSLOTS (PCI_SLOTMAX + 1) 80 #define MAXFUNCS (PCI_FUNCMAX + 1) 81 82 struct funcinfo { 83 char *fi_name; 84 char *fi_param; 85 struct pci_devinst *fi_devi; 86 }; 87 88 struct intxinfo { 89 int ii_count; 90 int ii_pirq_pin; 91 int ii_ioapic_irq; 92 }; 93 94 struct slotinfo { 95 struct intxinfo si_intpins[4]; 96 struct funcinfo si_funcs[MAXFUNCS]; 97 }; 98 99 struct businfo { 100 uint16_t iobase, iolimit; /* I/O window */ 101 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 102 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 103 struct slotinfo slotinfo[MAXSLOTS]; 104 }; 105 106 static struct businfo *pci_businfo[MAXBUSES]; 107 108 SET_DECLARE(pci_devemu_set, struct pci_devemu); 109 110 static uint64_t pci_emul_iobase; 111 static uint64_t pci_emul_membase32; 112 static uint64_t pci_emul_membase64; 113 114 #define PCI_EMUL_IOBASE 0x2000 115 #define PCI_EMUL_IOLIMIT 0x10000 116 117 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 118 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 119 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 120 121 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 122 123 #define PCI_EMUL_MEMBASE64 0xD000000000UL 124 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 125 126 static struct pci_devemu *pci_emul_finddev(char *name); 127 static void pci_lintr_route(struct pci_devinst *pi); 128 static void pci_lintr_update(struct pci_devinst *pi); 129 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, 130 int func, int coff, int bytes, uint32_t *val); 131 132 static __inline void 133 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 134 { 135 136 if (bytes == 1) 137 pci_set_cfgdata8(pi, coff, val); 138 else if (bytes == 2) 139 pci_set_cfgdata16(pi, coff, val); 140 else 141 pci_set_cfgdata32(pi, coff, val); 142 } 143 144 static __inline uint32_t 145 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 146 { 147 148 if (bytes == 1) 149 return (pci_get_cfgdata8(pi, coff)); 150 else if (bytes == 2) 151 return (pci_get_cfgdata16(pi, coff)); 152 else 153 return (pci_get_cfgdata32(pi, coff)); 154 } 155 156 /* 157 * I/O access 158 */ 159 160 /* 161 * Slot options are in the form: 162 * 163 * <bus>:<slot>:<func>,<emul>[,<config>] 164 * <slot>[:<func>],<emul>[,<config>] 165 * 166 * slot is 0..31 167 * func is 0..7 168 * emul is a string describing the type of PCI device e.g. virtio-net 169 * config is an optional string, depending on the device, that can be 170 * used for configuration. 171 * Examples are: 172 * 1,virtio-net,tap0 173 * 3:0,dummy 174 */ 175 static void 176 pci_parse_slot_usage(char *aopt) 177 { 178 179 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt); 180 } 181 182 int 183 pci_parse_slot(char *opt) 184 { 185 struct businfo *bi; 186 struct slotinfo *si; 187 char *emul, *config, *str, *cp; 188 int error, bnum, snum, fnum; 189 190 error = -1; 191 str = strdup(opt); 192 193 emul = config = NULL; 194 if ((cp = strchr(str, ',')) != NULL) { 195 *cp = '\0'; 196 emul = cp + 1; 197 if ((cp = strchr(emul, ',')) != NULL) { 198 *cp = '\0'; 199 config = cp + 1; 200 } 201 } else { 202 pci_parse_slot_usage(opt); 203 goto done; 204 } 205 206 /* <bus>:<slot>:<func> */ 207 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 208 bnum = 0; 209 /* <slot>:<func> */ 210 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 211 fnum = 0; 212 /* <slot> */ 213 if (sscanf(str, "%d", &snum) != 1) { 214 snum = -1; 215 } 216 } 217 } 218 219 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 220 fnum < 0 || fnum >= MAXFUNCS) { 221 pci_parse_slot_usage(opt); 222 goto done; 223 } 224 225 if (pci_businfo[bnum] == NULL) 226 pci_businfo[bnum] = calloc(1, sizeof(struct businfo)); 227 228 bi = pci_businfo[bnum]; 229 si = &bi->slotinfo[snum]; 230 231 if (si->si_funcs[fnum].fi_name != NULL) { 232 EPRINTLN("pci slot %d:%d already occupied!", 233 snum, fnum); 234 goto done; 235 } 236 237 if (pci_emul_finddev(emul) == NULL) { 238 EPRINTLN("pci slot %d:%d: unknown device \"%s\"", 239 snum, fnum, emul); 240 goto done; 241 } 242 243 error = 0; 244 si->si_funcs[fnum].fi_name = emul; 245 si->si_funcs[fnum].fi_param = config; 246 247 done: 248 if (error) 249 free(str); 250 251 return (error); 252 } 253 254 void 255 pci_print_supported_devices() 256 { 257 struct pci_devemu **pdpp, *pdp; 258 259 SET_FOREACH(pdpp, pci_devemu_set) { 260 pdp = *pdpp; 261 printf("%s\n", pdp->pe_emu); 262 } 263 } 264 265 static int 266 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 267 { 268 269 if (offset < pi->pi_msix.pba_offset) 270 return (0); 271 272 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 273 return (0); 274 } 275 276 return (1); 277 } 278 279 int 280 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 281 uint64_t value) 282 { 283 int msix_entry_offset; 284 int tab_index; 285 char *dest; 286 287 /* support only 4 or 8 byte writes */ 288 if (size != 4 && size != 8) 289 return (-1); 290 291 /* 292 * Return if table index is beyond what device supports 293 */ 294 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 295 if (tab_index >= pi->pi_msix.table_count) 296 return (-1); 297 298 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 299 300 /* support only aligned writes */ 301 if ((msix_entry_offset % size) != 0) 302 return (-1); 303 304 dest = (char *)(pi->pi_msix.table + tab_index); 305 dest += msix_entry_offset; 306 307 if (size == 4) 308 *((uint32_t *)dest) = value; 309 else 310 *((uint64_t *)dest) = value; 311 312 return (0); 313 } 314 315 uint64_t 316 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 317 { 318 char *dest; 319 int msix_entry_offset; 320 int tab_index; 321 uint64_t retval = ~0; 322 323 /* 324 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 325 * table but we also allow 1 byte access to accommodate reads from 326 * ddb. 327 */ 328 if (size != 1 && size != 4 && size != 8) 329 return (retval); 330 331 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 332 333 /* support only aligned reads */ 334 if ((msix_entry_offset % size) != 0) { 335 return (retval); 336 } 337 338 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 339 340 if (tab_index < pi->pi_msix.table_count) { 341 /* valid MSI-X Table access */ 342 dest = (char *)(pi->pi_msix.table + tab_index); 343 dest += msix_entry_offset; 344 345 if (size == 1) 346 retval = *((uint8_t *)dest); 347 else if (size == 4) 348 retval = *((uint32_t *)dest); 349 else 350 retval = *((uint64_t *)dest); 351 } else if (pci_valid_pba_offset(pi, offset)) { 352 /* return 0 for PBA access */ 353 retval = 0; 354 } 355 356 return (retval); 357 } 358 359 int 360 pci_msix_table_bar(struct pci_devinst *pi) 361 { 362 363 if (pi->pi_msix.table != NULL) 364 return (pi->pi_msix.table_bar); 365 else 366 return (-1); 367 } 368 369 int 370 pci_msix_pba_bar(struct pci_devinst *pi) 371 { 372 373 if (pi->pi_msix.table != NULL) 374 return (pi->pi_msix.pba_bar); 375 else 376 return (-1); 377 } 378 379 static int 380 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 381 uint32_t *eax, void *arg) 382 { 383 struct pci_devinst *pdi = arg; 384 struct pci_devemu *pe = pdi->pi_d; 385 uint64_t offset; 386 int i; 387 388 for (i = 0; i <= PCI_BARMAX; i++) { 389 if (pdi->pi_bar[i].type == PCIBAR_IO && 390 port >= pdi->pi_bar[i].addr && 391 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 392 offset = port - pdi->pi_bar[i].addr; 393 if (in) 394 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 395 offset, bytes); 396 else 397 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 398 bytes, *eax); 399 return (0); 400 } 401 } 402 return (-1); 403 } 404 405 static int 406 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 407 int size, uint64_t *val, void *arg1, long arg2) 408 { 409 struct pci_devinst *pdi = arg1; 410 struct pci_devemu *pe = pdi->pi_d; 411 uint64_t offset; 412 int bidx = (int) arg2; 413 414 assert(bidx <= PCI_BARMAX); 415 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 416 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 417 assert(addr >= pdi->pi_bar[bidx].addr && 418 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 419 420 offset = addr - pdi->pi_bar[bidx].addr; 421 422 if (dir == MEM_F_WRITE) { 423 if (size == 8) { 424 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 425 4, *val & 0xffffffff); 426 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4, 427 4, *val >> 32); 428 } else { 429 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 430 size, *val); 431 } 432 } else { 433 if (size == 8) { 434 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 435 offset, 4); 436 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 437 offset + 4, 4) << 32; 438 } else { 439 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 440 offset, size); 441 } 442 } 443 444 return (0); 445 } 446 447 448 static int 449 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 450 uint64_t *addr) 451 { 452 uint64_t base; 453 454 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 455 456 base = roundup2(*baseptr, size); 457 458 if (base + size <= limit) { 459 *addr = base; 460 *baseptr = base + size; 461 return (0); 462 } else 463 return (-1); 464 } 465 466 int 467 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 468 uint64_t size) 469 { 470 471 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 472 } 473 474 /* 475 * Register (or unregister) the MMIO or I/O region associated with the BAR 476 * register 'idx' of an emulated pci device. 477 */ 478 static void 479 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 480 { 481 int error; 482 struct inout_port iop; 483 struct mem_range mr; 484 485 switch (pi->pi_bar[idx].type) { 486 case PCIBAR_IO: 487 bzero(&iop, sizeof(struct inout_port)); 488 iop.name = pi->pi_name; 489 iop.port = pi->pi_bar[idx].addr; 490 iop.size = pi->pi_bar[idx].size; 491 if (registration) { 492 iop.flags = IOPORT_F_INOUT; 493 iop.handler = pci_emul_io_handler; 494 iop.arg = pi; 495 error = register_inout(&iop); 496 } else 497 error = unregister_inout(&iop); 498 break; 499 case PCIBAR_MEM32: 500 case PCIBAR_MEM64: 501 bzero(&mr, sizeof(struct mem_range)); 502 mr.name = pi->pi_name; 503 mr.base = pi->pi_bar[idx].addr; 504 mr.size = pi->pi_bar[idx].size; 505 if (registration) { 506 mr.flags = MEM_F_RW; 507 mr.handler = pci_emul_mem_handler; 508 mr.arg1 = pi; 509 mr.arg2 = idx; 510 error = register_mem(&mr); 511 } else 512 error = unregister_mem(&mr); 513 break; 514 default: 515 error = EINVAL; 516 break; 517 } 518 assert(error == 0); 519 } 520 521 static void 522 unregister_bar(struct pci_devinst *pi, int idx) 523 { 524 525 modify_bar_registration(pi, idx, 0); 526 } 527 528 static void 529 register_bar(struct pci_devinst *pi, int idx) 530 { 531 532 modify_bar_registration(pi, idx, 1); 533 } 534 535 /* Are we decoding i/o port accesses for the emulated pci device? */ 536 static int 537 porten(struct pci_devinst *pi) 538 { 539 uint16_t cmd; 540 541 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 542 543 return (cmd & PCIM_CMD_PORTEN); 544 } 545 546 /* Are we decoding memory accesses for the emulated pci device? */ 547 static int 548 memen(struct pci_devinst *pi) 549 { 550 uint16_t cmd; 551 552 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 553 554 return (cmd & PCIM_CMD_MEMEN); 555 } 556 557 /* 558 * Update the MMIO or I/O address that is decoded by the BAR register. 559 * 560 * If the pci device has enabled the address space decoding then intercept 561 * the address range decoded by the BAR register. 562 */ 563 static void 564 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 565 { 566 int decode; 567 568 if (pi->pi_bar[idx].type == PCIBAR_IO) 569 decode = porten(pi); 570 else 571 decode = memen(pi); 572 573 if (decode) 574 unregister_bar(pi, idx); 575 576 switch (type) { 577 case PCIBAR_IO: 578 case PCIBAR_MEM32: 579 pi->pi_bar[idx].addr = addr; 580 break; 581 case PCIBAR_MEM64: 582 pi->pi_bar[idx].addr &= ~0xffffffffUL; 583 pi->pi_bar[idx].addr |= addr; 584 break; 585 case PCIBAR_MEMHI64: 586 pi->pi_bar[idx].addr &= 0xffffffff; 587 pi->pi_bar[idx].addr |= addr; 588 break; 589 default: 590 assert(0); 591 } 592 593 if (decode) 594 register_bar(pi, idx); 595 } 596 597 int 598 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 599 enum pcibar_type type, uint64_t size) 600 { 601 uint64_t *baseptr = NULL; 602 uint64_t limit = 0, lobits = 0; 603 uint64_t addr, mask, bar; 604 uint16_t cmd, enbit; 605 int error; 606 607 assert(idx >= 0 && idx <= PCI_BARMAX); 608 609 if ((size & (size - 1)) != 0) 610 size = 1UL << flsl(size); /* round up to a power of 2 */ 611 612 /* Enforce minimum BAR sizes required by the PCI standard */ 613 if (type == PCIBAR_IO) { 614 if (size < 4) 615 size = 4; 616 } else { 617 if (size < 16) 618 size = 16; 619 } 620 621 switch (type) { 622 case PCIBAR_NONE: 623 baseptr = NULL; 624 addr = mask = lobits = enbit = 0; 625 break; 626 case PCIBAR_IO: 627 baseptr = &pci_emul_iobase; 628 limit = PCI_EMUL_IOLIMIT; 629 mask = PCIM_BAR_IO_BASE; 630 lobits = PCIM_BAR_IO_SPACE; 631 enbit = PCIM_CMD_PORTEN; 632 break; 633 case PCIBAR_MEM64: 634 /* 635 * XXX 636 * Some drivers do not work well if the 64-bit BAR is allocated 637 * above 4GB. Allow for this by allocating small requests under 638 * 4GB unless then allocation size is larger than some arbitrary 639 * number (32MB currently). 640 */ 641 if (size > 32 * 1024 * 1024) { 642 /* 643 * XXX special case for device requiring peer-peer DMA 644 */ 645 if (size == 0x100000000UL) 646 baseptr = &hostbase; 647 else 648 baseptr = &pci_emul_membase64; 649 limit = PCI_EMUL_MEMLIMIT64; 650 mask = PCIM_BAR_MEM_BASE; 651 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 652 PCIM_BAR_MEM_PREFETCH; 653 } else { 654 baseptr = &pci_emul_membase32; 655 limit = PCI_EMUL_MEMLIMIT32; 656 mask = PCIM_BAR_MEM_BASE; 657 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 658 } 659 enbit = PCIM_CMD_MEMEN; 660 break; 661 case PCIBAR_MEM32: 662 baseptr = &pci_emul_membase32; 663 limit = PCI_EMUL_MEMLIMIT32; 664 mask = PCIM_BAR_MEM_BASE; 665 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 666 enbit = PCIM_CMD_MEMEN; 667 break; 668 default: 669 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 670 #ifdef FreeBSD 671 assert(0); 672 #else 673 abort(); 674 #endif 675 } 676 677 if (baseptr != NULL) { 678 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 679 if (error != 0) 680 return (error); 681 } 682 683 pdi->pi_bar[idx].type = type; 684 pdi->pi_bar[idx].addr = addr; 685 pdi->pi_bar[idx].size = size; 686 687 /* Initialize the BAR register in config space */ 688 bar = (addr & mask) | lobits; 689 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 690 691 if (type == PCIBAR_MEM64) { 692 assert(idx + 1 <= PCI_BARMAX); 693 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 694 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 695 } 696 697 cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 698 if ((cmd & enbit) != enbit) 699 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 700 register_bar(pdi, idx); 701 702 return (0); 703 } 704 705 #define CAP_START_OFFSET 0x40 706 static int 707 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 708 { 709 int i, capoff, reallen; 710 uint16_t sts; 711 712 assert(caplen > 0); 713 714 reallen = roundup2(caplen, 4); /* dword aligned */ 715 716 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 717 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 718 capoff = CAP_START_OFFSET; 719 else 720 capoff = pi->pi_capend + 1; 721 722 /* Check if we have enough space */ 723 if (capoff + reallen > PCI_REGMAX + 1) 724 return (-1); 725 726 /* Set the previous capability pointer */ 727 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 728 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 729 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 730 } else 731 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 732 733 /* Copy the capability */ 734 for (i = 0; i < caplen; i++) 735 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 736 737 /* Set the next capability pointer */ 738 pci_set_cfgdata8(pi, capoff + 1, 0); 739 740 pi->pi_prevcap = capoff; 741 pi->pi_capend = capoff + reallen - 1; 742 return (0); 743 } 744 745 static struct pci_devemu * 746 pci_emul_finddev(char *name) 747 { 748 struct pci_devemu **pdpp, *pdp; 749 750 SET_FOREACH(pdpp, pci_devemu_set) { 751 pdp = *pdpp; 752 if (!strcmp(pdp->pe_emu, name)) { 753 return (pdp); 754 } 755 } 756 757 return (NULL); 758 } 759 760 static int 761 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 762 int func, struct funcinfo *fi) 763 { 764 struct pci_devinst *pdi; 765 int err; 766 767 pdi = calloc(1, sizeof(struct pci_devinst)); 768 769 pdi->pi_vmctx = ctx; 770 pdi->pi_bus = bus; 771 pdi->pi_slot = slot; 772 pdi->pi_func = func; 773 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 774 pdi->pi_lintr.pin = 0; 775 pdi->pi_lintr.state = IDLE; 776 pdi->pi_lintr.pirq_pin = 0; 777 pdi->pi_lintr.ioapic_irq = 0; 778 pdi->pi_d = pde; 779 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 780 781 /* Disable legacy interrupts */ 782 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 783 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 784 785 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 786 787 err = (*pde->pe_init)(ctx, pdi, fi->fi_param); 788 if (err == 0) 789 fi->fi_devi = pdi; 790 else 791 free(pdi); 792 793 return (err); 794 } 795 796 void 797 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 798 { 799 int mmc; 800 801 /* Number of msi messages must be a power of 2 between 1 and 32 */ 802 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 803 mmc = ffs(msgnum) - 1; 804 805 bzero(msicap, sizeof(struct msicap)); 806 msicap->capid = PCIY_MSI; 807 msicap->nextptr = nextptr; 808 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 809 } 810 811 int 812 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 813 { 814 struct msicap msicap; 815 816 pci_populate_msicap(&msicap, msgnum, 0); 817 818 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 819 } 820 821 static void 822 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 823 uint32_t msix_tab_size) 824 { 825 826 assert(msix_tab_size % 4096 == 0); 827 828 bzero(msixcap, sizeof(struct msixcap)); 829 msixcap->capid = PCIY_MSIX; 830 831 /* 832 * Message Control Register, all fields set to 833 * zero except for the Table Size. 834 * Note: Table size N is encoded as N-1 835 */ 836 msixcap->msgctrl = msgnum - 1; 837 838 /* 839 * MSI-X BAR setup: 840 * - MSI-X table start at offset 0 841 * - PBA table starts at a 4K aligned offset after the MSI-X table 842 */ 843 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 844 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 845 } 846 847 static void 848 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 849 { 850 int i, table_size; 851 852 assert(table_entries > 0); 853 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 854 855 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 856 pi->pi_msix.table = calloc(1, table_size); 857 858 /* set mask bit of vector control register */ 859 for (i = 0; i < table_entries; i++) 860 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 861 } 862 863 int 864 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 865 { 866 uint32_t tab_size; 867 struct msixcap msixcap; 868 869 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 870 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 871 872 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 873 874 /* Align table size to nearest 4K */ 875 tab_size = roundup2(tab_size, 4096); 876 877 pi->pi_msix.table_bar = barnum; 878 pi->pi_msix.pba_bar = barnum; 879 pi->pi_msix.table_offset = 0; 880 pi->pi_msix.table_count = msgnum; 881 pi->pi_msix.pba_offset = tab_size; 882 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 883 884 pci_msix_table_init(pi, msgnum); 885 886 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 887 888 /* allocate memory for MSI-X Table and PBA */ 889 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 890 tab_size + pi->pi_msix.pba_size); 891 892 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 893 sizeof(msixcap))); 894 } 895 896 static void 897 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 898 int bytes, uint32_t val) 899 { 900 uint16_t msgctrl, rwmask; 901 int off; 902 903 off = offset - capoff; 904 /* Message Control Register */ 905 if (off == 2 && bytes == 2) { 906 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 907 msgctrl = pci_get_cfgdata16(pi, offset); 908 msgctrl &= ~rwmask; 909 msgctrl |= val & rwmask; 910 val = msgctrl; 911 912 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 913 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 914 pci_lintr_update(pi); 915 } 916 917 CFGWRITE(pi, offset, val, bytes); 918 } 919 920 static void 921 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 922 int bytes, uint32_t val) 923 { 924 uint16_t msgctrl, rwmask, msgdata, mme; 925 uint32_t addrlo; 926 927 /* 928 * If guest is writing to the message control register make sure 929 * we do not overwrite read-only fields. 930 */ 931 if ((offset - capoff) == 2 && bytes == 2) { 932 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 933 msgctrl = pci_get_cfgdata16(pi, offset); 934 msgctrl &= ~rwmask; 935 msgctrl |= val & rwmask; 936 val = msgctrl; 937 } 938 CFGWRITE(pi, offset, val, bytes); 939 940 msgctrl = pci_get_cfgdata16(pi, capoff + 2); 941 addrlo = pci_get_cfgdata32(pi, capoff + 4); 942 if (msgctrl & PCIM_MSICTRL_64BIT) 943 msgdata = pci_get_cfgdata16(pi, capoff + 12); 944 else 945 msgdata = pci_get_cfgdata16(pi, capoff + 8); 946 947 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 948 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 949 if (pi->pi_msi.enabled) { 950 pi->pi_msi.addr = addrlo; 951 pi->pi_msi.msg_data = msgdata; 952 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 953 } else { 954 pi->pi_msi.maxmsgnum = 0; 955 } 956 pci_lintr_update(pi); 957 } 958 959 void 960 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 961 int bytes, uint32_t val) 962 { 963 964 /* XXX don't write to the readonly parts */ 965 CFGWRITE(pi, offset, val, bytes); 966 } 967 968 #define PCIECAP_VERSION 0x2 969 int 970 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 971 { 972 int err; 973 struct pciecap pciecap; 974 975 bzero(&pciecap, sizeof(pciecap)); 976 977 /* 978 * Use the integrated endpoint type for endpoints on a root complex bus. 979 * 980 * NB: bhyve currently only supports a single PCI bus that is the root 981 * complex bus, so all endpoints are integrated. 982 */ 983 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 984 type = PCIEM_TYPE_ROOT_INT_EP; 985 986 pciecap.capid = PCIY_EXPRESS; 987 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 988 if (type != PCIEM_TYPE_ROOT_INT_EP) { 989 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 990 pciecap.link_status = 0x11; /* gen1, x1 */ 991 } 992 993 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 994 return (err); 995 } 996 997 /* 998 * This function assumes that 'coff' is in the capabilities region of the 999 * config space. A capoff parameter of zero will force a search for the 1000 * offset and type. 1001 */ 1002 void 1003 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val, 1004 uint8_t capoff, int capid) 1005 { 1006 uint8_t nextoff; 1007 1008 /* Do not allow un-aligned writes */ 1009 if ((offset & (bytes - 1)) != 0) 1010 return; 1011 1012 if (capoff == 0) { 1013 /* Find the capability that we want to update */ 1014 capoff = CAP_START_OFFSET; 1015 while (1) { 1016 nextoff = pci_get_cfgdata8(pi, capoff + 1); 1017 if (nextoff == 0) 1018 break; 1019 if (offset >= capoff && offset < nextoff) 1020 break; 1021 1022 capoff = nextoff; 1023 } 1024 assert(offset >= capoff); 1025 capid = pci_get_cfgdata8(pi, capoff); 1026 } 1027 1028 /* 1029 * Capability ID and Next Capability Pointer are readonly. 1030 * However, some o/s's do 4-byte writes that include these. 1031 * For this case, trim the write back to 2 bytes and adjust 1032 * the data. 1033 */ 1034 if (offset == capoff || offset == capoff + 1) { 1035 if (offset == capoff && bytes == 4) { 1036 bytes = 2; 1037 offset += 2; 1038 val >>= 16; 1039 } else 1040 return; 1041 } 1042 1043 switch (capid) { 1044 case PCIY_MSI: 1045 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1046 break; 1047 case PCIY_MSIX: 1048 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1049 break; 1050 case PCIY_EXPRESS: 1051 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1052 break; 1053 default: 1054 break; 1055 } 1056 } 1057 1058 static int 1059 pci_emul_iscap(struct pci_devinst *pi, int offset) 1060 { 1061 uint16_t sts; 1062 1063 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1064 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1065 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1066 return (1); 1067 } 1068 return (0); 1069 } 1070 1071 static int 1072 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1073 int size, uint64_t *val, void *arg1, long arg2) 1074 { 1075 /* 1076 * Ignore writes; return 0xff's for reads. The mem read code 1077 * will take care of truncating to the correct size. 1078 */ 1079 if (dir == MEM_F_READ) { 1080 *val = 0xffffffffffffffff; 1081 } 1082 1083 return (0); 1084 } 1085 1086 static int 1087 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1088 int bytes, uint64_t *val, void *arg1, long arg2) 1089 { 1090 int bus, slot, func, coff, in; 1091 1092 coff = addr & 0xfff; 1093 func = (addr >> 12) & 0x7; 1094 slot = (addr >> 15) & 0x1f; 1095 bus = (addr >> 20) & 0xff; 1096 in = (dir == MEM_F_READ); 1097 if (in) 1098 *val = ~0UL; 1099 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val); 1100 return (0); 1101 } 1102 1103 uint64_t 1104 pci_ecfg_base(void) 1105 { 1106 1107 return (PCI_EMUL_ECFG_BASE); 1108 } 1109 1110 #define BUSIO_ROUNDUP 32 1111 #define BUSMEM_ROUNDUP (1024 * 1024) 1112 1113 int 1114 init_pci(struct vmctx *ctx) 1115 { 1116 struct mem_range mr; 1117 struct pci_devemu *pde; 1118 struct businfo *bi; 1119 struct slotinfo *si; 1120 struct funcinfo *fi; 1121 size_t lowmem; 1122 int bus, slot, func; 1123 int error; 1124 1125 pci_emul_iobase = PCI_EMUL_IOBASE; 1126 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1127 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1128 1129 for (bus = 0; bus < MAXBUSES; bus++) { 1130 if ((bi = pci_businfo[bus]) == NULL) 1131 continue; 1132 /* 1133 * Keep track of the i/o and memory resources allocated to 1134 * this bus. 1135 */ 1136 bi->iobase = pci_emul_iobase; 1137 bi->membase32 = pci_emul_membase32; 1138 bi->membase64 = pci_emul_membase64; 1139 1140 for (slot = 0; slot < MAXSLOTS; slot++) { 1141 si = &bi->slotinfo[slot]; 1142 for (func = 0; func < MAXFUNCS; func++) { 1143 fi = &si->si_funcs[func]; 1144 if (fi->fi_name == NULL) 1145 continue; 1146 pde = pci_emul_finddev(fi->fi_name); 1147 assert(pde != NULL); 1148 error = pci_emul_init(ctx, pde, bus, slot, 1149 func, fi); 1150 if (error) 1151 return (error); 1152 } 1153 } 1154 1155 /* 1156 * Add some slop to the I/O and memory resources decoded by 1157 * this bus to give a guest some flexibility if it wants to 1158 * reprogram the BARs. 1159 */ 1160 pci_emul_iobase += BUSIO_ROUNDUP; 1161 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1162 bi->iolimit = pci_emul_iobase; 1163 1164 pci_emul_membase32 += BUSMEM_ROUNDUP; 1165 pci_emul_membase32 = roundup2(pci_emul_membase32, 1166 BUSMEM_ROUNDUP); 1167 bi->memlimit32 = pci_emul_membase32; 1168 1169 pci_emul_membase64 += BUSMEM_ROUNDUP; 1170 pci_emul_membase64 = roundup2(pci_emul_membase64, 1171 BUSMEM_ROUNDUP); 1172 bi->memlimit64 = pci_emul_membase64; 1173 } 1174 1175 /* 1176 * PCI backends are initialized before routing INTx interrupts 1177 * so that LPC devices are able to reserve ISA IRQs before 1178 * routing PIRQ pins. 1179 */ 1180 for (bus = 0; bus < MAXBUSES; bus++) { 1181 if ((bi = pci_businfo[bus]) == NULL) 1182 continue; 1183 1184 for (slot = 0; slot < MAXSLOTS; slot++) { 1185 si = &bi->slotinfo[slot]; 1186 for (func = 0; func < MAXFUNCS; func++) { 1187 fi = &si->si_funcs[func]; 1188 if (fi->fi_devi == NULL) 1189 continue; 1190 pci_lintr_route(fi->fi_devi); 1191 } 1192 } 1193 } 1194 lpc_pirq_routed(); 1195 1196 /* 1197 * The guest physical memory map looks like the following: 1198 * [0, lowmem) guest system memory 1199 * [lowmem, lowmem_limit) memory hole (may be absent) 1200 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation) 1201 * [0xE0000000, 0xF0000000) PCI extended config window 1202 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1203 * [4GB, 4GB + highmem) 1204 */ 1205 1206 /* 1207 * Accesses to memory addresses that are not allocated to system 1208 * memory or PCI devices return 0xff's. 1209 */ 1210 lowmem = vm_get_lowmem_size(ctx); 1211 bzero(&mr, sizeof(struct mem_range)); 1212 mr.name = "PCI hole"; 1213 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1214 mr.base = lowmem; 1215 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1216 mr.handler = pci_emul_fallback_handler; 1217 error = register_mem_fallback(&mr); 1218 assert(error == 0); 1219 1220 /* PCI extended config space */ 1221 bzero(&mr, sizeof(struct mem_range)); 1222 mr.name = "PCI ECFG"; 1223 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1224 mr.base = PCI_EMUL_ECFG_BASE; 1225 mr.size = PCI_EMUL_ECFG_SIZE; 1226 mr.handler = pci_emul_ecfg_handler; 1227 error = register_mem(&mr); 1228 assert(error == 0); 1229 1230 return (0); 1231 } 1232 1233 static void 1234 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1235 void *arg) 1236 { 1237 1238 dsdt_line(" Package ()"); 1239 dsdt_line(" {"); 1240 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1241 dsdt_line(" 0x%02X,", pin - 1); 1242 dsdt_line(" Zero,"); 1243 dsdt_line(" 0x%X", ioapic_irq); 1244 dsdt_line(" },"); 1245 } 1246 1247 static void 1248 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1249 void *arg) 1250 { 1251 char *name; 1252 1253 name = lpc_pirq_name(pirq_pin); 1254 if (name == NULL) 1255 return; 1256 dsdt_line(" Package ()"); 1257 dsdt_line(" {"); 1258 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1259 dsdt_line(" 0x%02X,", pin - 1); 1260 dsdt_line(" %s,", name); 1261 dsdt_line(" 0x00"); 1262 dsdt_line(" },"); 1263 free(name); 1264 } 1265 1266 /* 1267 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1268 * corresponding to each PCI bus. 1269 */ 1270 static void 1271 pci_bus_write_dsdt(int bus) 1272 { 1273 struct businfo *bi; 1274 struct slotinfo *si; 1275 struct pci_devinst *pi; 1276 int count, func, slot; 1277 1278 /* 1279 * If there are no devices on this 'bus' then just return. 1280 */ 1281 if ((bi = pci_businfo[bus]) == NULL) { 1282 /* 1283 * Bus 0 is special because it decodes the I/O ports used 1284 * for PCI config space access even if there are no devices 1285 * on it. 1286 */ 1287 if (bus != 0) 1288 return; 1289 } 1290 1291 dsdt_line(" Device (PC%02X)", bus); 1292 dsdt_line(" {"); 1293 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1294 1295 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1296 dsdt_line(" {"); 1297 dsdt_line(" Return (0x%08X)", bus); 1298 dsdt_line(" }"); 1299 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1300 dsdt_line(" {"); 1301 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1302 "MaxFixed, PosDecode,"); 1303 dsdt_line(" 0x0000, // Granularity"); 1304 dsdt_line(" 0x%04X, // Range Minimum", bus); 1305 dsdt_line(" 0x%04X, // Range Maximum", bus); 1306 dsdt_line(" 0x0000, // Translation Offset"); 1307 dsdt_line(" 0x0001, // Length"); 1308 dsdt_line(" ,, )"); 1309 1310 if (bus == 0) { 1311 dsdt_indent(3); 1312 dsdt_fixed_ioport(0xCF8, 8); 1313 dsdt_unindent(3); 1314 1315 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1316 "PosDecode, EntireRange,"); 1317 dsdt_line(" 0x0000, // Granularity"); 1318 dsdt_line(" 0x0000, // Range Minimum"); 1319 dsdt_line(" 0x0CF7, // Range Maximum"); 1320 dsdt_line(" 0x0000, // Translation Offset"); 1321 dsdt_line(" 0x0CF8, // Length"); 1322 dsdt_line(" ,, , TypeStatic)"); 1323 1324 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1325 "PosDecode, EntireRange,"); 1326 dsdt_line(" 0x0000, // Granularity"); 1327 dsdt_line(" 0x0D00, // Range Minimum"); 1328 dsdt_line(" 0x%04X, // Range Maximum", 1329 PCI_EMUL_IOBASE - 1); 1330 dsdt_line(" 0x0000, // Translation Offset"); 1331 dsdt_line(" 0x%04X, // Length", 1332 PCI_EMUL_IOBASE - 0x0D00); 1333 dsdt_line(" ,, , TypeStatic)"); 1334 1335 if (bi == NULL) { 1336 dsdt_line(" })"); 1337 goto done; 1338 } 1339 } 1340 assert(bi != NULL); 1341 1342 /* i/o window */ 1343 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1344 "PosDecode, EntireRange,"); 1345 dsdt_line(" 0x0000, // Granularity"); 1346 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1347 dsdt_line(" 0x%04X, // Range Maximum", 1348 bi->iolimit - 1); 1349 dsdt_line(" 0x0000, // Translation Offset"); 1350 dsdt_line(" 0x%04X, // Length", 1351 bi->iolimit - bi->iobase); 1352 dsdt_line(" ,, , TypeStatic)"); 1353 1354 /* mmio window (32-bit) */ 1355 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1356 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1357 dsdt_line(" 0x00000000, // Granularity"); 1358 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1359 dsdt_line(" 0x%08X, // Range Maximum\n", 1360 bi->memlimit32 - 1); 1361 dsdt_line(" 0x00000000, // Translation Offset"); 1362 dsdt_line(" 0x%08X, // Length\n", 1363 bi->memlimit32 - bi->membase32); 1364 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1365 1366 /* mmio window (64-bit) */ 1367 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1368 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1369 dsdt_line(" 0x0000000000000000, // Granularity"); 1370 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1371 dsdt_line(" 0x%016lX, // Range Maximum\n", 1372 bi->memlimit64 - 1); 1373 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1374 dsdt_line(" 0x%016lX, // Length\n", 1375 bi->memlimit64 - bi->membase64); 1376 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1377 dsdt_line(" })"); 1378 1379 count = pci_count_lintr(bus); 1380 if (count != 0) { 1381 dsdt_indent(2); 1382 dsdt_line("Name (PPRT, Package ()"); 1383 dsdt_line("{"); 1384 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1385 dsdt_line("})"); 1386 dsdt_line("Name (APRT, Package ()"); 1387 dsdt_line("{"); 1388 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1389 dsdt_line("})"); 1390 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1391 dsdt_line("{"); 1392 dsdt_line(" If (PICM)"); 1393 dsdt_line(" {"); 1394 dsdt_line(" Return (APRT)"); 1395 dsdt_line(" }"); 1396 dsdt_line(" Else"); 1397 dsdt_line(" {"); 1398 dsdt_line(" Return (PPRT)"); 1399 dsdt_line(" }"); 1400 dsdt_line("}"); 1401 dsdt_unindent(2); 1402 } 1403 1404 dsdt_indent(2); 1405 for (slot = 0; slot < MAXSLOTS; slot++) { 1406 si = &bi->slotinfo[slot]; 1407 for (func = 0; func < MAXFUNCS; func++) { 1408 pi = si->si_funcs[func].fi_devi; 1409 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1410 pi->pi_d->pe_write_dsdt(pi); 1411 } 1412 } 1413 dsdt_unindent(2); 1414 done: 1415 dsdt_line(" }"); 1416 } 1417 1418 void 1419 pci_write_dsdt(void) 1420 { 1421 int bus; 1422 1423 dsdt_indent(1); 1424 dsdt_line("Name (PICM, 0x00)"); 1425 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1426 dsdt_line("{"); 1427 dsdt_line(" Store (Arg0, PICM)"); 1428 dsdt_line("}"); 1429 dsdt_line(""); 1430 dsdt_line("Scope (_SB)"); 1431 dsdt_line("{"); 1432 for (bus = 0; bus < MAXBUSES; bus++) 1433 pci_bus_write_dsdt(bus); 1434 dsdt_line("}"); 1435 dsdt_unindent(1); 1436 } 1437 1438 int 1439 pci_bus_configured(int bus) 1440 { 1441 assert(bus >= 0 && bus < MAXBUSES); 1442 return (pci_businfo[bus] != NULL); 1443 } 1444 1445 int 1446 pci_msi_enabled(struct pci_devinst *pi) 1447 { 1448 return (pi->pi_msi.enabled); 1449 } 1450 1451 int 1452 pci_msi_maxmsgnum(struct pci_devinst *pi) 1453 { 1454 if (pi->pi_msi.enabled) 1455 return (pi->pi_msi.maxmsgnum); 1456 else 1457 return (0); 1458 } 1459 1460 int 1461 pci_msix_enabled(struct pci_devinst *pi) 1462 { 1463 1464 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1465 } 1466 1467 void 1468 pci_generate_msix(struct pci_devinst *pi, int index) 1469 { 1470 struct msix_table_entry *mte; 1471 1472 if (!pci_msix_enabled(pi)) 1473 return; 1474 1475 if (pi->pi_msix.function_mask) 1476 return; 1477 1478 if (index >= pi->pi_msix.table_count) 1479 return; 1480 1481 mte = &pi->pi_msix.table[index]; 1482 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1483 /* XXX Set PBA bit if interrupt is disabled */ 1484 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1485 } 1486 } 1487 1488 void 1489 pci_generate_msi(struct pci_devinst *pi, int index) 1490 { 1491 1492 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1493 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1494 pi->pi_msi.msg_data + index); 1495 } 1496 } 1497 1498 static bool 1499 pci_lintr_permitted(struct pci_devinst *pi) 1500 { 1501 uint16_t cmd; 1502 1503 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1504 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1505 (cmd & PCIM_CMD_INTxDIS))); 1506 } 1507 1508 void 1509 pci_lintr_request(struct pci_devinst *pi) 1510 { 1511 struct businfo *bi; 1512 struct slotinfo *si; 1513 int bestpin, bestcount, pin; 1514 1515 bi = pci_businfo[pi->pi_bus]; 1516 assert(bi != NULL); 1517 1518 /* 1519 * Just allocate a pin from our slot. The pin will be 1520 * assigned IRQs later when interrupts are routed. 1521 */ 1522 si = &bi->slotinfo[pi->pi_slot]; 1523 bestpin = 0; 1524 bestcount = si->si_intpins[0].ii_count; 1525 for (pin = 1; pin < 4; pin++) { 1526 if (si->si_intpins[pin].ii_count < bestcount) { 1527 bestpin = pin; 1528 bestcount = si->si_intpins[pin].ii_count; 1529 } 1530 } 1531 1532 si->si_intpins[bestpin].ii_count++; 1533 pi->pi_lintr.pin = bestpin + 1; 1534 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1535 } 1536 1537 static void 1538 pci_lintr_route(struct pci_devinst *pi) 1539 { 1540 struct businfo *bi; 1541 struct intxinfo *ii; 1542 1543 if (pi->pi_lintr.pin == 0) 1544 return; 1545 1546 bi = pci_businfo[pi->pi_bus]; 1547 assert(bi != NULL); 1548 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1549 1550 /* 1551 * Attempt to allocate an I/O APIC pin for this intpin if one 1552 * is not yet assigned. 1553 */ 1554 if (ii->ii_ioapic_irq == 0) 1555 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1556 assert(ii->ii_ioapic_irq > 0); 1557 1558 /* 1559 * Attempt to allocate a PIRQ pin for this intpin if one is 1560 * not yet assigned. 1561 */ 1562 if (ii->ii_pirq_pin == 0) 1563 ii->ii_pirq_pin = pirq_alloc_pin(pi); 1564 assert(ii->ii_pirq_pin > 0); 1565 1566 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1567 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1568 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1569 } 1570 1571 void 1572 pci_lintr_assert(struct pci_devinst *pi) 1573 { 1574 1575 assert(pi->pi_lintr.pin > 0); 1576 1577 pthread_mutex_lock(&pi->pi_lintr.lock); 1578 if (pi->pi_lintr.state == IDLE) { 1579 if (pci_lintr_permitted(pi)) { 1580 pi->pi_lintr.state = ASSERTED; 1581 pci_irq_assert(pi); 1582 } else 1583 pi->pi_lintr.state = PENDING; 1584 } 1585 pthread_mutex_unlock(&pi->pi_lintr.lock); 1586 } 1587 1588 void 1589 pci_lintr_deassert(struct pci_devinst *pi) 1590 { 1591 1592 assert(pi->pi_lintr.pin > 0); 1593 1594 pthread_mutex_lock(&pi->pi_lintr.lock); 1595 if (pi->pi_lintr.state == ASSERTED) { 1596 pi->pi_lintr.state = IDLE; 1597 pci_irq_deassert(pi); 1598 } else if (pi->pi_lintr.state == PENDING) 1599 pi->pi_lintr.state = IDLE; 1600 pthread_mutex_unlock(&pi->pi_lintr.lock); 1601 } 1602 1603 static void 1604 pci_lintr_update(struct pci_devinst *pi) 1605 { 1606 1607 pthread_mutex_lock(&pi->pi_lintr.lock); 1608 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1609 pci_irq_deassert(pi); 1610 pi->pi_lintr.state = PENDING; 1611 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1612 pi->pi_lintr.state = ASSERTED; 1613 pci_irq_assert(pi); 1614 } 1615 pthread_mutex_unlock(&pi->pi_lintr.lock); 1616 #ifndef __FreeBSD__ 1617 if (pi->pi_d->pe_lintrupdate != NULL) { 1618 pi->pi_d->pe_lintrupdate(pi); 1619 } 1620 #endif /* __FreeBSD__ */ 1621 } 1622 1623 int 1624 pci_count_lintr(int bus) 1625 { 1626 int count, slot, pin; 1627 struct slotinfo *slotinfo; 1628 1629 count = 0; 1630 if (pci_businfo[bus] != NULL) { 1631 for (slot = 0; slot < MAXSLOTS; slot++) { 1632 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 1633 for (pin = 0; pin < 4; pin++) { 1634 if (slotinfo->si_intpins[pin].ii_count != 0) 1635 count++; 1636 } 1637 } 1638 } 1639 return (count); 1640 } 1641 1642 void 1643 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 1644 { 1645 struct businfo *bi; 1646 struct slotinfo *si; 1647 struct intxinfo *ii; 1648 int slot, pin; 1649 1650 if ((bi = pci_businfo[bus]) == NULL) 1651 return; 1652 1653 for (slot = 0; slot < MAXSLOTS; slot++) { 1654 si = &bi->slotinfo[slot]; 1655 for (pin = 0; pin < 4; pin++) { 1656 ii = &si->si_intpins[pin]; 1657 if (ii->ii_count != 0) 1658 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 1659 ii->ii_ioapic_irq, arg); 1660 } 1661 } 1662 } 1663 1664 /* 1665 * Return 1 if the emulated device in 'slot' is a multi-function device. 1666 * Return 0 otherwise. 1667 */ 1668 static int 1669 pci_emul_is_mfdev(int bus, int slot) 1670 { 1671 struct businfo *bi; 1672 struct slotinfo *si; 1673 int f, numfuncs; 1674 1675 numfuncs = 0; 1676 if ((bi = pci_businfo[bus]) != NULL) { 1677 si = &bi->slotinfo[slot]; 1678 for (f = 0; f < MAXFUNCS; f++) { 1679 if (si->si_funcs[f].fi_devi != NULL) { 1680 numfuncs++; 1681 } 1682 } 1683 } 1684 return (numfuncs > 1); 1685 } 1686 1687 /* 1688 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1689 * whether or not is a multi-function being emulated in the pci 'slot'. 1690 */ 1691 static void 1692 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 1693 { 1694 int mfdev; 1695 1696 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1697 mfdev = pci_emul_is_mfdev(bus, slot); 1698 switch (bytes) { 1699 case 1: 1700 case 2: 1701 *rv &= ~PCIM_MFDEV; 1702 if (mfdev) { 1703 *rv |= PCIM_MFDEV; 1704 } 1705 break; 1706 case 4: 1707 *rv &= ~(PCIM_MFDEV << 16); 1708 if (mfdev) { 1709 *rv |= (PCIM_MFDEV << 16); 1710 } 1711 break; 1712 } 1713 } 1714 } 1715 1716 /* 1717 * Update device state in response to changes to the PCI command 1718 * register. 1719 */ 1720 void 1721 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 1722 { 1723 int i; 1724 uint16_t changed, new; 1725 1726 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 1727 changed = old ^ new; 1728 1729 /* 1730 * If the MMIO or I/O address space decoding has changed then 1731 * register/unregister all BARs that decode that address space. 1732 */ 1733 for (i = 0; i <= PCI_BARMAX; i++) { 1734 switch (pi->pi_bar[i].type) { 1735 case PCIBAR_NONE: 1736 case PCIBAR_MEMHI64: 1737 break; 1738 case PCIBAR_IO: 1739 /* I/O address space decoding changed? */ 1740 if (changed & PCIM_CMD_PORTEN) { 1741 if (new & PCIM_CMD_PORTEN) 1742 register_bar(pi, i); 1743 else 1744 unregister_bar(pi, i); 1745 } 1746 break; 1747 case PCIBAR_MEM32: 1748 case PCIBAR_MEM64: 1749 /* MMIO address space decoding changed? */ 1750 if (changed & PCIM_CMD_MEMEN) { 1751 if (new & PCIM_CMD_MEMEN) 1752 register_bar(pi, i); 1753 else 1754 unregister_bar(pi, i); 1755 } 1756 break; 1757 default: 1758 assert(0); 1759 } 1760 } 1761 1762 /* 1763 * If INTx has been unmasked and is pending, assert the 1764 * interrupt. 1765 */ 1766 pci_lintr_update(pi); 1767 } 1768 1769 static void 1770 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 1771 { 1772 int rshift; 1773 uint32_t cmd, old, readonly; 1774 1775 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1776 1777 /* 1778 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 1779 * 1780 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 1781 * 'write 1 to clear'. However these bits are not set to '1' by 1782 * any device emulation so it is simpler to treat them as readonly. 1783 */ 1784 rshift = (coff & 0x3) * 8; 1785 readonly = 0xFFFFF880 >> rshift; 1786 1787 old = CFGREAD(pi, coff, bytes); 1788 new &= ~readonly; 1789 new |= (old & readonly); 1790 CFGWRITE(pi, coff, new, bytes); /* update config */ 1791 1792 pci_emul_cmd_changed(pi, cmd); 1793 } 1794 1795 static void 1796 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func, 1797 int coff, int bytes, uint32_t *eax) 1798 { 1799 struct businfo *bi; 1800 struct slotinfo *si; 1801 struct pci_devinst *pi; 1802 struct pci_devemu *pe; 1803 int idx, needcfg; 1804 uint64_t addr, mask; 1805 uint64_t bar = 0; 1806 1807 if ((bi = pci_businfo[bus]) != NULL) { 1808 si = &bi->slotinfo[slot]; 1809 pi = si->si_funcs[func].fi_devi; 1810 } else 1811 pi = NULL; 1812 1813 /* 1814 * Just return if there is no device at this slot:func or if the 1815 * the guest is doing an un-aligned access. 1816 */ 1817 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 1818 (coff & (bytes - 1)) != 0) { 1819 if (in) 1820 *eax = 0xffffffff; 1821 return; 1822 } 1823 1824 /* 1825 * Ignore all writes beyond the standard config space and return all 1826 * ones on reads. 1827 */ 1828 if (coff >= PCI_REGMAX + 1) { 1829 if (in) { 1830 *eax = 0xffffffff; 1831 /* 1832 * Extended capabilities begin at offset 256 in config 1833 * space. Absence of extended capabilities is signaled 1834 * with all 0s in the extended capability header at 1835 * offset 256. 1836 */ 1837 if (coff <= PCI_REGMAX + 4) 1838 *eax = 0x00000000; 1839 } 1840 return; 1841 } 1842 1843 pe = pi->pi_d; 1844 1845 /* 1846 * Config read 1847 */ 1848 if (in) { 1849 /* Let the device emulation override the default handler */ 1850 if (pe->pe_cfgread != NULL) { 1851 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes, 1852 eax); 1853 } else { 1854 needcfg = 1; 1855 } 1856 1857 if (needcfg) 1858 *eax = CFGREAD(pi, coff, bytes); 1859 1860 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax); 1861 } else { 1862 /* Let the device emulation override the default handler */ 1863 if (pe->pe_cfgwrite != NULL && 1864 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1865 return; 1866 1867 /* 1868 * Special handling for write to BAR registers 1869 */ 1870 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1871 /* 1872 * Ignore writes to BAR registers that are not 1873 * 4-byte aligned. 1874 */ 1875 if (bytes != 4 || (coff & 0x3) != 0) 1876 return; 1877 idx = (coff - PCIR_BAR(0)) / 4; 1878 mask = ~(pi->pi_bar[idx].size - 1); 1879 switch (pi->pi_bar[idx].type) { 1880 case PCIBAR_NONE: 1881 pi->pi_bar[idx].addr = bar = 0; 1882 break; 1883 case PCIBAR_IO: 1884 addr = *eax & mask; 1885 addr &= 0xffff; 1886 bar = addr | PCIM_BAR_IO_SPACE; 1887 /* 1888 * Register the new BAR value for interception 1889 */ 1890 if (addr != pi->pi_bar[idx].addr) { 1891 update_bar_address(pi, addr, idx, 1892 PCIBAR_IO); 1893 } 1894 break; 1895 case PCIBAR_MEM32: 1896 addr = bar = *eax & mask; 1897 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1898 if (addr != pi->pi_bar[idx].addr) { 1899 update_bar_address(pi, addr, idx, 1900 PCIBAR_MEM32); 1901 } 1902 break; 1903 case PCIBAR_MEM64: 1904 addr = bar = *eax & mask; 1905 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1906 PCIM_BAR_MEM_PREFETCH; 1907 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1908 update_bar_address(pi, addr, idx, 1909 PCIBAR_MEM64); 1910 } 1911 break; 1912 case PCIBAR_MEMHI64: 1913 mask = ~(pi->pi_bar[idx - 1].size - 1); 1914 addr = ((uint64_t)*eax << 32) & mask; 1915 bar = addr >> 32; 1916 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1917 update_bar_address(pi, addr, idx - 1, 1918 PCIBAR_MEMHI64); 1919 } 1920 break; 1921 default: 1922 assert(0); 1923 } 1924 pci_set_cfgdata32(pi, coff, bar); 1925 1926 } else if (pci_emul_iscap(pi, coff)) { 1927 pci_emul_capwrite(pi, coff, bytes, *eax, 0, 0); 1928 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 1929 pci_emul_cmdsts_write(pi, coff, *eax, bytes); 1930 } else { 1931 CFGWRITE(pi, coff, *eax, bytes); 1932 } 1933 } 1934 } 1935 1936 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 1937 1938 static int 1939 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1940 uint32_t *eax, void *arg) 1941 { 1942 uint32_t x; 1943 1944 if (bytes != 4) { 1945 if (in) 1946 *eax = (bytes == 2) ? 0xffff : 0xff; 1947 return (0); 1948 } 1949 1950 if (in) { 1951 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 1952 if (cfgenable) 1953 x |= CONF1_ENABLE; 1954 *eax = x; 1955 } else { 1956 x = *eax; 1957 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 1958 cfgoff = x & PCI_REGMAX; 1959 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1960 cfgslot = (x >> 11) & PCI_SLOTMAX; 1961 cfgbus = (x >> 16) & PCI_BUSMAX; 1962 } 1963 1964 return (0); 1965 } 1966 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1967 1968 static int 1969 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1970 uint32_t *eax, void *arg) 1971 { 1972 int coff; 1973 1974 assert(bytes == 1 || bytes == 2 || bytes == 4); 1975 1976 coff = cfgoff + (port - CONF1_DATA_PORT); 1977 if (cfgenable) { 1978 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes, 1979 eax); 1980 } else { 1981 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 1982 if (in) 1983 *eax = 0xffffffff; 1984 } 1985 return (0); 1986 } 1987 1988 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1989 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1990 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1991 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1992 1993 #define PCI_EMUL_TEST 1994 #ifdef PCI_EMUL_TEST 1995 /* 1996 * Define a dummy test device 1997 */ 1998 #define DIOSZ 8 1999 #define DMEMSZ 4096 2000 struct pci_emul_dsoftc { 2001 uint8_t ioregs[DIOSZ]; 2002 uint8_t memregs[2][DMEMSZ]; 2003 }; 2004 2005 #define PCI_EMUL_MSI_MSGS 4 2006 #define PCI_EMUL_MSIX_MSGS 16 2007 2008 static int 2009 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2010 { 2011 int error; 2012 struct pci_emul_dsoftc *sc; 2013 2014 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 2015 2016 pi->pi_arg = sc; 2017 2018 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 2019 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 2020 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 2021 2022 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 2023 assert(error == 0); 2024 2025 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 2026 assert(error == 0); 2027 2028 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2029 assert(error == 0); 2030 2031 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2032 assert(error == 0); 2033 2034 return (0); 2035 } 2036 2037 static void 2038 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2039 uint64_t offset, int size, uint64_t value) 2040 { 2041 int i; 2042 struct pci_emul_dsoftc *sc = pi->pi_arg; 2043 2044 if (baridx == 0) { 2045 if (offset + size > DIOSZ) { 2046 printf("diow: iow too large, offset %ld size %d\n", 2047 offset, size); 2048 return; 2049 } 2050 2051 if (size == 1) { 2052 sc->ioregs[offset] = value & 0xff; 2053 } else if (size == 2) { 2054 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2055 } else if (size == 4) { 2056 *(uint32_t *)&sc->ioregs[offset] = value; 2057 } else { 2058 printf("diow: iow unknown size %d\n", size); 2059 } 2060 2061 /* 2062 * Special magic value to generate an interrupt 2063 */ 2064 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2065 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2066 2067 if (value == 0xabcdef) { 2068 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2069 pci_generate_msi(pi, i); 2070 } 2071 } 2072 2073 if (baridx == 1 || baridx == 2) { 2074 if (offset + size > DMEMSZ) { 2075 printf("diow: memw too large, offset %ld size %d\n", 2076 offset, size); 2077 return; 2078 } 2079 2080 i = baridx - 1; /* 'memregs' index */ 2081 2082 if (size == 1) { 2083 sc->memregs[i][offset] = value; 2084 } else if (size == 2) { 2085 *(uint16_t *)&sc->memregs[i][offset] = value; 2086 } else if (size == 4) { 2087 *(uint32_t *)&sc->memregs[i][offset] = value; 2088 } else if (size == 8) { 2089 *(uint64_t *)&sc->memregs[i][offset] = value; 2090 } else { 2091 printf("diow: memw unknown size %d\n", size); 2092 } 2093 2094 /* 2095 * magic interrupt ?? 2096 */ 2097 } 2098 2099 if (baridx > 2 || baridx < 0) { 2100 printf("diow: unknown bar idx %d\n", baridx); 2101 } 2102 } 2103 2104 static uint64_t 2105 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2106 uint64_t offset, int size) 2107 { 2108 struct pci_emul_dsoftc *sc = pi->pi_arg; 2109 uint32_t value; 2110 int i; 2111 2112 value = 0; 2113 if (baridx == 0) { 2114 if (offset + size > DIOSZ) { 2115 printf("dior: ior too large, offset %ld size %d\n", 2116 offset, size); 2117 return (0); 2118 } 2119 2120 value = 0; 2121 if (size == 1) { 2122 value = sc->ioregs[offset]; 2123 } else if (size == 2) { 2124 value = *(uint16_t *) &sc->ioregs[offset]; 2125 } else if (size == 4) { 2126 value = *(uint32_t *) &sc->ioregs[offset]; 2127 } else { 2128 printf("dior: ior unknown size %d\n", size); 2129 } 2130 } 2131 2132 if (baridx == 1 || baridx == 2) { 2133 if (offset + size > DMEMSZ) { 2134 printf("dior: memr too large, offset %ld size %d\n", 2135 offset, size); 2136 return (0); 2137 } 2138 2139 i = baridx - 1; /* 'memregs' index */ 2140 2141 if (size == 1) { 2142 value = sc->memregs[i][offset]; 2143 } else if (size == 2) { 2144 value = *(uint16_t *) &sc->memregs[i][offset]; 2145 } else if (size == 4) { 2146 value = *(uint32_t *) &sc->memregs[i][offset]; 2147 } else if (size == 8) { 2148 value = *(uint64_t *) &sc->memregs[i][offset]; 2149 } else { 2150 printf("dior: ior unknown size %d\n", size); 2151 } 2152 } 2153 2154 2155 if (baridx > 2 || baridx < 0) { 2156 printf("dior: unknown bar idx %d\n", baridx); 2157 return (0); 2158 } 2159 2160 return (value); 2161 } 2162 2163 struct pci_devemu pci_dummy = { 2164 .pe_emu = "dummy", 2165 .pe_init = pci_emul_dinit, 2166 .pe_barwrite = pci_emul_diow, 2167 .pe_barread = pci_emul_dior 2168 }; 2169 PCI_EMUL_SET(pci_dummy); 2170 2171 #endif /* PCI_EMUL_TEST */ 2172