1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * This file and its contents are supplied under the terms of the 32 * Common Development and Distribution License ("CDDL"), version 1.0. 33 * You may only use this file in accordance with the terms of version 34 * 1.0 of the CDDL. 35 * 36 * A full copy of the text of the CDDL should have accompanied this 37 * source. A copy of the CDDL is also available via the Internet at 38 * http://www.illumos.org/license/CDDL. 39 * 40 * Copyright 2014 Pluribus Networks Inc. 41 * Copyright 2018 Joyent, Inc. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/param.h> 48 #include <sys/linker_set.h> 49 50 #include <ctype.h> 51 #include <errno.h> 52 #include <pthread.h> 53 #include <stdio.h> 54 #include <stdlib.h> 55 #include <string.h> 56 #include <strings.h> 57 #include <assert.h> 58 #include <stdbool.h> 59 60 #include <machine/vmm.h> 61 #include <vmmapi.h> 62 63 #include "acpi.h" 64 #include "bhyverun.h" 65 #include "config.h" 66 #include "debug.h" 67 #include "inout.h" 68 #include "ioapic.h" 69 #include "mem.h" 70 #include "pci_emul.h" 71 #include "pci_irq.h" 72 #include "pci_lpc.h" 73 74 #define CONF1_ADDR_PORT 0x0cf8 75 #define CONF1_DATA_PORT 0x0cfc 76 77 #define CONF1_ENABLE 0x80000000ul 78 79 #define MAXBUSES (PCI_BUSMAX + 1) 80 #define MAXSLOTS (PCI_SLOTMAX + 1) 81 #define MAXFUNCS (PCI_FUNCMAX + 1) 82 83 struct funcinfo { 84 nvlist_t *fi_config; 85 struct pci_devemu *fi_pde; 86 struct pci_devinst *fi_devi; 87 }; 88 89 struct intxinfo { 90 int ii_count; 91 int ii_pirq_pin; 92 int ii_ioapic_irq; 93 }; 94 95 struct slotinfo { 96 struct intxinfo si_intpins[4]; 97 struct funcinfo si_funcs[MAXFUNCS]; 98 }; 99 100 struct businfo { 101 uint16_t iobase, iolimit; /* I/O window */ 102 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 103 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 104 struct slotinfo slotinfo[MAXSLOTS]; 105 }; 106 107 static struct businfo *pci_businfo[MAXBUSES]; 108 109 SET_DECLARE(pci_devemu_set, struct pci_devemu); 110 111 static uint64_t pci_emul_iobase; 112 static uint64_t pci_emul_membase32; 113 static uint64_t pci_emul_membase64; 114 115 #define PCI_EMUL_IOBASE 0x2000 116 #define PCI_EMUL_IOLIMIT 0x10000 117 118 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 119 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 120 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 121 122 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 123 124 #define PCI_EMUL_MEMBASE64 0xD000000000UL 125 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 126 127 static struct pci_devemu *pci_emul_finddev(const char *name); 128 static void pci_lintr_route(struct pci_devinst *pi); 129 static void pci_lintr_update(struct pci_devinst *pi); 130 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, 131 int func, int coff, int bytes, uint32_t *val); 132 133 static __inline void 134 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 135 { 136 137 if (bytes == 1) 138 pci_set_cfgdata8(pi, coff, val); 139 else if (bytes == 2) 140 pci_set_cfgdata16(pi, coff, val); 141 else 142 pci_set_cfgdata32(pi, coff, val); 143 } 144 145 static __inline uint32_t 146 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 147 { 148 149 if (bytes == 1) 150 return (pci_get_cfgdata8(pi, coff)); 151 else if (bytes == 2) 152 return (pci_get_cfgdata16(pi, coff)); 153 else 154 return (pci_get_cfgdata32(pi, coff)); 155 } 156 157 /* 158 * I/O access 159 */ 160 161 /* 162 * Slot options are in the form: 163 * 164 * <bus>:<slot>:<func>,<emul>[,<config>] 165 * <slot>[:<func>],<emul>[,<config>] 166 * 167 * slot is 0..31 168 * func is 0..7 169 * emul is a string describing the type of PCI device e.g. virtio-net 170 * config is an optional string, depending on the device, that can be 171 * used for configuration. 172 * Examples are: 173 * 1,virtio-net,tap0 174 * 3:0,dummy 175 */ 176 static void 177 pci_parse_slot_usage(char *aopt) 178 { 179 180 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt); 181 } 182 183 /* 184 * Helper function to parse a list of comma-separated options where 185 * each option is formatted as "name[=value]". If no value is 186 * provided, the option is treated as a boolean and is given a value 187 * of true. 188 */ 189 int 190 pci_parse_legacy_config(nvlist_t *nvl, const char *opt) 191 { 192 char *config, *name, *tofree, *value; 193 194 if (opt == NULL) 195 return (0); 196 197 config = tofree = strdup(opt); 198 while ((name = strsep(&config, ",")) != NULL) { 199 value = strchr(name, '='); 200 if (value != NULL) { 201 *value = '\0'; 202 value++; 203 set_config_value_node(nvl, name, value); 204 } else 205 set_config_bool_node(nvl, name, true); 206 } 207 free(tofree); 208 return (0); 209 } 210 211 /* 212 * PCI device configuration is stored in MIBs that encode the device's 213 * location: 214 * 215 * pci.<bus>.<slot>.<func> 216 * 217 * Where "bus", "slot", and "func" are all decimal values without 218 * leading zeroes. Each valid device must have a "device" node which 219 * identifies the driver model of the device. 220 * 221 * Device backends can provide a parser for the "config" string. If 222 * a custom parser is not provided, pci_parse_legacy_config() is used 223 * to parse the string. 224 */ 225 int 226 pci_parse_slot(char *opt) 227 { 228 char node_name[sizeof("pci.XXX.XX.X")]; 229 struct pci_devemu *pde; 230 char *emul, *config, *str, *cp; 231 int error, bnum, snum, fnum; 232 nvlist_t *nvl; 233 234 error = -1; 235 str = strdup(opt); 236 237 emul = config = NULL; 238 if ((cp = strchr(str, ',')) != NULL) { 239 *cp = '\0'; 240 emul = cp + 1; 241 if ((cp = strchr(emul, ',')) != NULL) { 242 *cp = '\0'; 243 config = cp + 1; 244 } 245 } else { 246 pci_parse_slot_usage(opt); 247 goto done; 248 } 249 250 /* <bus>:<slot>:<func> */ 251 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 252 bnum = 0; 253 /* <slot>:<func> */ 254 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 255 fnum = 0; 256 /* <slot> */ 257 if (sscanf(str, "%d", &snum) != 1) { 258 snum = -1; 259 } 260 } 261 } 262 263 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 264 fnum < 0 || fnum >= MAXFUNCS) { 265 pci_parse_slot_usage(opt); 266 goto done; 267 } 268 269 pde = pci_emul_finddev(emul); 270 if (pde == NULL) { 271 EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum, 272 fnum, emul); 273 goto done; 274 } 275 276 snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum, 277 fnum); 278 nvl = find_config_node(node_name); 279 if (nvl != NULL) { 280 EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum, 281 fnum); 282 goto done; 283 } 284 nvl = create_config_node(node_name); 285 if (pde->pe_alias != NULL) 286 set_config_value_node(nvl, "device", pde->pe_alias); 287 else 288 set_config_value_node(nvl, "device", pde->pe_emu); 289 290 if (pde->pe_legacy_config != NULL) 291 error = pde->pe_legacy_config(nvl, config); 292 else 293 error = pci_parse_legacy_config(nvl, config); 294 done: 295 free(str); 296 return (error); 297 } 298 299 void 300 pci_print_supported_devices() 301 { 302 struct pci_devemu **pdpp, *pdp; 303 304 SET_FOREACH(pdpp, pci_devemu_set) { 305 pdp = *pdpp; 306 printf("%s\n", pdp->pe_emu); 307 } 308 } 309 310 static int 311 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 312 { 313 314 if (offset < pi->pi_msix.pba_offset) 315 return (0); 316 317 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 318 return (0); 319 } 320 321 return (1); 322 } 323 324 int 325 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 326 uint64_t value) 327 { 328 int msix_entry_offset; 329 int tab_index; 330 char *dest; 331 332 /* support only 4 or 8 byte writes */ 333 if (size != 4 && size != 8) 334 return (-1); 335 336 /* 337 * Return if table index is beyond what device supports 338 */ 339 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 340 if (tab_index >= pi->pi_msix.table_count) 341 return (-1); 342 343 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 344 345 /* support only aligned writes */ 346 if ((msix_entry_offset % size) != 0) 347 return (-1); 348 349 dest = (char *)(pi->pi_msix.table + tab_index); 350 dest += msix_entry_offset; 351 352 if (size == 4) 353 *((uint32_t *)dest) = value; 354 else 355 *((uint64_t *)dest) = value; 356 357 return (0); 358 } 359 360 uint64_t 361 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 362 { 363 char *dest; 364 int msix_entry_offset; 365 int tab_index; 366 uint64_t retval = ~0; 367 368 /* 369 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 370 * table but we also allow 1 byte access to accommodate reads from 371 * ddb. 372 */ 373 if (size != 1 && size != 4 && size != 8) 374 return (retval); 375 376 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 377 378 /* support only aligned reads */ 379 if ((msix_entry_offset % size) != 0) { 380 return (retval); 381 } 382 383 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 384 385 if (tab_index < pi->pi_msix.table_count) { 386 /* valid MSI-X Table access */ 387 dest = (char *)(pi->pi_msix.table + tab_index); 388 dest += msix_entry_offset; 389 390 if (size == 1) 391 retval = *((uint8_t *)dest); 392 else if (size == 4) 393 retval = *((uint32_t *)dest); 394 else 395 retval = *((uint64_t *)dest); 396 } else if (pci_valid_pba_offset(pi, offset)) { 397 /* return 0 for PBA access */ 398 retval = 0; 399 } 400 401 return (retval); 402 } 403 404 int 405 pci_msix_table_bar(struct pci_devinst *pi) 406 { 407 408 if (pi->pi_msix.table != NULL) 409 return (pi->pi_msix.table_bar); 410 else 411 return (-1); 412 } 413 414 int 415 pci_msix_pba_bar(struct pci_devinst *pi) 416 { 417 418 if (pi->pi_msix.table != NULL) 419 return (pi->pi_msix.pba_bar); 420 else 421 return (-1); 422 } 423 424 static int 425 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 426 uint32_t *eax, void *arg) 427 { 428 struct pci_devinst *pdi = arg; 429 struct pci_devemu *pe = pdi->pi_d; 430 uint64_t offset; 431 int i; 432 433 for (i = 0; i <= PCI_BARMAX; i++) { 434 if (pdi->pi_bar[i].type == PCIBAR_IO && 435 port >= pdi->pi_bar[i].addr && 436 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 437 offset = port - pdi->pi_bar[i].addr; 438 if (in) 439 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 440 offset, bytes); 441 else 442 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 443 bytes, *eax); 444 return (0); 445 } 446 } 447 return (-1); 448 } 449 450 static int 451 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 452 int size, uint64_t *val, void *arg1, long arg2) 453 { 454 struct pci_devinst *pdi = arg1; 455 struct pci_devemu *pe = pdi->pi_d; 456 uint64_t offset; 457 int bidx = (int) arg2; 458 459 assert(bidx <= PCI_BARMAX); 460 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 461 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 462 assert(addr >= pdi->pi_bar[bidx].addr && 463 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 464 465 offset = addr - pdi->pi_bar[bidx].addr; 466 467 if (dir == MEM_F_WRITE) { 468 if (size == 8) { 469 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 470 4, *val & 0xffffffff); 471 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4, 472 4, *val >> 32); 473 } else { 474 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 475 size, *val); 476 } 477 } else { 478 if (size == 8) { 479 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 480 offset, 4); 481 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 482 offset + 4, 4) << 32; 483 } else { 484 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 485 offset, size); 486 } 487 } 488 489 return (0); 490 } 491 492 493 static int 494 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 495 uint64_t *addr) 496 { 497 uint64_t base; 498 499 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 500 501 base = roundup2(*baseptr, size); 502 503 if (base + size <= limit) { 504 *addr = base; 505 *baseptr = base + size; 506 return (0); 507 } else 508 return (-1); 509 } 510 511 /* 512 * Register (or unregister) the MMIO or I/O region associated with the BAR 513 * register 'idx' of an emulated pci device. 514 */ 515 static void 516 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 517 { 518 struct pci_devemu *pe; 519 int error; 520 struct inout_port iop; 521 struct mem_range mr; 522 523 pe = pi->pi_d; 524 switch (pi->pi_bar[idx].type) { 525 case PCIBAR_IO: 526 bzero(&iop, sizeof(struct inout_port)); 527 iop.name = pi->pi_name; 528 iop.port = pi->pi_bar[idx].addr; 529 iop.size = pi->pi_bar[idx].size; 530 if (registration) { 531 iop.flags = IOPORT_F_INOUT; 532 iop.handler = pci_emul_io_handler; 533 iop.arg = pi; 534 error = register_inout(&iop); 535 } else 536 error = unregister_inout(&iop); 537 if (pe->pe_baraddr != NULL) 538 (*pe->pe_baraddr)(pi->pi_vmctx, pi, idx, registration, 539 pi->pi_bar[idx].addr); 540 break; 541 case PCIBAR_MEM32: 542 case PCIBAR_MEM64: 543 bzero(&mr, sizeof(struct mem_range)); 544 mr.name = pi->pi_name; 545 mr.base = pi->pi_bar[idx].addr; 546 mr.size = pi->pi_bar[idx].size; 547 if (registration) { 548 mr.flags = MEM_F_RW; 549 mr.handler = pci_emul_mem_handler; 550 mr.arg1 = pi; 551 mr.arg2 = idx; 552 error = register_mem(&mr); 553 } else 554 error = unregister_mem(&mr); 555 if (pe->pe_baraddr != NULL) 556 (*pe->pe_baraddr)(pi->pi_vmctx, pi, idx, registration, 557 pi->pi_bar[idx].addr); 558 break; 559 default: 560 error = EINVAL; 561 break; 562 } 563 assert(error == 0); 564 } 565 566 static void 567 unregister_bar(struct pci_devinst *pi, int idx) 568 { 569 570 modify_bar_registration(pi, idx, 0); 571 } 572 573 static void 574 register_bar(struct pci_devinst *pi, int idx) 575 { 576 577 modify_bar_registration(pi, idx, 1); 578 } 579 580 /* Are we decoding i/o port accesses for the emulated pci device? */ 581 static int 582 porten(struct pci_devinst *pi) 583 { 584 uint16_t cmd; 585 586 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 587 588 return (cmd & PCIM_CMD_PORTEN); 589 } 590 591 /* Are we decoding memory accesses for the emulated pci device? */ 592 static int 593 memen(struct pci_devinst *pi) 594 { 595 uint16_t cmd; 596 597 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 598 599 return (cmd & PCIM_CMD_MEMEN); 600 } 601 602 /* 603 * Update the MMIO or I/O address that is decoded by the BAR register. 604 * 605 * If the pci device has enabled the address space decoding then intercept 606 * the address range decoded by the BAR register. 607 */ 608 static void 609 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 610 { 611 int decode; 612 613 if (pi->pi_bar[idx].type == PCIBAR_IO) 614 decode = porten(pi); 615 else 616 decode = memen(pi); 617 618 if (decode) 619 unregister_bar(pi, idx); 620 621 switch (type) { 622 case PCIBAR_IO: 623 case PCIBAR_MEM32: 624 pi->pi_bar[idx].addr = addr; 625 break; 626 case PCIBAR_MEM64: 627 pi->pi_bar[idx].addr &= ~0xffffffffUL; 628 pi->pi_bar[idx].addr |= addr; 629 break; 630 case PCIBAR_MEMHI64: 631 pi->pi_bar[idx].addr &= 0xffffffff; 632 pi->pi_bar[idx].addr |= addr; 633 break; 634 default: 635 assert(0); 636 } 637 638 if (decode) 639 register_bar(pi, idx); 640 } 641 642 int 643 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 644 uint64_t size) 645 { 646 uint64_t *baseptr = NULL; 647 uint64_t limit = 0, lobits = 0; 648 uint64_t addr, mask, bar; 649 uint16_t cmd, enbit; 650 int error; 651 652 assert(idx >= 0 && idx <= PCI_BARMAX); 653 654 if ((size & (size - 1)) != 0) 655 size = 1UL << flsl(size); /* round up to a power of 2 */ 656 657 /* Enforce minimum BAR sizes required by the PCI standard */ 658 if (type == PCIBAR_IO) { 659 if (size < 4) 660 size = 4; 661 } else { 662 if (size < 16) 663 size = 16; 664 } 665 666 switch (type) { 667 case PCIBAR_NONE: 668 baseptr = NULL; 669 addr = mask = lobits = enbit = 0; 670 break; 671 case PCIBAR_IO: 672 baseptr = &pci_emul_iobase; 673 limit = PCI_EMUL_IOLIMIT; 674 mask = PCIM_BAR_IO_BASE; 675 lobits = PCIM_BAR_IO_SPACE; 676 enbit = PCIM_CMD_PORTEN; 677 break; 678 case PCIBAR_MEM64: 679 /* 680 * XXX 681 * Some drivers do not work well if the 64-bit BAR is allocated 682 * above 4GB. Allow for this by allocating small requests under 683 * 4GB unless then allocation size is larger than some arbitrary 684 * number (128MB currently). 685 */ 686 if (size > 128 * 1024 * 1024) { 687 baseptr = &pci_emul_membase64; 688 limit = PCI_EMUL_MEMLIMIT64; 689 mask = PCIM_BAR_MEM_BASE; 690 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 691 PCIM_BAR_MEM_PREFETCH; 692 } else { 693 baseptr = &pci_emul_membase32; 694 limit = PCI_EMUL_MEMLIMIT32; 695 mask = PCIM_BAR_MEM_BASE; 696 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 697 } 698 enbit = PCIM_CMD_MEMEN; 699 break; 700 case PCIBAR_MEM32: 701 baseptr = &pci_emul_membase32; 702 limit = PCI_EMUL_MEMLIMIT32; 703 mask = PCIM_BAR_MEM_BASE; 704 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 705 enbit = PCIM_CMD_MEMEN; 706 break; 707 default: 708 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 709 #ifdef FreeBSD 710 assert(0); 711 #else 712 abort(); 713 #endif 714 } 715 716 if (baseptr != NULL) { 717 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 718 if (error != 0) 719 return (error); 720 } 721 722 pdi->pi_bar[idx].type = type; 723 pdi->pi_bar[idx].addr = addr; 724 pdi->pi_bar[idx].size = size; 725 726 /* Initialize the BAR register in config space */ 727 bar = (addr & mask) | lobits; 728 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 729 730 if (type == PCIBAR_MEM64) { 731 assert(idx + 1 <= PCI_BARMAX); 732 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 733 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 734 } 735 736 cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 737 if ((cmd & enbit) != enbit) 738 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 739 register_bar(pdi, idx); 740 741 return (0); 742 } 743 744 #define CAP_START_OFFSET 0x40 745 static int 746 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 747 { 748 int i, capoff, reallen; 749 uint16_t sts; 750 751 assert(caplen > 0); 752 753 reallen = roundup2(caplen, 4); /* dword aligned */ 754 755 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 756 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 757 capoff = CAP_START_OFFSET; 758 else 759 capoff = pi->pi_capend + 1; 760 761 /* Check if we have enough space */ 762 if (capoff + reallen > PCI_REGMAX + 1) 763 return (-1); 764 765 /* Set the previous capability pointer */ 766 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 767 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 768 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 769 } else 770 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 771 772 /* Copy the capability */ 773 for (i = 0; i < caplen; i++) 774 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 775 776 /* Set the next capability pointer */ 777 pci_set_cfgdata8(pi, capoff + 1, 0); 778 779 pi->pi_prevcap = capoff; 780 pi->pi_capend = capoff + reallen - 1; 781 return (0); 782 } 783 784 static struct pci_devemu * 785 pci_emul_finddev(const char *name) 786 { 787 struct pci_devemu **pdpp, *pdp; 788 789 SET_FOREACH(pdpp, pci_devemu_set) { 790 pdp = *pdpp; 791 if (!strcmp(pdp->pe_emu, name)) { 792 return (pdp); 793 } 794 } 795 796 return (NULL); 797 } 798 799 static int 800 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 801 int func, struct funcinfo *fi) 802 { 803 struct pci_devinst *pdi; 804 int err; 805 806 pdi = calloc(1, sizeof(struct pci_devinst)); 807 808 pdi->pi_vmctx = ctx; 809 pdi->pi_bus = bus; 810 pdi->pi_slot = slot; 811 pdi->pi_func = func; 812 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 813 pdi->pi_lintr.pin = 0; 814 pdi->pi_lintr.state = IDLE; 815 pdi->pi_lintr.pirq_pin = 0; 816 pdi->pi_lintr.ioapic_irq = 0; 817 pdi->pi_d = pde; 818 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 819 820 /* Disable legacy interrupts */ 821 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 822 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 823 824 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 825 826 err = (*pde->pe_init)(ctx, pdi, fi->fi_config); 827 if (err == 0) 828 fi->fi_devi = pdi; 829 else 830 free(pdi); 831 832 return (err); 833 } 834 835 void 836 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 837 { 838 int mmc; 839 840 /* Number of msi messages must be a power of 2 between 1 and 32 */ 841 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 842 mmc = ffs(msgnum) - 1; 843 844 bzero(msicap, sizeof(struct msicap)); 845 msicap->capid = PCIY_MSI; 846 msicap->nextptr = nextptr; 847 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 848 } 849 850 int 851 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 852 { 853 struct msicap msicap; 854 855 pci_populate_msicap(&msicap, msgnum, 0); 856 857 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 858 } 859 860 static void 861 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 862 uint32_t msix_tab_size) 863 { 864 865 assert(msix_tab_size % 4096 == 0); 866 867 bzero(msixcap, sizeof(struct msixcap)); 868 msixcap->capid = PCIY_MSIX; 869 870 /* 871 * Message Control Register, all fields set to 872 * zero except for the Table Size. 873 * Note: Table size N is encoded as N-1 874 */ 875 msixcap->msgctrl = msgnum - 1; 876 877 /* 878 * MSI-X BAR setup: 879 * - MSI-X table start at offset 0 880 * - PBA table starts at a 4K aligned offset after the MSI-X table 881 */ 882 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 883 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 884 } 885 886 static void 887 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 888 { 889 int i, table_size; 890 891 assert(table_entries > 0); 892 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 893 894 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 895 pi->pi_msix.table = calloc(1, table_size); 896 897 /* set mask bit of vector control register */ 898 for (i = 0; i < table_entries; i++) 899 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 900 } 901 902 int 903 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 904 { 905 uint32_t tab_size; 906 struct msixcap msixcap; 907 908 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 909 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 910 911 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 912 913 /* Align table size to nearest 4K */ 914 tab_size = roundup2(tab_size, 4096); 915 916 pi->pi_msix.table_bar = barnum; 917 pi->pi_msix.pba_bar = barnum; 918 pi->pi_msix.table_offset = 0; 919 pi->pi_msix.table_count = msgnum; 920 pi->pi_msix.pba_offset = tab_size; 921 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 922 923 pci_msix_table_init(pi, msgnum); 924 925 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 926 927 /* allocate memory for MSI-X Table and PBA */ 928 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 929 tab_size + pi->pi_msix.pba_size); 930 931 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 932 sizeof(msixcap))); 933 } 934 935 static void 936 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 937 int bytes, uint32_t val) 938 { 939 uint16_t msgctrl, rwmask; 940 int off; 941 942 off = offset - capoff; 943 /* Message Control Register */ 944 if (off == 2 && bytes == 2) { 945 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 946 msgctrl = pci_get_cfgdata16(pi, offset); 947 msgctrl &= ~rwmask; 948 msgctrl |= val & rwmask; 949 val = msgctrl; 950 951 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 952 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 953 pci_lintr_update(pi); 954 } 955 956 CFGWRITE(pi, offset, val, bytes); 957 } 958 959 static void 960 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 961 int bytes, uint32_t val) 962 { 963 uint16_t msgctrl, rwmask, msgdata, mme; 964 uint32_t addrlo; 965 966 /* 967 * If guest is writing to the message control register make sure 968 * we do not overwrite read-only fields. 969 */ 970 if ((offset - capoff) == 2 && bytes == 2) { 971 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 972 msgctrl = pci_get_cfgdata16(pi, offset); 973 msgctrl &= ~rwmask; 974 msgctrl |= val & rwmask; 975 val = msgctrl; 976 } 977 CFGWRITE(pi, offset, val, bytes); 978 979 msgctrl = pci_get_cfgdata16(pi, capoff + 2); 980 addrlo = pci_get_cfgdata32(pi, capoff + 4); 981 if (msgctrl & PCIM_MSICTRL_64BIT) 982 msgdata = pci_get_cfgdata16(pi, capoff + 12); 983 else 984 msgdata = pci_get_cfgdata16(pi, capoff + 8); 985 986 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 987 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 988 if (pi->pi_msi.enabled) { 989 pi->pi_msi.addr = addrlo; 990 pi->pi_msi.msg_data = msgdata; 991 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 992 } else { 993 pi->pi_msi.maxmsgnum = 0; 994 } 995 pci_lintr_update(pi); 996 } 997 998 void 999 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1000 int bytes, uint32_t val) 1001 { 1002 1003 /* XXX don't write to the readonly parts */ 1004 CFGWRITE(pi, offset, val, bytes); 1005 } 1006 1007 #define PCIECAP_VERSION 0x2 1008 int 1009 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 1010 { 1011 int err; 1012 struct pciecap pciecap; 1013 1014 bzero(&pciecap, sizeof(pciecap)); 1015 1016 /* 1017 * Use the integrated endpoint type for endpoints on a root complex bus. 1018 * 1019 * NB: bhyve currently only supports a single PCI bus that is the root 1020 * complex bus, so all endpoints are integrated. 1021 */ 1022 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 1023 type = PCIEM_TYPE_ROOT_INT_EP; 1024 1025 pciecap.capid = PCIY_EXPRESS; 1026 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 1027 if (type != PCIEM_TYPE_ROOT_INT_EP) { 1028 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 1029 pciecap.link_status = 0x11; /* gen1, x1 */ 1030 } 1031 1032 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 1033 return (err); 1034 } 1035 1036 /* 1037 * This function assumes that 'coff' is in the capabilities region of the 1038 * config space. A capoff parameter of zero will force a search for the 1039 * offset and type. 1040 */ 1041 void 1042 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val, 1043 uint8_t capoff, int capid) 1044 { 1045 uint8_t nextoff; 1046 1047 /* Do not allow un-aligned writes */ 1048 if ((offset & (bytes - 1)) != 0) 1049 return; 1050 1051 if (capoff == 0) { 1052 /* Find the capability that we want to update */ 1053 capoff = CAP_START_OFFSET; 1054 while (1) { 1055 nextoff = pci_get_cfgdata8(pi, capoff + 1); 1056 if (nextoff == 0) 1057 break; 1058 if (offset >= capoff && offset < nextoff) 1059 break; 1060 1061 capoff = nextoff; 1062 } 1063 assert(offset >= capoff); 1064 capid = pci_get_cfgdata8(pi, capoff); 1065 } 1066 1067 /* 1068 * Capability ID and Next Capability Pointer are readonly. 1069 * However, some o/s's do 4-byte writes that include these. 1070 * For this case, trim the write back to 2 bytes and adjust 1071 * the data. 1072 */ 1073 if (offset == capoff || offset == capoff + 1) { 1074 if (offset == capoff && bytes == 4) { 1075 bytes = 2; 1076 offset += 2; 1077 val >>= 16; 1078 } else 1079 return; 1080 } 1081 1082 switch (capid) { 1083 case PCIY_MSI: 1084 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1085 break; 1086 case PCIY_MSIX: 1087 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1088 break; 1089 case PCIY_EXPRESS: 1090 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1091 break; 1092 default: 1093 break; 1094 } 1095 } 1096 1097 static int 1098 pci_emul_iscap(struct pci_devinst *pi, int offset) 1099 { 1100 uint16_t sts; 1101 1102 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1103 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1104 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1105 return (1); 1106 } 1107 return (0); 1108 } 1109 1110 static int 1111 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1112 int size, uint64_t *val, void *arg1, long arg2) 1113 { 1114 /* 1115 * Ignore writes; return 0xff's for reads. The mem read code 1116 * will take care of truncating to the correct size. 1117 */ 1118 if (dir == MEM_F_READ) { 1119 *val = 0xffffffffffffffff; 1120 } 1121 1122 return (0); 1123 } 1124 1125 static int 1126 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1127 int bytes, uint64_t *val, void *arg1, long arg2) 1128 { 1129 int bus, slot, func, coff, in; 1130 1131 coff = addr & 0xfff; 1132 func = (addr >> 12) & 0x7; 1133 slot = (addr >> 15) & 0x1f; 1134 bus = (addr >> 20) & 0xff; 1135 in = (dir == MEM_F_READ); 1136 if (in) 1137 *val = ~0UL; 1138 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val); 1139 return (0); 1140 } 1141 1142 uint64_t 1143 pci_ecfg_base(void) 1144 { 1145 1146 return (PCI_EMUL_ECFG_BASE); 1147 } 1148 1149 #define BUSIO_ROUNDUP 32 1150 #define BUSMEM_ROUNDUP (1024 * 1024) 1151 1152 int 1153 init_pci(struct vmctx *ctx) 1154 { 1155 char node_name[sizeof("pci.XXX.XX.X")]; 1156 struct mem_range mr; 1157 struct pci_devemu *pde; 1158 struct businfo *bi; 1159 struct slotinfo *si; 1160 struct funcinfo *fi; 1161 nvlist_t *nvl; 1162 const char *emul; 1163 size_t lowmem; 1164 int bus, slot, func; 1165 int error; 1166 1167 pci_emul_iobase = PCI_EMUL_IOBASE; 1168 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1169 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1170 1171 for (bus = 0; bus < MAXBUSES; bus++) { 1172 snprintf(node_name, sizeof(node_name), "pci.%d", bus); 1173 nvl = find_config_node(node_name); 1174 if (nvl == NULL) 1175 continue; 1176 pci_businfo[bus] = calloc(1, sizeof(struct businfo)); 1177 bi = pci_businfo[bus]; 1178 1179 /* 1180 * Keep track of the i/o and memory resources allocated to 1181 * this bus. 1182 */ 1183 bi->iobase = pci_emul_iobase; 1184 bi->membase32 = pci_emul_membase32; 1185 bi->membase64 = pci_emul_membase64; 1186 1187 for (slot = 0; slot < MAXSLOTS; slot++) { 1188 si = &bi->slotinfo[slot]; 1189 for (func = 0; func < MAXFUNCS; func++) { 1190 fi = &si->si_funcs[func]; 1191 snprintf(node_name, sizeof(node_name), 1192 "pci.%d.%d.%d", bus, slot, func); 1193 nvl = find_config_node(node_name); 1194 if (nvl == NULL) 1195 continue; 1196 1197 fi->fi_config = nvl; 1198 emul = get_config_value_node(nvl, "device"); 1199 if (emul == NULL) { 1200 EPRINTLN("pci slot %d:%d:%d: missing " 1201 "\"device\" value", bus, slot, func); 1202 return (EINVAL); 1203 } 1204 pde = pci_emul_finddev(emul); 1205 if (pde == NULL) { 1206 EPRINTLN("pci slot %d:%d:%d: unknown " 1207 "device \"%s\"", bus, slot, func, 1208 emul); 1209 return (EINVAL); 1210 } 1211 if (pde->pe_alias != NULL) { 1212 EPRINTLN("pci slot %d:%d:%d: legacy " 1213 "device \"%s\", use \"%s\" instead", 1214 bus, slot, func, emul, 1215 pde->pe_alias); 1216 return (EINVAL); 1217 } 1218 fi->fi_pde = pde; 1219 error = pci_emul_init(ctx, pde, bus, slot, 1220 func, fi); 1221 if (error) 1222 return (error); 1223 } 1224 } 1225 1226 /* 1227 * Add some slop to the I/O and memory resources decoded by 1228 * this bus to give a guest some flexibility if it wants to 1229 * reprogram the BARs. 1230 */ 1231 pci_emul_iobase += BUSIO_ROUNDUP; 1232 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1233 bi->iolimit = pci_emul_iobase; 1234 1235 pci_emul_membase32 += BUSMEM_ROUNDUP; 1236 pci_emul_membase32 = roundup2(pci_emul_membase32, 1237 BUSMEM_ROUNDUP); 1238 bi->memlimit32 = pci_emul_membase32; 1239 1240 pci_emul_membase64 += BUSMEM_ROUNDUP; 1241 pci_emul_membase64 = roundup2(pci_emul_membase64, 1242 BUSMEM_ROUNDUP); 1243 bi->memlimit64 = pci_emul_membase64; 1244 } 1245 1246 /* 1247 * PCI backends are initialized before routing INTx interrupts 1248 * so that LPC devices are able to reserve ISA IRQs before 1249 * routing PIRQ pins. 1250 */ 1251 for (bus = 0; bus < MAXBUSES; bus++) { 1252 if ((bi = pci_businfo[bus]) == NULL) 1253 continue; 1254 1255 for (slot = 0; slot < MAXSLOTS; slot++) { 1256 si = &bi->slotinfo[slot]; 1257 for (func = 0; func < MAXFUNCS; func++) { 1258 fi = &si->si_funcs[func]; 1259 if (fi->fi_devi == NULL) 1260 continue; 1261 pci_lintr_route(fi->fi_devi); 1262 } 1263 } 1264 } 1265 lpc_pirq_routed(); 1266 1267 /* 1268 * The guest physical memory map looks like the following: 1269 * [0, lowmem) guest system memory 1270 * [lowmem, lowmem_limit) memory hole (may be absent) 1271 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation) 1272 * [0xE0000000, 0xF0000000) PCI extended config window 1273 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1274 * [4GB, 4GB + highmem) 1275 */ 1276 1277 /* 1278 * Accesses to memory addresses that are not allocated to system 1279 * memory or PCI devices return 0xff's. 1280 */ 1281 lowmem = vm_get_lowmem_size(ctx); 1282 bzero(&mr, sizeof(struct mem_range)); 1283 mr.name = "PCI hole"; 1284 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1285 mr.base = lowmem; 1286 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1287 mr.handler = pci_emul_fallback_handler; 1288 error = register_mem_fallback(&mr); 1289 assert(error == 0); 1290 1291 /* PCI extended config space */ 1292 bzero(&mr, sizeof(struct mem_range)); 1293 mr.name = "PCI ECFG"; 1294 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1295 mr.base = PCI_EMUL_ECFG_BASE; 1296 mr.size = PCI_EMUL_ECFG_SIZE; 1297 mr.handler = pci_emul_ecfg_handler; 1298 error = register_mem(&mr); 1299 assert(error == 0); 1300 1301 return (0); 1302 } 1303 1304 static void 1305 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1306 void *arg) 1307 { 1308 1309 dsdt_line(" Package ()"); 1310 dsdt_line(" {"); 1311 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1312 dsdt_line(" 0x%02X,", pin - 1); 1313 dsdt_line(" Zero,"); 1314 dsdt_line(" 0x%X", ioapic_irq); 1315 dsdt_line(" },"); 1316 } 1317 1318 static void 1319 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1320 void *arg) 1321 { 1322 char *name; 1323 1324 name = lpc_pirq_name(pirq_pin); 1325 if (name == NULL) 1326 return; 1327 dsdt_line(" Package ()"); 1328 dsdt_line(" {"); 1329 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1330 dsdt_line(" 0x%02X,", pin - 1); 1331 dsdt_line(" %s,", name); 1332 dsdt_line(" 0x00"); 1333 dsdt_line(" },"); 1334 free(name); 1335 } 1336 1337 /* 1338 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1339 * corresponding to each PCI bus. 1340 */ 1341 static void 1342 pci_bus_write_dsdt(int bus) 1343 { 1344 struct businfo *bi; 1345 struct slotinfo *si; 1346 struct pci_devinst *pi; 1347 int count, func, slot; 1348 1349 /* 1350 * If there are no devices on this 'bus' then just return. 1351 */ 1352 if ((bi = pci_businfo[bus]) == NULL) { 1353 /* 1354 * Bus 0 is special because it decodes the I/O ports used 1355 * for PCI config space access even if there are no devices 1356 * on it. 1357 */ 1358 if (bus != 0) 1359 return; 1360 } 1361 1362 dsdt_line(" Device (PC%02X)", bus); 1363 dsdt_line(" {"); 1364 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1365 1366 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1367 dsdt_line(" {"); 1368 dsdt_line(" Return (0x%08X)", bus); 1369 dsdt_line(" }"); 1370 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1371 dsdt_line(" {"); 1372 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1373 "MaxFixed, PosDecode,"); 1374 dsdt_line(" 0x0000, // Granularity"); 1375 dsdt_line(" 0x%04X, // Range Minimum", bus); 1376 dsdt_line(" 0x%04X, // Range Maximum", bus); 1377 dsdt_line(" 0x0000, // Translation Offset"); 1378 dsdt_line(" 0x0001, // Length"); 1379 dsdt_line(" ,, )"); 1380 1381 if (bus == 0) { 1382 dsdt_indent(3); 1383 dsdt_fixed_ioport(0xCF8, 8); 1384 dsdt_unindent(3); 1385 1386 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1387 "PosDecode, EntireRange,"); 1388 dsdt_line(" 0x0000, // Granularity"); 1389 dsdt_line(" 0x0000, // Range Minimum"); 1390 dsdt_line(" 0x0CF7, // Range Maximum"); 1391 dsdt_line(" 0x0000, // Translation Offset"); 1392 dsdt_line(" 0x0CF8, // Length"); 1393 dsdt_line(" ,, , TypeStatic)"); 1394 1395 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1396 "PosDecode, EntireRange,"); 1397 dsdt_line(" 0x0000, // Granularity"); 1398 dsdt_line(" 0x0D00, // Range Minimum"); 1399 dsdt_line(" 0x%04X, // Range Maximum", 1400 PCI_EMUL_IOBASE - 1); 1401 dsdt_line(" 0x0000, // Translation Offset"); 1402 dsdt_line(" 0x%04X, // Length", 1403 PCI_EMUL_IOBASE - 0x0D00); 1404 dsdt_line(" ,, , TypeStatic)"); 1405 1406 if (bi == NULL) { 1407 dsdt_line(" })"); 1408 goto done; 1409 } 1410 } 1411 assert(bi != NULL); 1412 1413 /* i/o window */ 1414 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1415 "PosDecode, EntireRange,"); 1416 dsdt_line(" 0x0000, // Granularity"); 1417 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1418 dsdt_line(" 0x%04X, // Range Maximum", 1419 bi->iolimit - 1); 1420 dsdt_line(" 0x0000, // Translation Offset"); 1421 dsdt_line(" 0x%04X, // Length", 1422 bi->iolimit - bi->iobase); 1423 dsdt_line(" ,, , TypeStatic)"); 1424 1425 /* mmio window (32-bit) */ 1426 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1427 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1428 dsdt_line(" 0x00000000, // Granularity"); 1429 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1430 dsdt_line(" 0x%08X, // Range Maximum\n", 1431 bi->memlimit32 - 1); 1432 dsdt_line(" 0x00000000, // Translation Offset"); 1433 dsdt_line(" 0x%08X, // Length\n", 1434 bi->memlimit32 - bi->membase32); 1435 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1436 1437 /* mmio window (64-bit) */ 1438 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1439 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1440 dsdt_line(" 0x0000000000000000, // Granularity"); 1441 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1442 dsdt_line(" 0x%016lX, // Range Maximum\n", 1443 bi->memlimit64 - 1); 1444 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1445 dsdt_line(" 0x%016lX, // Length\n", 1446 bi->memlimit64 - bi->membase64); 1447 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1448 dsdt_line(" })"); 1449 1450 count = pci_count_lintr(bus); 1451 if (count != 0) { 1452 dsdt_indent(2); 1453 dsdt_line("Name (PPRT, Package ()"); 1454 dsdt_line("{"); 1455 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1456 dsdt_line("})"); 1457 dsdt_line("Name (APRT, Package ()"); 1458 dsdt_line("{"); 1459 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1460 dsdt_line("})"); 1461 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1462 dsdt_line("{"); 1463 dsdt_line(" If (PICM)"); 1464 dsdt_line(" {"); 1465 dsdt_line(" Return (APRT)"); 1466 dsdt_line(" }"); 1467 dsdt_line(" Else"); 1468 dsdt_line(" {"); 1469 dsdt_line(" Return (PPRT)"); 1470 dsdt_line(" }"); 1471 dsdt_line("}"); 1472 dsdt_unindent(2); 1473 } 1474 1475 dsdt_indent(2); 1476 for (slot = 0; slot < MAXSLOTS; slot++) { 1477 si = &bi->slotinfo[slot]; 1478 for (func = 0; func < MAXFUNCS; func++) { 1479 pi = si->si_funcs[func].fi_devi; 1480 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1481 pi->pi_d->pe_write_dsdt(pi); 1482 } 1483 } 1484 dsdt_unindent(2); 1485 done: 1486 dsdt_line(" }"); 1487 } 1488 1489 void 1490 pci_write_dsdt(void) 1491 { 1492 int bus; 1493 1494 dsdt_indent(1); 1495 dsdt_line("Name (PICM, 0x00)"); 1496 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1497 dsdt_line("{"); 1498 dsdt_line(" Store (Arg0, PICM)"); 1499 dsdt_line("}"); 1500 dsdt_line(""); 1501 dsdt_line("Scope (_SB)"); 1502 dsdt_line("{"); 1503 for (bus = 0; bus < MAXBUSES; bus++) 1504 pci_bus_write_dsdt(bus); 1505 dsdt_line("}"); 1506 dsdt_unindent(1); 1507 } 1508 1509 int 1510 pci_bus_configured(int bus) 1511 { 1512 assert(bus >= 0 && bus < MAXBUSES); 1513 return (pci_businfo[bus] != NULL); 1514 } 1515 1516 int 1517 pci_msi_enabled(struct pci_devinst *pi) 1518 { 1519 return (pi->pi_msi.enabled); 1520 } 1521 1522 int 1523 pci_msi_maxmsgnum(struct pci_devinst *pi) 1524 { 1525 if (pi->pi_msi.enabled) 1526 return (pi->pi_msi.maxmsgnum); 1527 else 1528 return (0); 1529 } 1530 1531 int 1532 pci_msix_enabled(struct pci_devinst *pi) 1533 { 1534 1535 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1536 } 1537 1538 void 1539 pci_generate_msix(struct pci_devinst *pi, int index) 1540 { 1541 struct msix_table_entry *mte; 1542 1543 if (!pci_msix_enabled(pi)) 1544 return; 1545 1546 if (pi->pi_msix.function_mask) 1547 return; 1548 1549 if (index >= pi->pi_msix.table_count) 1550 return; 1551 1552 mte = &pi->pi_msix.table[index]; 1553 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1554 /* XXX Set PBA bit if interrupt is disabled */ 1555 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1556 } 1557 } 1558 1559 void 1560 pci_generate_msi(struct pci_devinst *pi, int index) 1561 { 1562 1563 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1564 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1565 pi->pi_msi.msg_data + index); 1566 } 1567 } 1568 1569 static bool 1570 pci_lintr_permitted(struct pci_devinst *pi) 1571 { 1572 uint16_t cmd; 1573 1574 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1575 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1576 (cmd & PCIM_CMD_INTxDIS))); 1577 } 1578 1579 void 1580 pci_lintr_request(struct pci_devinst *pi) 1581 { 1582 struct businfo *bi; 1583 struct slotinfo *si; 1584 int bestpin, bestcount, pin; 1585 1586 bi = pci_businfo[pi->pi_bus]; 1587 assert(bi != NULL); 1588 1589 /* 1590 * Just allocate a pin from our slot. The pin will be 1591 * assigned IRQs later when interrupts are routed. 1592 */ 1593 si = &bi->slotinfo[pi->pi_slot]; 1594 bestpin = 0; 1595 bestcount = si->si_intpins[0].ii_count; 1596 for (pin = 1; pin < 4; pin++) { 1597 if (si->si_intpins[pin].ii_count < bestcount) { 1598 bestpin = pin; 1599 bestcount = si->si_intpins[pin].ii_count; 1600 } 1601 } 1602 1603 si->si_intpins[bestpin].ii_count++; 1604 pi->pi_lintr.pin = bestpin + 1; 1605 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1606 } 1607 1608 static void 1609 pci_lintr_route(struct pci_devinst *pi) 1610 { 1611 struct businfo *bi; 1612 struct intxinfo *ii; 1613 1614 if (pi->pi_lintr.pin == 0) 1615 return; 1616 1617 bi = pci_businfo[pi->pi_bus]; 1618 assert(bi != NULL); 1619 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1620 1621 /* 1622 * Attempt to allocate an I/O APIC pin for this intpin if one 1623 * is not yet assigned. 1624 */ 1625 if (ii->ii_ioapic_irq == 0) 1626 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1627 assert(ii->ii_ioapic_irq > 0); 1628 1629 /* 1630 * Attempt to allocate a PIRQ pin for this intpin if one is 1631 * not yet assigned. 1632 */ 1633 if (ii->ii_pirq_pin == 0) 1634 ii->ii_pirq_pin = pirq_alloc_pin(pi); 1635 assert(ii->ii_pirq_pin > 0); 1636 1637 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1638 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1639 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1640 } 1641 1642 void 1643 pci_lintr_assert(struct pci_devinst *pi) 1644 { 1645 1646 assert(pi->pi_lintr.pin > 0); 1647 1648 pthread_mutex_lock(&pi->pi_lintr.lock); 1649 if (pi->pi_lintr.state == IDLE) { 1650 if (pci_lintr_permitted(pi)) { 1651 pi->pi_lintr.state = ASSERTED; 1652 pci_irq_assert(pi); 1653 } else 1654 pi->pi_lintr.state = PENDING; 1655 } 1656 pthread_mutex_unlock(&pi->pi_lintr.lock); 1657 } 1658 1659 void 1660 pci_lintr_deassert(struct pci_devinst *pi) 1661 { 1662 1663 assert(pi->pi_lintr.pin > 0); 1664 1665 pthread_mutex_lock(&pi->pi_lintr.lock); 1666 if (pi->pi_lintr.state == ASSERTED) { 1667 pi->pi_lintr.state = IDLE; 1668 pci_irq_deassert(pi); 1669 } else if (pi->pi_lintr.state == PENDING) 1670 pi->pi_lintr.state = IDLE; 1671 pthread_mutex_unlock(&pi->pi_lintr.lock); 1672 } 1673 1674 static void 1675 pci_lintr_update(struct pci_devinst *pi) 1676 { 1677 1678 pthread_mutex_lock(&pi->pi_lintr.lock); 1679 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1680 pci_irq_deassert(pi); 1681 pi->pi_lintr.state = PENDING; 1682 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1683 pi->pi_lintr.state = ASSERTED; 1684 pci_irq_assert(pi); 1685 } 1686 pthread_mutex_unlock(&pi->pi_lintr.lock); 1687 #ifndef __FreeBSD__ 1688 if (pi->pi_d->pe_lintrupdate != NULL) { 1689 pi->pi_d->pe_lintrupdate(pi); 1690 } 1691 #endif /* __FreeBSD__ */ 1692 } 1693 1694 int 1695 pci_count_lintr(int bus) 1696 { 1697 int count, slot, pin; 1698 struct slotinfo *slotinfo; 1699 1700 count = 0; 1701 if (pci_businfo[bus] != NULL) { 1702 for (slot = 0; slot < MAXSLOTS; slot++) { 1703 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 1704 for (pin = 0; pin < 4; pin++) { 1705 if (slotinfo->si_intpins[pin].ii_count != 0) 1706 count++; 1707 } 1708 } 1709 } 1710 return (count); 1711 } 1712 1713 void 1714 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 1715 { 1716 struct businfo *bi; 1717 struct slotinfo *si; 1718 struct intxinfo *ii; 1719 int slot, pin; 1720 1721 if ((bi = pci_businfo[bus]) == NULL) 1722 return; 1723 1724 for (slot = 0; slot < MAXSLOTS; slot++) { 1725 si = &bi->slotinfo[slot]; 1726 for (pin = 0; pin < 4; pin++) { 1727 ii = &si->si_intpins[pin]; 1728 if (ii->ii_count != 0) 1729 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 1730 ii->ii_ioapic_irq, arg); 1731 } 1732 } 1733 } 1734 1735 /* 1736 * Return 1 if the emulated device in 'slot' is a multi-function device. 1737 * Return 0 otherwise. 1738 */ 1739 static int 1740 pci_emul_is_mfdev(int bus, int slot) 1741 { 1742 struct businfo *bi; 1743 struct slotinfo *si; 1744 int f, numfuncs; 1745 1746 numfuncs = 0; 1747 if ((bi = pci_businfo[bus]) != NULL) { 1748 si = &bi->slotinfo[slot]; 1749 for (f = 0; f < MAXFUNCS; f++) { 1750 if (si->si_funcs[f].fi_devi != NULL) { 1751 numfuncs++; 1752 } 1753 } 1754 } 1755 return (numfuncs > 1); 1756 } 1757 1758 /* 1759 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1760 * whether or not is a multi-function being emulated in the pci 'slot'. 1761 */ 1762 static void 1763 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 1764 { 1765 int mfdev; 1766 1767 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1768 mfdev = pci_emul_is_mfdev(bus, slot); 1769 switch (bytes) { 1770 case 1: 1771 case 2: 1772 *rv &= ~PCIM_MFDEV; 1773 if (mfdev) { 1774 *rv |= PCIM_MFDEV; 1775 } 1776 break; 1777 case 4: 1778 *rv &= ~(PCIM_MFDEV << 16); 1779 if (mfdev) { 1780 *rv |= (PCIM_MFDEV << 16); 1781 } 1782 break; 1783 } 1784 } 1785 } 1786 1787 /* 1788 * Update device state in response to changes to the PCI command 1789 * register. 1790 */ 1791 void 1792 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 1793 { 1794 int i; 1795 uint16_t changed, new; 1796 1797 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 1798 changed = old ^ new; 1799 1800 /* 1801 * If the MMIO or I/O address space decoding has changed then 1802 * register/unregister all BARs that decode that address space. 1803 */ 1804 for (i = 0; i <= PCI_BARMAX; i++) { 1805 switch (pi->pi_bar[i].type) { 1806 case PCIBAR_NONE: 1807 case PCIBAR_MEMHI64: 1808 break; 1809 case PCIBAR_IO: 1810 /* I/O address space decoding changed? */ 1811 if (changed & PCIM_CMD_PORTEN) { 1812 if (new & PCIM_CMD_PORTEN) 1813 register_bar(pi, i); 1814 else 1815 unregister_bar(pi, i); 1816 } 1817 break; 1818 case PCIBAR_MEM32: 1819 case PCIBAR_MEM64: 1820 /* MMIO address space decoding changed? */ 1821 if (changed & PCIM_CMD_MEMEN) { 1822 if (new & PCIM_CMD_MEMEN) 1823 register_bar(pi, i); 1824 else 1825 unregister_bar(pi, i); 1826 } 1827 break; 1828 default: 1829 assert(0); 1830 } 1831 } 1832 1833 /* 1834 * If INTx has been unmasked and is pending, assert the 1835 * interrupt. 1836 */ 1837 pci_lintr_update(pi); 1838 } 1839 1840 static void 1841 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 1842 { 1843 int rshift; 1844 uint32_t cmd, old, readonly; 1845 1846 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1847 1848 /* 1849 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 1850 * 1851 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 1852 * 'write 1 to clear'. However these bits are not set to '1' by 1853 * any device emulation so it is simpler to treat them as readonly. 1854 */ 1855 rshift = (coff & 0x3) * 8; 1856 readonly = 0xFFFFF880 >> rshift; 1857 1858 old = CFGREAD(pi, coff, bytes); 1859 new &= ~readonly; 1860 new |= (old & readonly); 1861 CFGWRITE(pi, coff, new, bytes); /* update config */ 1862 1863 pci_emul_cmd_changed(pi, cmd); 1864 } 1865 1866 static void 1867 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func, 1868 int coff, int bytes, uint32_t *eax) 1869 { 1870 struct businfo *bi; 1871 struct slotinfo *si; 1872 struct pci_devinst *pi; 1873 struct pci_devemu *pe; 1874 int idx, needcfg; 1875 uint64_t addr, mask; 1876 uint64_t bar = 0; 1877 1878 if ((bi = pci_businfo[bus]) != NULL) { 1879 si = &bi->slotinfo[slot]; 1880 pi = si->si_funcs[func].fi_devi; 1881 } else 1882 pi = NULL; 1883 1884 /* 1885 * Just return if there is no device at this slot:func or if the 1886 * the guest is doing an un-aligned access. 1887 */ 1888 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 1889 (coff & (bytes - 1)) != 0) { 1890 if (in) 1891 *eax = 0xffffffff; 1892 return; 1893 } 1894 1895 /* 1896 * Ignore all writes beyond the standard config space and return all 1897 * ones on reads. 1898 */ 1899 if (coff >= PCI_REGMAX + 1) { 1900 if (in) { 1901 *eax = 0xffffffff; 1902 /* 1903 * Extended capabilities begin at offset 256 in config 1904 * space. Absence of extended capabilities is signaled 1905 * with all 0s in the extended capability header at 1906 * offset 256. 1907 */ 1908 if (coff <= PCI_REGMAX + 4) 1909 *eax = 0x00000000; 1910 } 1911 return; 1912 } 1913 1914 pe = pi->pi_d; 1915 1916 /* 1917 * Config read 1918 */ 1919 if (in) { 1920 /* Let the device emulation override the default handler */ 1921 if (pe->pe_cfgread != NULL) { 1922 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes, 1923 eax); 1924 } else { 1925 needcfg = 1; 1926 } 1927 1928 if (needcfg) 1929 *eax = CFGREAD(pi, coff, bytes); 1930 1931 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax); 1932 } else { 1933 /* Let the device emulation override the default handler */ 1934 if (pe->pe_cfgwrite != NULL && 1935 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1936 return; 1937 1938 /* 1939 * Special handling for write to BAR registers 1940 */ 1941 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1942 /* 1943 * Ignore writes to BAR registers that are not 1944 * 4-byte aligned. 1945 */ 1946 if (bytes != 4 || (coff & 0x3) != 0) 1947 return; 1948 idx = (coff - PCIR_BAR(0)) / 4; 1949 mask = ~(pi->pi_bar[idx].size - 1); 1950 switch (pi->pi_bar[idx].type) { 1951 case PCIBAR_NONE: 1952 pi->pi_bar[idx].addr = bar = 0; 1953 break; 1954 case PCIBAR_IO: 1955 addr = *eax & mask; 1956 addr &= 0xffff; 1957 bar = addr | PCIM_BAR_IO_SPACE; 1958 /* 1959 * Register the new BAR value for interception 1960 */ 1961 if (addr != pi->pi_bar[idx].addr) { 1962 update_bar_address(pi, addr, idx, 1963 PCIBAR_IO); 1964 } 1965 break; 1966 case PCIBAR_MEM32: 1967 addr = bar = *eax & mask; 1968 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1969 if (addr != pi->pi_bar[idx].addr) { 1970 update_bar_address(pi, addr, idx, 1971 PCIBAR_MEM32); 1972 } 1973 break; 1974 case PCIBAR_MEM64: 1975 addr = bar = *eax & mask; 1976 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1977 PCIM_BAR_MEM_PREFETCH; 1978 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1979 update_bar_address(pi, addr, idx, 1980 PCIBAR_MEM64); 1981 } 1982 break; 1983 case PCIBAR_MEMHI64: 1984 mask = ~(pi->pi_bar[idx - 1].size - 1); 1985 addr = ((uint64_t)*eax << 32) & mask; 1986 bar = addr >> 32; 1987 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1988 update_bar_address(pi, addr, idx - 1, 1989 PCIBAR_MEMHI64); 1990 } 1991 break; 1992 default: 1993 assert(0); 1994 } 1995 pci_set_cfgdata32(pi, coff, bar); 1996 1997 } else if (pci_emul_iscap(pi, coff)) { 1998 pci_emul_capwrite(pi, coff, bytes, *eax, 0, 0); 1999 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 2000 pci_emul_cmdsts_write(pi, coff, *eax, bytes); 2001 } else { 2002 CFGWRITE(pi, coff, *eax, bytes); 2003 } 2004 } 2005 } 2006 2007 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 2008 2009 static int 2010 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 2011 uint32_t *eax, void *arg) 2012 { 2013 uint32_t x; 2014 2015 if (bytes != 4) { 2016 if (in) 2017 *eax = (bytes == 2) ? 0xffff : 0xff; 2018 return (0); 2019 } 2020 2021 if (in) { 2022 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 2023 if (cfgenable) 2024 x |= CONF1_ENABLE; 2025 *eax = x; 2026 } else { 2027 x = *eax; 2028 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 2029 cfgoff = x & PCI_REGMAX; 2030 cfgfunc = (x >> 8) & PCI_FUNCMAX; 2031 cfgslot = (x >> 11) & PCI_SLOTMAX; 2032 cfgbus = (x >> 16) & PCI_BUSMAX; 2033 } 2034 2035 return (0); 2036 } 2037 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 2038 2039 static int 2040 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 2041 uint32_t *eax, void *arg) 2042 { 2043 int coff; 2044 2045 assert(bytes == 1 || bytes == 2 || bytes == 4); 2046 2047 coff = cfgoff + (port - CONF1_DATA_PORT); 2048 if (cfgenable) { 2049 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes, 2050 eax); 2051 } else { 2052 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 2053 if (in) 2054 *eax = 0xffffffff; 2055 } 2056 return (0); 2057 } 2058 2059 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 2060 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 2061 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 2062 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 2063 2064 #define PCI_EMUL_TEST 2065 #ifdef PCI_EMUL_TEST 2066 /* 2067 * Define a dummy test device 2068 */ 2069 #define DIOSZ 8 2070 #define DMEMSZ 4096 2071 struct pci_emul_dsoftc { 2072 uint8_t ioregs[DIOSZ]; 2073 uint8_t memregs[2][DMEMSZ]; 2074 }; 2075 2076 #define PCI_EMUL_MSI_MSGS 4 2077 #define PCI_EMUL_MSIX_MSGS 16 2078 2079 static int 2080 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl) 2081 { 2082 int error; 2083 struct pci_emul_dsoftc *sc; 2084 2085 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 2086 2087 pi->pi_arg = sc; 2088 2089 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 2090 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 2091 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 2092 2093 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 2094 assert(error == 0); 2095 2096 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 2097 assert(error == 0); 2098 2099 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2100 assert(error == 0); 2101 2102 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2103 assert(error == 0); 2104 2105 return (0); 2106 } 2107 2108 static void 2109 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2110 uint64_t offset, int size, uint64_t value) 2111 { 2112 int i; 2113 struct pci_emul_dsoftc *sc = pi->pi_arg; 2114 2115 if (baridx == 0) { 2116 if (offset + size > DIOSZ) { 2117 printf("diow: iow too large, offset %ld size %d\n", 2118 offset, size); 2119 return; 2120 } 2121 2122 if (size == 1) { 2123 sc->ioregs[offset] = value & 0xff; 2124 } else if (size == 2) { 2125 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2126 } else if (size == 4) { 2127 *(uint32_t *)&sc->ioregs[offset] = value; 2128 } else { 2129 printf("diow: iow unknown size %d\n", size); 2130 } 2131 2132 /* 2133 * Special magic value to generate an interrupt 2134 */ 2135 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2136 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2137 2138 if (value == 0xabcdef) { 2139 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2140 pci_generate_msi(pi, i); 2141 } 2142 } 2143 2144 if (baridx == 1 || baridx == 2) { 2145 if (offset + size > DMEMSZ) { 2146 printf("diow: memw too large, offset %ld size %d\n", 2147 offset, size); 2148 return; 2149 } 2150 2151 i = baridx - 1; /* 'memregs' index */ 2152 2153 if (size == 1) { 2154 sc->memregs[i][offset] = value; 2155 } else if (size == 2) { 2156 *(uint16_t *)&sc->memregs[i][offset] = value; 2157 } else if (size == 4) { 2158 *(uint32_t *)&sc->memregs[i][offset] = value; 2159 } else if (size == 8) { 2160 *(uint64_t *)&sc->memregs[i][offset] = value; 2161 } else { 2162 printf("diow: memw unknown size %d\n", size); 2163 } 2164 2165 /* 2166 * magic interrupt ?? 2167 */ 2168 } 2169 2170 if (baridx > 2 || baridx < 0) { 2171 printf("diow: unknown bar idx %d\n", baridx); 2172 } 2173 } 2174 2175 static uint64_t 2176 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2177 uint64_t offset, int size) 2178 { 2179 struct pci_emul_dsoftc *sc = pi->pi_arg; 2180 uint32_t value; 2181 int i; 2182 2183 value = 0; 2184 if (baridx == 0) { 2185 if (offset + size > DIOSZ) { 2186 printf("dior: ior too large, offset %ld size %d\n", 2187 offset, size); 2188 return (0); 2189 } 2190 2191 value = 0; 2192 if (size == 1) { 2193 value = sc->ioregs[offset]; 2194 } else if (size == 2) { 2195 value = *(uint16_t *) &sc->ioregs[offset]; 2196 } else if (size == 4) { 2197 value = *(uint32_t *) &sc->ioregs[offset]; 2198 } else { 2199 printf("dior: ior unknown size %d\n", size); 2200 } 2201 } 2202 2203 if (baridx == 1 || baridx == 2) { 2204 if (offset + size > DMEMSZ) { 2205 printf("dior: memr too large, offset %ld size %d\n", 2206 offset, size); 2207 return (0); 2208 } 2209 2210 i = baridx - 1; /* 'memregs' index */ 2211 2212 if (size == 1) { 2213 value = sc->memregs[i][offset]; 2214 } else if (size == 2) { 2215 value = *(uint16_t *) &sc->memregs[i][offset]; 2216 } else if (size == 4) { 2217 value = *(uint32_t *) &sc->memregs[i][offset]; 2218 } else if (size == 8) { 2219 value = *(uint64_t *) &sc->memregs[i][offset]; 2220 } else { 2221 printf("dior: ior unknown size %d\n", size); 2222 } 2223 } 2224 2225 2226 if (baridx > 2 || baridx < 0) { 2227 printf("dior: unknown bar idx %d\n", baridx); 2228 return (0); 2229 } 2230 2231 return (value); 2232 } 2233 2234 struct pci_devemu pci_dummy = { 2235 .pe_emu = "dummy", 2236 .pe_init = pci_emul_dinit, 2237 .pe_barwrite = pci_emul_diow, 2238 .pe_barread = pci_emul_dior, 2239 }; 2240 PCI_EMUL_SET(pci_dummy); 2241 2242 #endif /* PCI_EMUL_TEST */ 2243