1 /* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org> 6 * Copyright (c) 2013 Jeremiah Lott, Avere Systems 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer 14 * in this position and unchanged. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/types.h> 36 #ifndef WITHOUT_CAPSICUM 37 #include <sys/capsicum.h> 38 #endif 39 #include <sys/limits.h> 40 #include <sys/ioctl.h> 41 #include <sys/uio.h> 42 #include <net/ethernet.h> 43 #include <netinet/in.h> 44 #include <netinet/tcp.h> 45 #ifndef __FreeBSD__ 46 #include <sys/filio.h> 47 #endif 48 49 #ifndef WITHOUT_CAPSICUM 50 #include <capsicum_helpers.h> 51 #endif 52 #include <err.h> 53 #include <errno.h> 54 #include <fcntl.h> 55 #include <md5.h> 56 #include <stdio.h> 57 #include <stdlib.h> 58 #include <string.h> 59 #include <sysexits.h> 60 #include <unistd.h> 61 #include <pthread.h> 62 #include <pthread_np.h> 63 64 #include "e1000_regs.h" 65 #include "e1000_defines.h" 66 #include "mii.h" 67 68 #include "bhyverun.h" 69 #include "debug.h" 70 #include "pci_emul.h" 71 #include "mevent.h" 72 #include "net_utils.h" 73 74 /* Hardware/register definitions XXX: move some to common code. */ 75 #define E82545_VENDOR_ID_INTEL 0x8086 76 #define E82545_DEV_ID_82545EM_COPPER 0x100F 77 #define E82545_SUBDEV_ID 0x1008 78 79 #define E82545_REVISION_4 4 80 81 #define E82545_MDIC_DATA_MASK 0x0000FFFF 82 #define E82545_MDIC_OP_MASK 0x0c000000 83 #define E82545_MDIC_IE 0x20000000 84 85 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */ 86 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */ 87 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */ 88 89 #define E82545_BAR_REGISTER 0 90 #define E82545_BAR_REGISTER_LEN (128*1024) 91 #define E82545_BAR_FLASH 1 92 #define E82545_BAR_FLASH_LEN (64*1024) 93 #define E82545_BAR_IO 2 94 #define E82545_BAR_IO_LEN 8 95 96 #define E82545_IOADDR 0x00000000 97 #define E82545_IODATA 0x00000004 98 #define E82545_IO_REGISTER_MAX 0x0001FFFF 99 #define E82545_IO_FLASH_BASE 0x00080000 100 #define E82545_IO_FLASH_MAX 0x000FFFFF 101 102 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2)) 103 #define E82545_RAR_MAX 15 104 #define E82545_MTA_MAX 127 105 #define E82545_VFTA_MAX 127 106 107 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits, 108 * followed by 6 address bits. 109 * TODO: make opcode bits and addr bits configurable? 110 * NVM Commands - Microwire */ 111 #define E82545_NVM_OPCODE_BITS 3 112 #define E82545_NVM_ADDR_BITS 6 113 #define E82545_NVM_DATA_BITS 16 114 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS) 115 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1) 116 #define E82545_NVM_OPCODE_MASK \ 117 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS) 118 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */ 119 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */ 120 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */ 121 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */ 122 123 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */ 124 125 #define E1000_ICR_SRPD 0x00010000 126 127 /* This is an arbitrary number. There is no hard limit on the chip. */ 128 #define I82545_MAX_TXSEGS 64 129 130 /* Legacy receive descriptor */ 131 struct e1000_rx_desc { 132 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 133 uint16_t length; /* Length of data DMAed into data buffer */ 134 uint16_t csum; /* Packet checksum */ 135 uint8_t status; /* Descriptor status */ 136 uint8_t errors; /* Descriptor Errors */ 137 uint16_t special; 138 }; 139 140 /* Transmit descriptor types */ 141 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000) 142 #define E1000_TXD_TYP_L (0) 143 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C) 144 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D) 145 146 /* Legacy transmit descriptor */ 147 struct e1000_tx_desc { 148 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 149 union { 150 uint32_t data; 151 struct { 152 uint16_t length; /* Data buffer length */ 153 uint8_t cso; /* Checksum offset */ 154 uint8_t cmd; /* Descriptor control */ 155 } flags; 156 } lower; 157 union { 158 uint32_t data; 159 struct { 160 uint8_t status; /* Descriptor status */ 161 uint8_t css; /* Checksum start */ 162 uint16_t special; 163 } fields; 164 } upper; 165 }; 166 167 /* Context descriptor */ 168 struct e1000_context_desc { 169 union { 170 uint32_t ip_config; 171 struct { 172 uint8_t ipcss; /* IP checksum start */ 173 uint8_t ipcso; /* IP checksum offset */ 174 uint16_t ipcse; /* IP checksum end */ 175 } ip_fields; 176 } lower_setup; 177 union { 178 uint32_t tcp_config; 179 struct { 180 uint8_t tucss; /* TCP checksum start */ 181 uint8_t tucso; /* TCP checksum offset */ 182 uint16_t tucse; /* TCP checksum end */ 183 } tcp_fields; 184 } upper_setup; 185 uint32_t cmd_and_length; 186 union { 187 uint32_t data; 188 struct { 189 uint8_t status; /* Descriptor status */ 190 uint8_t hdr_len; /* Header length */ 191 uint16_t mss; /* Maximum segment size */ 192 } fields; 193 } tcp_seg_setup; 194 }; 195 196 /* Data descriptor */ 197 struct e1000_data_desc { 198 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 199 union { 200 uint32_t data; 201 struct { 202 uint16_t length; /* Data buffer length */ 203 uint8_t typ_len_ext; 204 uint8_t cmd; 205 } flags; 206 } lower; 207 union { 208 uint32_t data; 209 struct { 210 uint8_t status; /* Descriptor status */ 211 uint8_t popts; /* Packet Options */ 212 uint16_t special; 213 } fields; 214 } upper; 215 }; 216 217 union e1000_tx_udesc { 218 struct e1000_tx_desc td; 219 struct e1000_context_desc cd; 220 struct e1000_data_desc dd; 221 }; 222 223 /* Tx checksum info for a packet. */ 224 struct ck_info { 225 int ck_valid; /* ck_info is valid */ 226 uint8_t ck_start; /* start byte of cksum calcuation */ 227 uint8_t ck_off; /* offset of cksum insertion */ 228 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */ 229 }; 230 231 /* 232 * Debug printf 233 */ 234 static int e82545_debug = 0; 235 #define WPRINTF(msg,params...) PRINTLN("e82545: " msg, params) 236 #define DPRINTF(msg,params...) if (e82545_debug) WPRINTF(msg, params) 237 238 #define MIN(a,b) (((a)<(b))?(a):(b)) 239 #define MAX(a,b) (((a)>(b))?(a):(b)) 240 241 /* s/w representation of the RAL/RAH regs */ 242 struct eth_uni { 243 int eu_valid; 244 int eu_addrsel; 245 struct ether_addr eu_eth; 246 }; 247 248 249 struct e82545_softc { 250 struct pci_devinst *esc_pi; 251 struct vmctx *esc_ctx; 252 struct mevent *esc_mevp; 253 struct mevent *esc_mevpitr; 254 pthread_mutex_t esc_mtx; 255 struct ether_addr esc_mac; 256 int esc_tapfd; 257 258 /* General */ 259 uint32_t esc_CTRL; /* x0000 device ctl */ 260 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */ 261 uint32_t esc_FCAH; /* x002C flow ctl addr hi */ 262 uint32_t esc_FCT; /* x0030 flow ctl type */ 263 uint32_t esc_VET; /* x0038 VLAN eth type */ 264 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */ 265 uint32_t esc_LEDCTL; /* x0E00 LED control */ 266 uint32_t esc_PBA; /* x1000 pkt buffer allocation */ 267 268 /* Interrupt control */ 269 int esc_irq_asserted; 270 uint32_t esc_ICR; /* x00C0 cause read/clear */ 271 uint32_t esc_ITR; /* x00C4 intr throttling */ 272 uint32_t esc_ICS; /* x00C8 cause set */ 273 uint32_t esc_IMS; /* x00D0 mask set/read */ 274 uint32_t esc_IMC; /* x00D8 mask clear */ 275 276 /* Transmit */ 277 union e1000_tx_udesc *esc_txdesc; 278 struct e1000_context_desc esc_txctx; 279 pthread_t esc_tx_tid; 280 pthread_cond_t esc_tx_cond; 281 int esc_tx_enabled; 282 int esc_tx_active; 283 uint32_t esc_TXCW; /* x0178 transmit config */ 284 uint32_t esc_TCTL; /* x0400 transmit ctl */ 285 uint32_t esc_TIPG; /* x0410 inter-packet gap */ 286 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */ 287 uint64_t esc_tdba; /* verified 64-bit desc table addr */ 288 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */ 289 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */ 290 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */ 291 uint16_t esc_TDH; /* x3810 desc table head idx */ 292 uint16_t esc_TDHr; /* internal read version of TDH */ 293 uint16_t esc_TDT; /* x3818 desc table tail idx */ 294 uint32_t esc_TIDV; /* x3820 intr delay */ 295 uint32_t esc_TXDCTL; /* x3828 desc control */ 296 uint32_t esc_TADV; /* x382C intr absolute delay */ 297 298 /* L2 frame acceptance */ 299 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */ 300 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */ 301 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */ 302 303 /* Receive */ 304 struct e1000_rx_desc *esc_rxdesc; 305 pthread_cond_t esc_rx_cond; 306 int esc_rx_enabled; 307 int esc_rx_active; 308 int esc_rx_loopback; 309 uint32_t esc_RCTL; /* x0100 receive ctl */ 310 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */ 311 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */ 312 uint64_t esc_rdba; /* verified 64-bit desc table addr */ 313 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */ 314 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/ 315 uint32_t esc_RDLEN; /* x2808 #descriptors */ 316 uint16_t esc_RDH; /* x2810 desc table head idx */ 317 uint16_t esc_RDT; /* x2818 desc table tail idx */ 318 uint32_t esc_RDTR; /* x2820 intr delay */ 319 uint32_t esc_RXDCTL; /* x2828 desc control */ 320 uint32_t esc_RADV; /* x282C intr absolute delay */ 321 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */ 322 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */ 323 324 /* IO Port register access */ 325 uint32_t io_addr; 326 327 /* Shadow copy of MDIC */ 328 uint32_t mdi_control; 329 /* Shadow copy of EECD */ 330 uint32_t eeprom_control; 331 /* Latest NVM in/out */ 332 uint16_t nvm_data; 333 uint16_t nvm_opaddr; 334 /* stats */ 335 uint32_t missed_pkt_count; /* dropped for no room in rx queue */ 336 uint32_t pkt_rx_by_size[6]; 337 uint32_t pkt_tx_by_size[6]; 338 uint32_t good_pkt_rx_count; 339 uint32_t bcast_pkt_rx_count; 340 uint32_t mcast_pkt_rx_count; 341 uint32_t good_pkt_tx_count; 342 uint32_t bcast_pkt_tx_count; 343 uint32_t mcast_pkt_tx_count; 344 uint32_t oversize_rx_count; 345 uint32_t tso_tx_count; 346 uint64_t good_octets_rx; 347 uint64_t good_octets_tx; 348 uint64_t missed_octets; /* counts missed and oversized */ 349 350 uint8_t nvm_bits:6; /* number of bits remaining in/out */ 351 uint8_t nvm_mode:2; 352 #define E82545_NVM_MODE_OPADDR 0x0 353 #define E82545_NVM_MODE_DATAIN 0x1 354 #define E82545_NVM_MODE_DATAOUT 0x2 355 /* EEPROM data */ 356 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE]; 357 }; 358 359 static void e82545_reset(struct e82545_softc *sc, int dev); 360 static void e82545_rx_enable(struct e82545_softc *sc); 361 static void e82545_rx_disable(struct e82545_softc *sc); 362 #ifdef __FreeBSD__ 363 static void e82545_tap_callback(int fd, enum ev_type type, void *param); 364 #endif 365 static void e82545_tx_start(struct e82545_softc *sc); 366 static void e82545_tx_enable(struct e82545_softc *sc); 367 static void e82545_tx_disable(struct e82545_softc *sc); 368 369 static inline int 370 e82545_size_stat_index(uint32_t size) 371 { 372 if (size <= 64) { 373 return 0; 374 } else if (size >= 1024) { 375 return 5; 376 } else { 377 /* should be 1-4 */ 378 return (ffs(size) - 6); 379 } 380 } 381 382 static void 383 e82545_init_eeprom(struct e82545_softc *sc) 384 { 385 uint16_t checksum, i; 386 387 /* mac addr */ 388 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) | 389 (((uint16_t)sc->esc_mac.octet[1]) << 8); 390 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) | 391 (((uint16_t)sc->esc_mac.octet[3]) << 8); 392 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) | 393 (((uint16_t)sc->esc_mac.octet[5]) << 8); 394 395 /* pci ids */ 396 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID; 397 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL; 398 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER; 399 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL; 400 401 /* fill in the checksum */ 402 checksum = 0; 403 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 404 checksum += sc->eeprom_data[i]; 405 } 406 checksum = NVM_SUM - checksum; 407 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum; 408 DPRINTF("eeprom checksum: 0x%x", checksum); 409 } 410 411 static void 412 e82545_write_mdi(struct e82545_softc *sc, uint8_t reg_addr, 413 uint8_t phy_addr, uint32_t data) 414 { 415 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x", reg_addr, phy_addr, data); 416 } 417 418 static uint32_t 419 e82545_read_mdi(struct e82545_softc *sc, uint8_t reg_addr, 420 uint8_t phy_addr) 421 { 422 //DPRINTF("Read mdi reg:0x%x phy:0x%x", reg_addr, phy_addr); 423 switch (reg_addr) { 424 case PHY_STATUS: 425 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS | 426 MII_SR_AUTONEG_COMPLETE); 427 case PHY_AUTONEG_ADV: 428 return NWAY_AR_SELECTOR_FIELD; 429 case PHY_LP_ABILITY: 430 return 0; 431 case PHY_1000T_STATUS: 432 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS | 433 SR_1000T_LOCAL_RX_STATUS); 434 case PHY_ID1: 435 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF; 436 case PHY_ID2: 437 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF; 438 default: 439 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x", reg_addr, phy_addr); 440 return 0; 441 } 442 /* not reached */ 443 } 444 445 static void 446 e82545_eecd_strobe(struct e82545_softc *sc) 447 { 448 /* Microwire state machine */ 449 /* 450 DPRINTF("eeprom state machine srtobe " 451 "0x%x 0x%x 0x%x 0x%x", 452 sc->nvm_mode, sc->nvm_bits, 453 sc->nvm_opaddr, sc->nvm_data);*/ 454 455 if (sc->nvm_bits == 0) { 456 DPRINTF("eeprom state machine not expecting data! " 457 "0x%x 0x%x 0x%x 0x%x", 458 sc->nvm_mode, sc->nvm_bits, 459 sc->nvm_opaddr, sc->nvm_data); 460 return; 461 } 462 sc->nvm_bits--; 463 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) { 464 /* shifting out */ 465 if (sc->nvm_data & 0x8000) { 466 sc->eeprom_control |= E1000_EECD_DO; 467 } else { 468 sc->eeprom_control &= ~E1000_EECD_DO; 469 } 470 sc->nvm_data <<= 1; 471 if (sc->nvm_bits == 0) { 472 /* read done, back to opcode mode. */ 473 sc->nvm_opaddr = 0; 474 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 475 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 476 } 477 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) { 478 /* shifting in */ 479 sc->nvm_data <<= 1; 480 if (sc->eeprom_control & E1000_EECD_DI) { 481 sc->nvm_data |= 1; 482 } 483 if (sc->nvm_bits == 0) { 484 /* eeprom write */ 485 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 486 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK; 487 if (op != E82545_NVM_OPCODE_WRITE) { 488 DPRINTF("Illegal eeprom write op 0x%x", 489 sc->nvm_opaddr); 490 } else if (addr >= E82545_NVM_EEPROM_SIZE) { 491 DPRINTF("Illegal eeprom write addr 0x%x", 492 sc->nvm_opaddr); 493 } else { 494 DPRINTF("eeprom write eeprom[0x%x] = 0x%x", 495 addr, sc->nvm_data); 496 sc->eeprom_data[addr] = sc->nvm_data; 497 } 498 /* back to opcode mode */ 499 sc->nvm_opaddr = 0; 500 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 501 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 502 } 503 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) { 504 sc->nvm_opaddr <<= 1; 505 if (sc->eeprom_control & E1000_EECD_DI) { 506 sc->nvm_opaddr |= 1; 507 } 508 if (sc->nvm_bits == 0) { 509 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 510 switch (op) { 511 case E82545_NVM_OPCODE_EWEN: 512 DPRINTF("eeprom write enable: 0x%x", 513 sc->nvm_opaddr); 514 /* back to opcode mode */ 515 sc->nvm_opaddr = 0; 516 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 517 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 518 break; 519 case E82545_NVM_OPCODE_READ: 520 { 521 uint16_t addr = sc->nvm_opaddr & 522 E82545_NVM_ADDR_MASK; 523 sc->nvm_mode = E82545_NVM_MODE_DATAOUT; 524 sc->nvm_bits = E82545_NVM_DATA_BITS; 525 if (addr < E82545_NVM_EEPROM_SIZE) { 526 sc->nvm_data = sc->eeprom_data[addr]; 527 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x", 528 addr, sc->nvm_data); 529 } else { 530 DPRINTF("eeprom illegal read: 0x%x", 531 sc->nvm_opaddr); 532 sc->nvm_data = 0; 533 } 534 break; 535 } 536 case E82545_NVM_OPCODE_WRITE: 537 sc->nvm_mode = E82545_NVM_MODE_DATAIN; 538 sc->nvm_bits = E82545_NVM_DATA_BITS; 539 sc->nvm_data = 0; 540 break; 541 default: 542 DPRINTF("eeprom unknown op: 0x%x", 543 sc->nvm_opaddr); 544 /* back to opcode mode */ 545 sc->nvm_opaddr = 0; 546 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 547 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 548 } 549 } 550 } else { 551 DPRINTF("eeprom state machine wrong state! " 552 "0x%x 0x%x 0x%x 0x%x", 553 sc->nvm_mode, sc->nvm_bits, 554 sc->nvm_opaddr, sc->nvm_data); 555 } 556 } 557 558 #ifdef __FreeBSD__ 559 static void 560 e82545_itr_callback(int fd, enum ev_type type, void *param) 561 { 562 uint32_t new; 563 struct e82545_softc *sc = param; 564 565 pthread_mutex_lock(&sc->esc_mtx); 566 new = sc->esc_ICR & sc->esc_IMS; 567 if (new && !sc->esc_irq_asserted) { 568 DPRINTF("itr callback: lintr assert %x", new); 569 sc->esc_irq_asserted = 1; 570 pci_lintr_assert(sc->esc_pi); 571 } else { 572 mevent_delete(sc->esc_mevpitr); 573 sc->esc_mevpitr = NULL; 574 } 575 pthread_mutex_unlock(&sc->esc_mtx); 576 } 577 #endif 578 579 static void 580 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits) 581 { 582 uint32_t new; 583 584 DPRINTF("icr assert: 0x%x", bits); 585 586 /* 587 * An interrupt is only generated if bits are set that 588 * aren't already in the ICR, these bits are unmasked, 589 * and there isn't an interrupt already pending. 590 */ 591 new = bits & ~sc->esc_ICR & sc->esc_IMS; 592 sc->esc_ICR |= bits; 593 594 if (new == 0) { 595 DPRINTF("icr assert: masked %x, ims %x", new, sc->esc_IMS); 596 } else if (sc->esc_mevpitr != NULL) { 597 DPRINTF("icr assert: throttled %x, ims %x", new, sc->esc_IMS); 598 } else if (!sc->esc_irq_asserted) { 599 DPRINTF("icr assert: lintr assert %x", new); 600 sc->esc_irq_asserted = 1; 601 pci_lintr_assert(sc->esc_pi); 602 if (sc->esc_ITR != 0) { 603 #ifdef __FreeBSD__ 604 sc->esc_mevpitr = mevent_add( 605 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 606 EVF_TIMER, e82545_itr_callback, sc); 607 #endif 608 } 609 } 610 } 611 612 static void 613 e82545_ims_change(struct e82545_softc *sc, uint32_t bits) 614 { 615 uint32_t new; 616 617 /* 618 * Changing the mask may allow previously asserted 619 * but masked interrupt requests to generate an interrupt. 620 */ 621 new = bits & sc->esc_ICR & ~sc->esc_IMS; 622 sc->esc_IMS |= bits; 623 624 if (new == 0) { 625 DPRINTF("ims change: masked %x, ims %x", new, sc->esc_IMS); 626 } else if (sc->esc_mevpitr != NULL) { 627 DPRINTF("ims change: throttled %x, ims %x", new, sc->esc_IMS); 628 } else if (!sc->esc_irq_asserted) { 629 DPRINTF("ims change: lintr assert %x", new); 630 sc->esc_irq_asserted = 1; 631 pci_lintr_assert(sc->esc_pi); 632 if (sc->esc_ITR != 0) { 633 #ifdef __FreeBSD__ 634 sc->esc_mevpitr = mevent_add( 635 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 636 EVF_TIMER, e82545_itr_callback, sc); 637 #endif 638 } 639 } 640 } 641 642 static void 643 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits) 644 { 645 646 DPRINTF("icr deassert: 0x%x", bits); 647 sc->esc_ICR &= ~bits; 648 649 /* 650 * If there are no longer any interrupt sources and there 651 * was an asserted interrupt, clear it 652 */ 653 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) { 654 DPRINTF("icr deassert: lintr deassert %x", bits); 655 pci_lintr_deassert(sc->esc_pi); 656 sc->esc_irq_asserted = 0; 657 } 658 } 659 660 static void 661 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value) 662 { 663 664 DPRINTF("intr_write: off %x, val %x", offset, value); 665 666 switch (offset) { 667 case E1000_ICR: 668 e82545_icr_deassert(sc, value); 669 break; 670 case E1000_ITR: 671 sc->esc_ITR = value; 672 break; 673 case E1000_ICS: 674 sc->esc_ICS = value; /* not used: store for debug */ 675 e82545_icr_assert(sc, value); 676 break; 677 case E1000_IMS: 678 e82545_ims_change(sc, value); 679 break; 680 case E1000_IMC: 681 sc->esc_IMC = value; /* for debug */ 682 sc->esc_IMS &= ~value; 683 // XXX clear interrupts if all ICR bits now masked 684 // and interrupt was pending ? 685 break; 686 default: 687 break; 688 } 689 } 690 691 static uint32_t 692 e82545_intr_read(struct e82545_softc *sc, uint32_t offset) 693 { 694 uint32_t retval; 695 696 retval = 0; 697 698 DPRINTF("intr_read: off %x", offset); 699 700 switch (offset) { 701 case E1000_ICR: 702 retval = sc->esc_ICR; 703 sc->esc_ICR = 0; 704 e82545_icr_deassert(sc, ~0); 705 break; 706 case E1000_ITR: 707 retval = sc->esc_ITR; 708 break; 709 case E1000_ICS: 710 /* write-only register */ 711 break; 712 case E1000_IMS: 713 retval = sc->esc_IMS; 714 break; 715 case E1000_IMC: 716 /* write-only register */ 717 break; 718 default: 719 break; 720 } 721 722 return (retval); 723 } 724 725 static void 726 e82545_devctl(struct e82545_softc *sc, uint32_t val) 727 { 728 729 sc->esc_CTRL = val & ~E1000_CTRL_RST; 730 731 if (val & E1000_CTRL_RST) { 732 DPRINTF("e1k: s/w reset, ctl %x", val); 733 e82545_reset(sc, 1); 734 } 735 /* XXX check for phy reset ? */ 736 } 737 738 static void 739 e82545_rx_update_rdba(struct e82545_softc *sc) 740 { 741 742 /* XXX verify desc base/len within phys mem range */ 743 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 | 744 sc->esc_RDBAL; 745 746 /* Cache host mapping of guest descriptor array */ 747 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx, 748 sc->esc_rdba, sc->esc_RDLEN); 749 } 750 751 static void 752 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val) 753 { 754 int on; 755 756 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN); 757 758 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */ 759 sc->esc_RCTL = val & ~0xF9204c01; 760 761 DPRINTF("rx_ctl - %s RCTL %x, val %x", 762 on ? "on" : "off", sc->esc_RCTL, val); 763 764 /* state change requested */ 765 if (on != sc->esc_rx_enabled) { 766 if (on) { 767 /* Catch disallowed/unimplemented settings */ 768 //assert(!(val & E1000_RCTL_LBM_TCVR)); 769 770 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) { 771 sc->esc_rx_loopback = 1; 772 } else { 773 sc->esc_rx_loopback = 0; 774 } 775 776 e82545_rx_update_rdba(sc); 777 e82545_rx_enable(sc); 778 } else { 779 e82545_rx_disable(sc); 780 sc->esc_rx_loopback = 0; 781 sc->esc_rdba = 0; 782 sc->esc_rxdesc = NULL; 783 } 784 } 785 } 786 787 static void 788 e82545_tx_update_tdba(struct e82545_softc *sc) 789 { 790 791 /* XXX verify desc base/len within phys mem range */ 792 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL; 793 794 /* Cache host mapping of guest descriptor array */ 795 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba, 796 sc->esc_TDLEN); 797 } 798 799 static void 800 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val) 801 { 802 int on; 803 804 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN); 805 806 /* ignore TCTL_EN settings that don't change state */ 807 if (on == sc->esc_tx_enabled) 808 return; 809 810 if (on) { 811 e82545_tx_update_tdba(sc); 812 e82545_tx_enable(sc); 813 } else { 814 e82545_tx_disable(sc); 815 sc->esc_tdba = 0; 816 sc->esc_txdesc = NULL; 817 } 818 819 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */ 820 sc->esc_TCTL = val & ~0xFE800005; 821 } 822 823 int 824 e82545_bufsz(uint32_t rctl) 825 { 826 827 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) { 828 case (E1000_RCTL_SZ_2048): return (2048); 829 case (E1000_RCTL_SZ_1024): return (1024); 830 case (E1000_RCTL_SZ_512): return (512); 831 case (E1000_RCTL_SZ_256): return (256); 832 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384); 833 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192); 834 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096); 835 } 836 return (256); /* Forbidden value. */ 837 } 838 839 #ifdef __FreeBSD__ 840 static uint8_t dummybuf[2048]; 841 842 /* XXX one packet at a time until this is debugged */ 843 static void 844 e82545_tap_callback(int fd, enum ev_type type, void *param) 845 { 846 struct e82545_softc *sc = param; 847 struct e1000_rx_desc *rxd; 848 struct iovec vec[64]; 849 int left, len, lim, maxpktsz, maxpktdesc, bufsz, i, n, size; 850 uint32_t cause = 0; 851 uint16_t *tp, tag, head; 852 853 pthread_mutex_lock(&sc->esc_mtx); 854 DPRINTF("rx_run: head %x, tail %x", sc->esc_RDH, sc->esc_RDT); 855 856 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) { 857 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped", 858 sc->esc_rx_enabled, sc->esc_rx_loopback); 859 while (read(sc->esc_tapfd, dummybuf, sizeof(dummybuf)) > 0) { 860 } 861 goto done1; 862 } 863 bufsz = e82545_bufsz(sc->esc_RCTL); 864 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522; 865 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz; 866 size = sc->esc_RDLEN / 16; 867 head = sc->esc_RDH; 868 left = (size + sc->esc_RDT - head) % size; 869 if (left < maxpktdesc) { 870 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped", 871 left, maxpktdesc); 872 while (read(sc->esc_tapfd, dummybuf, sizeof(dummybuf)) > 0) { 873 } 874 goto done1; 875 } 876 877 sc->esc_rx_active = 1; 878 pthread_mutex_unlock(&sc->esc_mtx); 879 880 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) { 881 882 /* Grab rx descriptor pointed to by the head pointer */ 883 for (i = 0; i < maxpktdesc; i++) { 884 rxd = &sc->esc_rxdesc[(head + i) % size]; 885 vec[i].iov_base = paddr_guest2host(sc->esc_ctx, 886 rxd->buffer_addr, bufsz); 887 vec[i].iov_len = bufsz; 888 } 889 len = readv(sc->esc_tapfd, vec, maxpktdesc); 890 if (len <= 0) { 891 DPRINTF("tap: readv() returned %d\n", len); 892 goto done; 893 } 894 895 /* 896 * Adjust the packet length based on whether the CRC needs 897 * to be stripped or if the packet is less than the minimum 898 * eth packet size. 899 */ 900 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 901 len = ETHER_MIN_LEN - ETHER_CRC_LEN; 902 if (!(sc->esc_RCTL & E1000_RCTL_SECRC)) 903 len += ETHER_CRC_LEN; 904 n = (len + bufsz - 1) / bufsz; 905 906 DPRINTF("packet read %d bytes, %d segs, head %d", 907 len, n, head); 908 909 /* Apply VLAN filter. */ 910 tp = (uint16_t *)vec[0].iov_base + 6; 911 if ((sc->esc_RCTL & E1000_RCTL_VFE) && 912 (ntohs(tp[0]) == sc->esc_VET)) { 913 tag = ntohs(tp[1]) & 0x0fff; 914 if ((sc->esc_fvlan[tag >> 5] & 915 (1 << (tag & 0x1f))) != 0) { 916 DPRINTF("known VLAN %d", tag); 917 } else { 918 DPRINTF("unknown VLAN %d", tag); 919 n = 0; 920 continue; 921 } 922 } 923 924 /* Update all consumed descriptors. */ 925 for (i = 0; i < n - 1; i++) { 926 rxd = &sc->esc_rxdesc[(head + i) % size]; 927 rxd->length = bufsz; 928 rxd->csum = 0; 929 rxd->errors = 0; 930 rxd->special = 0; 931 rxd->status = E1000_RXD_STAT_DD; 932 } 933 rxd = &sc->esc_rxdesc[(head + i) % size]; 934 rxd->length = len % bufsz; 935 rxd->csum = 0; 936 rxd->errors = 0; 937 rxd->special = 0; 938 /* XXX signal no checksum for now */ 939 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM | 940 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD; 941 942 /* Schedule receive interrupts. */ 943 if (len <= sc->esc_RSRPD) { 944 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0; 945 } else { 946 /* XXX: RDRT and RADV timers should be here. */ 947 cause |= E1000_ICR_RXT0; 948 } 949 950 head = (head + n) % size; 951 left -= n; 952 } 953 954 done: 955 pthread_mutex_lock(&sc->esc_mtx); 956 sc->esc_rx_active = 0; 957 if (sc->esc_rx_enabled == 0) 958 pthread_cond_signal(&sc->esc_rx_cond); 959 960 sc->esc_RDH = head; 961 /* Respect E1000_RCTL_RDMTS */ 962 left = (size + sc->esc_RDT - head) % size; 963 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1))) 964 cause |= E1000_ICR_RXDMT0; 965 /* Assert all accumulated interrupts. */ 966 if (cause != 0) 967 e82545_icr_assert(sc, cause); 968 done1: 969 DPRINTF("rx_run done: head %x, tail %x", sc->esc_RDH, sc->esc_RDT); 970 pthread_mutex_unlock(&sc->esc_mtx); 971 } 972 #endif 973 974 static uint16_t 975 e82545_carry(uint32_t sum) 976 { 977 978 sum = (sum & 0xFFFF) + (sum >> 16); 979 if (sum > 0xFFFF) 980 sum -= 0xFFFF; 981 return (sum); 982 } 983 984 static uint16_t 985 #ifdef __FreeBSD__ 986 e82545_buf_checksum(uint8_t *buf, int len) 987 #else 988 e82545_buf_checksum(caddr_t buf, int len) 989 #endif 990 { 991 int i; 992 uint32_t sum = 0; 993 994 /* Checksum all the pairs of bytes first... */ 995 for (i = 0; i < (len & ~1U); i += 2) 996 sum += *((u_int16_t *)(buf + i)); 997 998 /* 999 * If there's a single byte left over, checksum it, too. 1000 * Network byte order is big-endian, so the remaining byte is 1001 * the high byte. 1002 */ 1003 if (i < len) 1004 sum += htons(buf[i] << 8); 1005 1006 return (e82545_carry(sum)); 1007 } 1008 1009 static uint16_t 1010 e82545_iov_checksum(struct iovec *iov, int iovcnt, int off, int len) 1011 { 1012 int now, odd; 1013 uint32_t sum = 0, s; 1014 1015 /* Skip completely unneeded vectors. */ 1016 while (iovcnt > 0 && iov->iov_len <= off && off > 0) { 1017 off -= iov->iov_len; 1018 iov++; 1019 iovcnt--; 1020 } 1021 1022 /* Calculate checksum of requested range. */ 1023 odd = 0; 1024 while (len > 0 && iovcnt > 0) { 1025 now = MIN(len, iov->iov_len - off); 1026 s = e82545_buf_checksum(iov->iov_base + off, now); 1027 sum += odd ? (s << 8) : s; 1028 odd ^= (now & 1); 1029 len -= now; 1030 off = 0; 1031 iov++; 1032 iovcnt--; 1033 } 1034 1035 return (e82545_carry(sum)); 1036 } 1037 1038 /* 1039 * Return the transmit descriptor type. 1040 */ 1041 int 1042 e82545_txdesc_type(uint32_t lower) 1043 { 1044 int type; 1045 1046 type = 0; 1047 1048 if (lower & E1000_TXD_CMD_DEXT) 1049 type = lower & E1000_TXD_MASK; 1050 1051 return (type); 1052 } 1053 1054 static void 1055 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck) 1056 { 1057 uint16_t cksum; 1058 int cklen; 1059 1060 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d", 1061 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len); 1062 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1 : INT_MAX; 1063 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen); 1064 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum; 1065 } 1066 1067 static void 1068 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt) 1069 { 1070 1071 if (sc->esc_tapfd == -1) 1072 return; 1073 1074 (void) writev(sc->esc_tapfd, iov, iovcnt); 1075 } 1076 1077 static void 1078 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1079 uint16_t dsize, int *tdwb) 1080 { 1081 union e1000_tx_udesc *dsc; 1082 1083 for ( ; head != tail; head = (head + 1) % dsize) { 1084 dsc = &sc->esc_txdesc[head]; 1085 if (dsc->td.lower.data & E1000_TXD_CMD_RS) { 1086 dsc->td.upper.data |= E1000_TXD_STAT_DD; 1087 *tdwb = 1; 1088 } 1089 } 1090 } 1091 1092 static int 1093 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1094 uint16_t dsize, uint16_t *rhead, int *tdwb) 1095 { 1096 #ifdef __FreeBSD__ 1097 uint8_t *hdr, *hdrp; 1098 #else 1099 caddr_t hdr, hdrp; 1100 #endif 1101 struct iovec iovb[I82545_MAX_TXSEGS + 2]; 1102 struct iovec tiov[I82545_MAX_TXSEGS + 2]; 1103 struct e1000_context_desc *cd; 1104 struct ck_info ckinfo[2]; 1105 struct iovec *iov; 1106 union e1000_tx_udesc *dsc; 1107 int desc, dtype, len, ntype, iovcnt, tlen, hdrlen, vlen, tcp, tso; 1108 int mss, paylen, seg, tiovcnt, left, now, nleft, nnow, pv, pvoff; 1109 uint32_t tcpsum, tcpseq; 1110 uint16_t ipcs, tcpcs, ipid, ohead; 1111 1112 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0; 1113 iovcnt = 0; 1114 tlen = 0; 1115 ntype = 0; 1116 tso = 0; 1117 ohead = head; 1118 hdr = NULL; 1119 1120 /* iovb[0/1] may be used for writable copy of headers. */ 1121 iov = &iovb[2]; 1122 1123 for (desc = 0; ; desc++, head = (head + 1) % dsize) { 1124 if (head == tail) { 1125 *rhead = head; 1126 return (0); 1127 } 1128 dsc = &sc->esc_txdesc[head]; 1129 dtype = e82545_txdesc_type(dsc->td.lower.data); 1130 1131 if (desc == 0) { 1132 switch (dtype) { 1133 case E1000_TXD_TYP_C: 1134 DPRINTF("tx ctxt desc idx %d: %016jx " 1135 "%08x%08x", 1136 head, dsc->td.buffer_addr, 1137 dsc->td.upper.data, dsc->td.lower.data); 1138 /* Save context and return */ 1139 sc->esc_txctx = dsc->cd; 1140 goto done; 1141 case E1000_TXD_TYP_L: 1142 DPRINTF("tx legacy desc idx %d: %08x%08x", 1143 head, dsc->td.upper.data, dsc->td.lower.data); 1144 /* 1145 * legacy cksum start valid in first descriptor 1146 */ 1147 ntype = dtype; 1148 ckinfo[0].ck_start = dsc->td.upper.fields.css; 1149 break; 1150 case E1000_TXD_TYP_D: 1151 DPRINTF("tx data desc idx %d: %08x%08x", 1152 head, dsc->td.upper.data, dsc->td.lower.data); 1153 ntype = dtype; 1154 break; 1155 default: 1156 break; 1157 } 1158 } else { 1159 /* Descriptor type must be consistent */ 1160 assert(dtype == ntype); 1161 DPRINTF("tx next desc idx %d: %08x%08x", 1162 head, dsc->td.upper.data, dsc->td.lower.data); 1163 } 1164 1165 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length : 1166 dsc->dd.lower.data & 0xFFFFF; 1167 1168 if (len > 0) { 1169 /* Strip checksum supplied by guest. */ 1170 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 && 1171 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0) 1172 len -= 2; 1173 tlen += len; 1174 if (iovcnt < I82545_MAX_TXSEGS) { 1175 iov[iovcnt].iov_base = paddr_guest2host( 1176 sc->esc_ctx, dsc->td.buffer_addr, len); 1177 iov[iovcnt].iov_len = len; 1178 } 1179 iovcnt++; 1180 } 1181 1182 /* 1183 * Pull out info that is valid in the final descriptor 1184 * and exit descriptor loop. 1185 */ 1186 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) { 1187 if (dtype == E1000_TXD_TYP_L) { 1188 if (dsc->td.lower.data & E1000_TXD_CMD_IC) { 1189 ckinfo[0].ck_valid = 1; 1190 ckinfo[0].ck_off = 1191 dsc->td.lower.flags.cso; 1192 ckinfo[0].ck_len = 0; 1193 } 1194 } else { 1195 cd = &sc->esc_txctx; 1196 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE) 1197 tso = 1; 1198 if (dsc->dd.upper.fields.popts & 1199 E1000_TXD_POPTS_IXSM) 1200 ckinfo[0].ck_valid = 1; 1201 if (dsc->dd.upper.fields.popts & 1202 E1000_TXD_POPTS_IXSM || tso) { 1203 ckinfo[0].ck_start = 1204 cd->lower_setup.ip_fields.ipcss; 1205 ckinfo[0].ck_off = 1206 cd->lower_setup.ip_fields.ipcso; 1207 ckinfo[0].ck_len = 1208 cd->lower_setup.ip_fields.ipcse; 1209 } 1210 if (dsc->dd.upper.fields.popts & 1211 E1000_TXD_POPTS_TXSM) 1212 ckinfo[1].ck_valid = 1; 1213 if (dsc->dd.upper.fields.popts & 1214 E1000_TXD_POPTS_TXSM || tso) { 1215 ckinfo[1].ck_start = 1216 cd->upper_setup.tcp_fields.tucss; 1217 ckinfo[1].ck_off = 1218 cd->upper_setup.tcp_fields.tucso; 1219 ckinfo[1].ck_len = 1220 cd->upper_setup.tcp_fields.tucse; 1221 } 1222 } 1223 break; 1224 } 1225 } 1226 1227 if (iovcnt > I82545_MAX_TXSEGS) { 1228 WPRINTF("tx too many descriptors (%d > %d) -- dropped", 1229 iovcnt, I82545_MAX_TXSEGS); 1230 goto done; 1231 } 1232 1233 hdrlen = vlen = 0; 1234 /* Estimate writable space for VLAN header insertion. */ 1235 if ((sc->esc_CTRL & E1000_CTRL_VME) && 1236 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) { 1237 hdrlen = ETHER_ADDR_LEN*2; 1238 vlen = ETHER_VLAN_ENCAP_LEN; 1239 } 1240 if (!tso) { 1241 /* Estimate required writable space for checksums. */ 1242 if (ckinfo[0].ck_valid) 1243 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2); 1244 if (ckinfo[1].ck_valid) 1245 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2); 1246 /* Round up writable space to the first vector. */ 1247 if (hdrlen != 0 && iov[0].iov_len > hdrlen && 1248 iov[0].iov_len < hdrlen + 100) 1249 hdrlen = iov[0].iov_len; 1250 } else { 1251 /* In case of TSO header length provided by software. */ 1252 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len; 1253 } 1254 1255 /* Allocate, fill and prepend writable header vector. */ 1256 if (hdrlen != 0) { 1257 hdr = __builtin_alloca(hdrlen + vlen); 1258 hdr += vlen; 1259 for (left = hdrlen, hdrp = hdr; left > 0; 1260 left -= now, hdrp += now) { 1261 now = MIN(left, iov->iov_len); 1262 memcpy(hdrp, iov->iov_base, now); 1263 iov->iov_base += now; 1264 iov->iov_len -= now; 1265 if (iov->iov_len == 0) { 1266 iov++; 1267 iovcnt--; 1268 } 1269 } 1270 iov--; 1271 iovcnt++; 1272 iov->iov_base = hdr; 1273 iov->iov_len = hdrlen; 1274 } 1275 1276 /* Insert VLAN tag. */ 1277 if (vlen != 0) { 1278 hdr -= ETHER_VLAN_ENCAP_LEN; 1279 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2); 1280 hdrlen += ETHER_VLAN_ENCAP_LEN; 1281 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8; 1282 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff; 1283 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8; 1284 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff; 1285 iov->iov_base = hdr; 1286 iov->iov_len += ETHER_VLAN_ENCAP_LEN; 1287 /* Correct checksum offsets after VLAN tag insertion. */ 1288 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN; 1289 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN; 1290 if (ckinfo[0].ck_len != 0) 1291 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN; 1292 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN; 1293 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN; 1294 if (ckinfo[1].ck_len != 0) 1295 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN; 1296 } 1297 1298 /* Simple non-TSO case. */ 1299 if (!tso) { 1300 /* Calculate checksums and transmit. */ 1301 if (ckinfo[0].ck_valid) 1302 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]); 1303 if (ckinfo[1].ck_valid) 1304 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]); 1305 e82545_transmit_backend(sc, iov, iovcnt); 1306 goto done; 1307 } 1308 1309 /* Doing TSO. */ 1310 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0; 1311 mss = sc->esc_txctx.tcp_seg_setup.fields.mss; 1312 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff); 1313 DPRINTF("tx %s segmentation offload %d+%d/%d bytes %d iovs\r\n", 1314 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt); 1315 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]); 1316 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]); 1317 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off]; 1318 tcpcs = 0; 1319 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */ 1320 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off]; 1321 pv = 1; 1322 pvoff = 0; 1323 for (seg = 0, left = paylen; left > 0; seg++, left -= now) { 1324 now = MIN(left, mss); 1325 1326 /* Construct IOVs for the segment. */ 1327 /* Include whole original header. */ 1328 tiov[0].iov_base = hdr; 1329 tiov[0].iov_len = hdrlen; 1330 tiovcnt = 1; 1331 /* Include respective part of payload IOV. */ 1332 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) { 1333 nnow = MIN(nleft, iov[pv].iov_len - pvoff); 1334 tiov[tiovcnt].iov_base = iov[pv].iov_base + pvoff; 1335 tiov[tiovcnt++].iov_len = nnow; 1336 if (pvoff + nnow == iov[pv].iov_len) { 1337 pv++; 1338 pvoff = 0; 1339 } else 1340 pvoff += nnow; 1341 } 1342 DPRINTF("tx segment %d %d+%d bytes %d iovs\r\n", 1343 seg, hdrlen, now, tiovcnt); 1344 1345 /* Update IP header. */ 1346 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) { 1347 /* IPv4 -- set length and ID */ 1348 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] = 1349 htons(hdrlen - ckinfo[0].ck_start + now); 1350 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1351 htons(ipid + seg); 1352 } else { 1353 /* IPv6 -- set length */ 1354 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1355 htons(hdrlen - ckinfo[0].ck_start - 40 + 1356 now); 1357 } 1358 1359 /* Update pseudo-header checksum. */ 1360 tcpsum = tcpcs; 1361 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now); 1362 1363 /* Update TCP/UDP headers. */ 1364 if (tcp) { 1365 /* Update sequence number and FIN/PUSH flags. */ 1366 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1367 htonl(tcpseq + paylen - left); 1368 if (now < left) { 1369 hdr[ckinfo[1].ck_start + 13] &= 1370 ~(TH_FIN | TH_PUSH); 1371 } 1372 } else { 1373 /* Update payload length. */ 1374 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1375 hdrlen - ckinfo[1].ck_start + now; 1376 } 1377 1378 /* Calculate checksums and transmit. */ 1379 if (ckinfo[0].ck_valid) { 1380 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs; 1381 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]); 1382 } 1383 if (ckinfo[1].ck_valid) { 1384 *(uint16_t *)&hdr[ckinfo[1].ck_off] = 1385 e82545_carry(tcpsum); 1386 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]); 1387 } 1388 e82545_transmit_backend(sc, tiov, tiovcnt); 1389 } 1390 1391 done: 1392 head = (head + 1) % dsize; 1393 e82545_transmit_done(sc, ohead, head, dsize, tdwb); 1394 1395 *rhead = head; 1396 return (desc + 1); 1397 } 1398 1399 static void 1400 e82545_tx_run(struct e82545_softc *sc) 1401 { 1402 uint32_t cause; 1403 uint16_t head, rhead, tail, size; 1404 int lim, tdwb, sent; 1405 1406 head = sc->esc_TDH; 1407 tail = sc->esc_TDT; 1408 size = sc->esc_TDLEN / 16; 1409 DPRINTF("tx_run: head %x, rhead %x, tail %x", 1410 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1411 1412 pthread_mutex_unlock(&sc->esc_mtx); 1413 rhead = head; 1414 tdwb = 0; 1415 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) { 1416 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb); 1417 if (sent == 0) 1418 break; 1419 head = rhead; 1420 } 1421 pthread_mutex_lock(&sc->esc_mtx); 1422 1423 sc->esc_TDH = head; 1424 sc->esc_TDHr = rhead; 1425 cause = 0; 1426 if (tdwb) 1427 cause |= E1000_ICR_TXDW; 1428 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT) 1429 cause |= E1000_ICR_TXQE; 1430 if (cause) 1431 e82545_icr_assert(sc, cause); 1432 1433 DPRINTF("tx_run done: head %x, rhead %x, tail %x", 1434 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1435 } 1436 1437 static void * 1438 e82545_tx_thread(void *param) 1439 { 1440 struct e82545_softc *sc = param; 1441 1442 pthread_mutex_lock(&sc->esc_mtx); 1443 for (;;) { 1444 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) { 1445 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT) 1446 break; 1447 sc->esc_tx_active = 0; 1448 if (sc->esc_tx_enabled == 0) 1449 pthread_cond_signal(&sc->esc_tx_cond); 1450 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1451 } 1452 sc->esc_tx_active = 1; 1453 1454 /* Process some tx descriptors. Lock dropped inside. */ 1455 e82545_tx_run(sc); 1456 } 1457 #ifndef __FreeBSD__ 1458 return (NULL); 1459 #endif 1460 } 1461 1462 static void 1463 e82545_tx_start(struct e82545_softc *sc) 1464 { 1465 1466 if (sc->esc_tx_active == 0) 1467 pthread_cond_signal(&sc->esc_tx_cond); 1468 } 1469 1470 static void 1471 e82545_tx_enable(struct e82545_softc *sc) 1472 { 1473 1474 sc->esc_tx_enabled = 1; 1475 } 1476 1477 static void 1478 e82545_tx_disable(struct e82545_softc *sc) 1479 { 1480 1481 sc->esc_tx_enabled = 0; 1482 while (sc->esc_tx_active) 1483 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1484 } 1485 1486 static void 1487 e82545_rx_enable(struct e82545_softc *sc) 1488 { 1489 1490 sc->esc_rx_enabled = 1; 1491 } 1492 1493 static void 1494 e82545_rx_disable(struct e82545_softc *sc) 1495 { 1496 1497 sc->esc_rx_enabled = 0; 1498 while (sc->esc_rx_active) 1499 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx); 1500 } 1501 1502 static void 1503 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval) 1504 { 1505 struct eth_uni *eu; 1506 int idx; 1507 1508 idx = reg >> 1; 1509 assert(idx < 15); 1510 1511 eu = &sc->esc_uni[idx]; 1512 1513 if (reg & 0x1) { 1514 /* RAH */ 1515 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV); 1516 eu->eu_addrsel = (wval >> 16) & 0x3; 1517 eu->eu_eth.octet[5] = wval >> 8; 1518 eu->eu_eth.octet[4] = wval; 1519 } else { 1520 /* RAL */ 1521 eu->eu_eth.octet[3] = wval >> 24; 1522 eu->eu_eth.octet[2] = wval >> 16; 1523 eu->eu_eth.octet[1] = wval >> 8; 1524 eu->eu_eth.octet[0] = wval; 1525 } 1526 } 1527 1528 static uint32_t 1529 e82545_read_ra(struct e82545_softc *sc, int reg) 1530 { 1531 struct eth_uni *eu; 1532 uint32_t retval; 1533 int idx; 1534 1535 idx = reg >> 1; 1536 assert(idx < 15); 1537 1538 eu = &sc->esc_uni[idx]; 1539 1540 if (reg & 0x1) { 1541 /* RAH */ 1542 retval = (eu->eu_valid << 31) | 1543 (eu->eu_addrsel << 16) | 1544 (eu->eu_eth.octet[5] << 8) | 1545 eu->eu_eth.octet[4]; 1546 } else { 1547 /* RAL */ 1548 retval = (eu->eu_eth.octet[3] << 24) | 1549 (eu->eu_eth.octet[2] << 16) | 1550 (eu->eu_eth.octet[1] << 8) | 1551 eu->eu_eth.octet[0]; 1552 } 1553 1554 return (retval); 1555 } 1556 1557 static void 1558 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value) 1559 { 1560 int ridx; 1561 1562 if (offset & 0x3) { 1563 DPRINTF("Unaligned register write offset:0x%x value:0x%x", offset, value); 1564 return; 1565 } 1566 DPRINTF("Register write: 0x%x value: 0x%x", offset, value); 1567 1568 switch (offset) { 1569 case E1000_CTRL: 1570 case E1000_CTRL_DUP: 1571 e82545_devctl(sc, value); 1572 break; 1573 case E1000_FCAL: 1574 sc->esc_FCAL = value; 1575 break; 1576 case E1000_FCAH: 1577 sc->esc_FCAH = value & ~0xFFFF0000; 1578 break; 1579 case E1000_FCT: 1580 sc->esc_FCT = value & ~0xFFFF0000; 1581 break; 1582 case E1000_VET: 1583 sc->esc_VET = value & ~0xFFFF0000; 1584 break; 1585 case E1000_FCTTV: 1586 sc->esc_FCTTV = value & ~0xFFFF0000; 1587 break; 1588 case E1000_LEDCTL: 1589 sc->esc_LEDCTL = value & ~0x30303000; 1590 break; 1591 case E1000_PBA: 1592 sc->esc_PBA = value & 0x0000FF80; 1593 break; 1594 case E1000_ICR: 1595 case E1000_ITR: 1596 case E1000_ICS: 1597 case E1000_IMS: 1598 case E1000_IMC: 1599 e82545_intr_write(sc, offset, value); 1600 break; 1601 case E1000_RCTL: 1602 e82545_rx_ctl(sc, value); 1603 break; 1604 case E1000_FCRTL: 1605 sc->esc_FCRTL = value & ~0xFFFF0007; 1606 break; 1607 case E1000_FCRTH: 1608 sc->esc_FCRTH = value & ~0xFFFF0007; 1609 break; 1610 case E1000_RDBAL(0): 1611 sc->esc_RDBAL = value & ~0xF; 1612 if (sc->esc_rx_enabled) { 1613 /* Apparently legal: update cached address */ 1614 e82545_rx_update_rdba(sc); 1615 } 1616 break; 1617 case E1000_RDBAH(0): 1618 assert(!sc->esc_rx_enabled); 1619 sc->esc_RDBAH = value; 1620 break; 1621 case E1000_RDLEN(0): 1622 assert(!sc->esc_rx_enabled); 1623 sc->esc_RDLEN = value & ~0xFFF0007F; 1624 break; 1625 case E1000_RDH(0): 1626 /* XXX should only ever be zero ? Range check ? */ 1627 sc->esc_RDH = value; 1628 break; 1629 case E1000_RDT(0): 1630 /* XXX if this opens up the rx ring, do something ? */ 1631 sc->esc_RDT = value; 1632 break; 1633 case E1000_RDTR: 1634 /* ignore FPD bit 31 */ 1635 sc->esc_RDTR = value & ~0xFFFF0000; 1636 break; 1637 case E1000_RXDCTL(0): 1638 sc->esc_RXDCTL = value & ~0xFEC0C0C0; 1639 break; 1640 case E1000_RADV: 1641 sc->esc_RADV = value & ~0xFFFF0000; 1642 break; 1643 case E1000_RSRPD: 1644 sc->esc_RSRPD = value & ~0xFFFFF000; 1645 break; 1646 case E1000_RXCSUM: 1647 sc->esc_RXCSUM = value & ~0xFFFFF800; 1648 break; 1649 case E1000_TXCW: 1650 sc->esc_TXCW = value & ~0x3FFF0000; 1651 break; 1652 case E1000_TCTL: 1653 e82545_tx_ctl(sc, value); 1654 break; 1655 case E1000_TIPG: 1656 sc->esc_TIPG = value; 1657 break; 1658 case E1000_AIT: 1659 sc->esc_AIT = value; 1660 break; 1661 case E1000_TDBAL(0): 1662 sc->esc_TDBAL = value & ~0xF; 1663 if (sc->esc_tx_enabled) { 1664 /* Apparently legal */ 1665 e82545_tx_update_tdba(sc); 1666 } 1667 break; 1668 case E1000_TDBAH(0): 1669 //assert(!sc->esc_tx_enabled); 1670 sc->esc_TDBAH = value; 1671 break; 1672 case E1000_TDLEN(0): 1673 //assert(!sc->esc_tx_enabled); 1674 sc->esc_TDLEN = value & ~0xFFF0007F; 1675 break; 1676 case E1000_TDH(0): 1677 //assert(!sc->esc_tx_enabled); 1678 /* XXX should only ever be zero ? Range check ? */ 1679 sc->esc_TDHr = sc->esc_TDH = value; 1680 break; 1681 case E1000_TDT(0): 1682 /* XXX range check ? */ 1683 sc->esc_TDT = value; 1684 if (sc->esc_tx_enabled) 1685 e82545_tx_start(sc); 1686 break; 1687 case E1000_TIDV: 1688 sc->esc_TIDV = value & ~0xFFFF0000; 1689 break; 1690 case E1000_TXDCTL(0): 1691 //assert(!sc->esc_tx_enabled); 1692 sc->esc_TXDCTL = value & ~0xC0C0C0; 1693 break; 1694 case E1000_TADV: 1695 sc->esc_TADV = value & ~0xFFFF0000; 1696 break; 1697 case E1000_RAL(0) ... E1000_RAH(15): 1698 /* convert to u32 offset */ 1699 ridx = (offset - E1000_RAL(0)) >> 2; 1700 e82545_write_ra(sc, ridx, value); 1701 break; 1702 case E1000_MTA ... (E1000_MTA + (127*4)): 1703 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value; 1704 break; 1705 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1706 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value; 1707 break; 1708 case E1000_EECD: 1709 { 1710 //DPRINTF("EECD write 0x%x -> 0x%x", sc->eeprom_control, value); 1711 /* edge triggered low->high */ 1712 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ? 1713 0 : (value & E1000_EECD_SK)); 1714 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS| 1715 E1000_EECD_DI|E1000_EECD_REQ); 1716 sc->eeprom_control &= ~eecd_mask; 1717 sc->eeprom_control |= (value & eecd_mask); 1718 /* grant/revoke immediately */ 1719 if (value & E1000_EECD_REQ) { 1720 sc->eeprom_control |= E1000_EECD_GNT; 1721 } else { 1722 sc->eeprom_control &= ~E1000_EECD_GNT; 1723 } 1724 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) { 1725 e82545_eecd_strobe(sc); 1726 } 1727 return; 1728 } 1729 case E1000_MDIC: 1730 { 1731 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >> 1732 E1000_MDIC_REG_SHIFT); 1733 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >> 1734 E1000_MDIC_PHY_SHIFT); 1735 sc->mdi_control = 1736 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST)); 1737 if ((value & E1000_MDIC_READY) != 0) { 1738 DPRINTF("Incorrect MDIC ready bit: 0x%x", value); 1739 return; 1740 } 1741 switch (value & E82545_MDIC_OP_MASK) { 1742 case E1000_MDIC_OP_READ: 1743 sc->mdi_control &= ~E82545_MDIC_DATA_MASK; 1744 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr); 1745 break; 1746 case E1000_MDIC_OP_WRITE: 1747 e82545_write_mdi(sc, reg_addr, phy_addr, 1748 value & E82545_MDIC_DATA_MASK); 1749 break; 1750 default: 1751 DPRINTF("Unknown MDIC op: 0x%x", value); 1752 return; 1753 } 1754 /* TODO: barrier? */ 1755 sc->mdi_control |= E1000_MDIC_READY; 1756 if (value & E82545_MDIC_IE) { 1757 // TODO: generate interrupt 1758 } 1759 return; 1760 } 1761 case E1000_MANC: 1762 case E1000_STATUS: 1763 return; 1764 default: 1765 DPRINTF("Unknown write register: 0x%x value:%x", offset, value); 1766 return; 1767 } 1768 } 1769 1770 static uint32_t 1771 e82545_read_register(struct e82545_softc *sc, uint32_t offset) 1772 { 1773 uint32_t retval; 1774 int ridx; 1775 1776 if (offset & 0x3) { 1777 DPRINTF("Unaligned register read offset:0x%x", offset); 1778 return 0; 1779 } 1780 1781 DPRINTF("Register read: 0x%x", offset); 1782 1783 switch (offset) { 1784 case E1000_CTRL: 1785 retval = sc->esc_CTRL; 1786 break; 1787 case E1000_STATUS: 1788 retval = E1000_STATUS_FD | E1000_STATUS_LU | 1789 E1000_STATUS_SPEED_1000; 1790 break; 1791 case E1000_FCAL: 1792 retval = sc->esc_FCAL; 1793 break; 1794 case E1000_FCAH: 1795 retval = sc->esc_FCAH; 1796 break; 1797 case E1000_FCT: 1798 retval = sc->esc_FCT; 1799 break; 1800 case E1000_VET: 1801 retval = sc->esc_VET; 1802 break; 1803 case E1000_FCTTV: 1804 retval = sc->esc_FCTTV; 1805 break; 1806 case E1000_LEDCTL: 1807 retval = sc->esc_LEDCTL; 1808 break; 1809 case E1000_PBA: 1810 retval = sc->esc_PBA; 1811 break; 1812 case E1000_ICR: 1813 case E1000_ITR: 1814 case E1000_ICS: 1815 case E1000_IMS: 1816 case E1000_IMC: 1817 retval = e82545_intr_read(sc, offset); 1818 break; 1819 case E1000_RCTL: 1820 retval = sc->esc_RCTL; 1821 break; 1822 case E1000_FCRTL: 1823 retval = sc->esc_FCRTL; 1824 break; 1825 case E1000_FCRTH: 1826 retval = sc->esc_FCRTH; 1827 break; 1828 case E1000_RDBAL(0): 1829 retval = sc->esc_RDBAL; 1830 break; 1831 case E1000_RDBAH(0): 1832 retval = sc->esc_RDBAH; 1833 break; 1834 case E1000_RDLEN(0): 1835 retval = sc->esc_RDLEN; 1836 break; 1837 case E1000_RDH(0): 1838 retval = sc->esc_RDH; 1839 break; 1840 case E1000_RDT(0): 1841 retval = sc->esc_RDT; 1842 break; 1843 case E1000_RDTR: 1844 retval = sc->esc_RDTR; 1845 break; 1846 case E1000_RXDCTL(0): 1847 retval = sc->esc_RXDCTL; 1848 break; 1849 case E1000_RADV: 1850 retval = sc->esc_RADV; 1851 break; 1852 case E1000_RSRPD: 1853 retval = sc->esc_RSRPD; 1854 break; 1855 case E1000_RXCSUM: 1856 retval = sc->esc_RXCSUM; 1857 break; 1858 case E1000_TXCW: 1859 retval = sc->esc_TXCW; 1860 break; 1861 case E1000_TCTL: 1862 retval = sc->esc_TCTL; 1863 break; 1864 case E1000_TIPG: 1865 retval = sc->esc_TIPG; 1866 break; 1867 case E1000_AIT: 1868 retval = sc->esc_AIT; 1869 break; 1870 case E1000_TDBAL(0): 1871 retval = sc->esc_TDBAL; 1872 break; 1873 case E1000_TDBAH(0): 1874 retval = sc->esc_TDBAH; 1875 break; 1876 case E1000_TDLEN(0): 1877 retval = sc->esc_TDLEN; 1878 break; 1879 case E1000_TDH(0): 1880 retval = sc->esc_TDH; 1881 break; 1882 case E1000_TDT(0): 1883 retval = sc->esc_TDT; 1884 break; 1885 case E1000_TIDV: 1886 retval = sc->esc_TIDV; 1887 break; 1888 case E1000_TXDCTL(0): 1889 retval = sc->esc_TXDCTL; 1890 break; 1891 case E1000_TADV: 1892 retval = sc->esc_TADV; 1893 break; 1894 case E1000_RAL(0) ... E1000_RAH(15): 1895 /* convert to u32 offset */ 1896 ridx = (offset - E1000_RAL(0)) >> 2; 1897 retval = e82545_read_ra(sc, ridx); 1898 break; 1899 case E1000_MTA ... (E1000_MTA + (127*4)): 1900 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2]; 1901 break; 1902 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1903 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2]; 1904 break; 1905 case E1000_EECD: 1906 //DPRINTF("EECD read %x", sc->eeprom_control); 1907 retval = sc->eeprom_control; 1908 break; 1909 case E1000_MDIC: 1910 retval = sc->mdi_control; 1911 break; 1912 case E1000_MANC: 1913 retval = 0; 1914 break; 1915 /* stats that we emulate. */ 1916 case E1000_MPC: 1917 retval = sc->missed_pkt_count; 1918 break; 1919 case E1000_PRC64: 1920 retval = sc->pkt_rx_by_size[0]; 1921 break; 1922 case E1000_PRC127: 1923 retval = sc->pkt_rx_by_size[1]; 1924 break; 1925 case E1000_PRC255: 1926 retval = sc->pkt_rx_by_size[2]; 1927 break; 1928 case E1000_PRC511: 1929 retval = sc->pkt_rx_by_size[3]; 1930 break; 1931 case E1000_PRC1023: 1932 retval = sc->pkt_rx_by_size[4]; 1933 break; 1934 case E1000_PRC1522: 1935 retval = sc->pkt_rx_by_size[5]; 1936 break; 1937 case E1000_GPRC: 1938 retval = sc->good_pkt_rx_count; 1939 break; 1940 case E1000_BPRC: 1941 retval = sc->bcast_pkt_rx_count; 1942 break; 1943 case E1000_MPRC: 1944 retval = sc->mcast_pkt_rx_count; 1945 break; 1946 case E1000_GPTC: 1947 case E1000_TPT: 1948 retval = sc->good_pkt_tx_count; 1949 break; 1950 case E1000_GORCL: 1951 retval = (uint32_t)sc->good_octets_rx; 1952 break; 1953 case E1000_GORCH: 1954 retval = (uint32_t)(sc->good_octets_rx >> 32); 1955 break; 1956 case E1000_TOTL: 1957 case E1000_GOTCL: 1958 retval = (uint32_t)sc->good_octets_tx; 1959 break; 1960 case E1000_TOTH: 1961 case E1000_GOTCH: 1962 retval = (uint32_t)(sc->good_octets_tx >> 32); 1963 break; 1964 case E1000_ROC: 1965 retval = sc->oversize_rx_count; 1966 break; 1967 case E1000_TORL: 1968 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets); 1969 break; 1970 case E1000_TORH: 1971 retval = (uint32_t)((sc->good_octets_rx + 1972 sc->missed_octets) >> 32); 1973 break; 1974 case E1000_TPR: 1975 retval = sc->good_pkt_rx_count + sc->missed_pkt_count + 1976 sc->oversize_rx_count; 1977 break; 1978 case E1000_PTC64: 1979 retval = sc->pkt_tx_by_size[0]; 1980 break; 1981 case E1000_PTC127: 1982 retval = sc->pkt_tx_by_size[1]; 1983 break; 1984 case E1000_PTC255: 1985 retval = sc->pkt_tx_by_size[2]; 1986 break; 1987 case E1000_PTC511: 1988 retval = sc->pkt_tx_by_size[3]; 1989 break; 1990 case E1000_PTC1023: 1991 retval = sc->pkt_tx_by_size[4]; 1992 break; 1993 case E1000_PTC1522: 1994 retval = sc->pkt_tx_by_size[5]; 1995 break; 1996 case E1000_MPTC: 1997 retval = sc->mcast_pkt_tx_count; 1998 break; 1999 case E1000_BPTC: 2000 retval = sc->bcast_pkt_tx_count; 2001 break; 2002 case E1000_TSCTC: 2003 retval = sc->tso_tx_count; 2004 break; 2005 /* stats that are always 0. */ 2006 case E1000_CRCERRS: 2007 case E1000_ALGNERRC: 2008 case E1000_SYMERRS: 2009 case E1000_RXERRC: 2010 case E1000_SCC: 2011 case E1000_ECOL: 2012 case E1000_MCC: 2013 case E1000_LATECOL: 2014 case E1000_COLC: 2015 case E1000_DC: 2016 case E1000_TNCRS: 2017 case E1000_SEC: 2018 case E1000_CEXTERR: 2019 case E1000_RLEC: 2020 case E1000_XONRXC: 2021 case E1000_XONTXC: 2022 case E1000_XOFFRXC: 2023 case E1000_XOFFTXC: 2024 case E1000_FCRUC: 2025 case E1000_RNBC: 2026 case E1000_RUC: 2027 case E1000_RFC: 2028 case E1000_RJC: 2029 case E1000_MGTPRC: 2030 case E1000_MGTPDC: 2031 case E1000_MGTPTC: 2032 case E1000_TSCTFC: 2033 retval = 0; 2034 break; 2035 default: 2036 DPRINTF("Unknown read register: 0x%x", offset); 2037 retval = 0; 2038 break; 2039 } 2040 2041 return (retval); 2042 } 2043 2044 static void 2045 e82545_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2046 uint64_t offset, int size, uint64_t value) 2047 { 2048 struct e82545_softc *sc; 2049 2050 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d", baridx, offset, value, size); 2051 2052 sc = pi->pi_arg; 2053 2054 pthread_mutex_lock(&sc->esc_mtx); 2055 2056 switch (baridx) { 2057 case E82545_BAR_IO: 2058 switch (offset) { 2059 case E82545_IOADDR: 2060 if (size != 4) { 2061 DPRINTF("Wrong io addr write sz:%d value:0x%lx", size, value); 2062 } else 2063 sc->io_addr = (uint32_t)value; 2064 break; 2065 case E82545_IODATA: 2066 if (size != 4) { 2067 DPRINTF("Wrong io data write size:%d value:0x%lx", size, value); 2068 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2069 DPRINTF("Non-register io write addr:0x%x value:0x%lx", sc->io_addr, value); 2070 } else 2071 e82545_write_register(sc, sc->io_addr, 2072 (uint32_t)value); 2073 break; 2074 default: 2075 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d", offset, value, size); 2076 break; 2077 } 2078 break; 2079 case E82545_BAR_REGISTER: 2080 if (size != 4) { 2081 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx", size, offset, value); 2082 } else 2083 e82545_write_register(sc, (uint32_t)offset, 2084 (uint32_t)value); 2085 break; 2086 default: 2087 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d", 2088 baridx, offset, value, size); 2089 } 2090 2091 pthread_mutex_unlock(&sc->esc_mtx); 2092 } 2093 2094 static uint64_t 2095 e82545_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2096 uint64_t offset, int size) 2097 { 2098 struct e82545_softc *sc; 2099 uint64_t retval; 2100 2101 //DPRINTF("Read bar:%d offset:0x%lx size:%d", baridx, offset, size); 2102 sc = pi->pi_arg; 2103 retval = 0; 2104 2105 pthread_mutex_lock(&sc->esc_mtx); 2106 2107 switch (baridx) { 2108 case E82545_BAR_IO: 2109 switch (offset) { 2110 case E82545_IOADDR: 2111 if (size != 4) { 2112 DPRINTF("Wrong io addr read sz:%d", size); 2113 } else 2114 retval = sc->io_addr; 2115 break; 2116 case E82545_IODATA: 2117 if (size != 4) { 2118 DPRINTF("Wrong io data read sz:%d", size); 2119 } 2120 if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2121 DPRINTF("Non-register io read addr:0x%x", 2122 sc->io_addr); 2123 } else 2124 retval = e82545_read_register(sc, sc->io_addr); 2125 break; 2126 default: 2127 DPRINTF("Unknown io bar read offset:0x%lx size:%d", 2128 offset, size); 2129 break; 2130 } 2131 break; 2132 case E82545_BAR_REGISTER: 2133 if (size != 4) { 2134 DPRINTF("Wrong register read size:%d offset:0x%lx", 2135 size, offset); 2136 } else 2137 retval = e82545_read_register(sc, (uint32_t)offset); 2138 break; 2139 default: 2140 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d", 2141 baridx, offset, size); 2142 break; 2143 } 2144 2145 pthread_mutex_unlock(&sc->esc_mtx); 2146 2147 return (retval); 2148 } 2149 2150 static void 2151 e82545_reset(struct e82545_softc *sc, int drvr) 2152 { 2153 int i; 2154 2155 e82545_rx_disable(sc); 2156 e82545_tx_disable(sc); 2157 2158 /* clear outstanding interrupts */ 2159 if (sc->esc_irq_asserted) 2160 pci_lintr_deassert(sc->esc_pi); 2161 2162 /* misc */ 2163 if (!drvr) { 2164 sc->esc_FCAL = 0; 2165 sc->esc_FCAH = 0; 2166 sc->esc_FCT = 0; 2167 sc->esc_VET = 0; 2168 sc->esc_FCTTV = 0; 2169 } 2170 sc->esc_LEDCTL = 0x07061302; 2171 sc->esc_PBA = 0x00100030; 2172 2173 /* start nvm in opcode mode. */ 2174 sc->nvm_opaddr = 0; 2175 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 2176 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 2177 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN; 2178 e82545_init_eeprom(sc); 2179 2180 /* interrupt */ 2181 sc->esc_ICR = 0; 2182 sc->esc_ITR = 250; 2183 sc->esc_ICS = 0; 2184 sc->esc_IMS = 0; 2185 sc->esc_IMC = 0; 2186 2187 /* L2 filters */ 2188 if (!drvr) { 2189 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan)); 2190 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast)); 2191 memset(sc->esc_uni, 0, sizeof(sc->esc_uni)); 2192 2193 /* XXX not necessary on 82545 ?? */ 2194 sc->esc_uni[0].eu_valid = 1; 2195 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet, 2196 ETHER_ADDR_LEN); 2197 } else { 2198 /* Clear RAH valid bits */ 2199 for (i = 0; i < 16; i++) 2200 sc->esc_uni[i].eu_valid = 0; 2201 } 2202 2203 /* receive */ 2204 if (!drvr) { 2205 sc->esc_RDBAL = 0; 2206 sc->esc_RDBAH = 0; 2207 } 2208 sc->esc_RCTL = 0; 2209 sc->esc_FCRTL = 0; 2210 sc->esc_FCRTH = 0; 2211 sc->esc_RDLEN = 0; 2212 sc->esc_RDH = 0; 2213 sc->esc_RDT = 0; 2214 sc->esc_RDTR = 0; 2215 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */ 2216 sc->esc_RADV = 0; 2217 sc->esc_RXCSUM = 0; 2218 2219 /* transmit */ 2220 if (!drvr) { 2221 sc->esc_TDBAL = 0; 2222 sc->esc_TDBAH = 0; 2223 sc->esc_TIPG = 0; 2224 sc->esc_AIT = 0; 2225 sc->esc_TIDV = 0; 2226 sc->esc_TADV = 0; 2227 } 2228 sc->esc_tdba = 0; 2229 sc->esc_txdesc = NULL; 2230 sc->esc_TXCW = 0; 2231 sc->esc_TCTL = 0; 2232 sc->esc_TDLEN = 0; 2233 sc->esc_TDT = 0; 2234 sc->esc_TDHr = sc->esc_TDH = 0; 2235 sc->esc_TXDCTL = 0; 2236 } 2237 2238 static void 2239 e82545_open_tap(struct e82545_softc *sc, char *opts) 2240 { 2241 char tbuf[80]; 2242 #ifndef WITHOUT_CAPSICUM 2243 cap_rights_t rights; 2244 #endif 2245 2246 if (opts == NULL) { 2247 sc->esc_tapfd = -1; 2248 return; 2249 } 2250 2251 strcpy(tbuf, "/dev/"); 2252 strlcat(tbuf, opts, sizeof(tbuf)); 2253 2254 sc->esc_tapfd = open(tbuf, O_RDWR); 2255 if (sc->esc_tapfd == -1) { 2256 DPRINTF("unable to open tap device %s\n", opts); 2257 exit(4); 2258 } 2259 2260 /* 2261 * Set non-blocking and register for read 2262 * notifications with the event loop 2263 */ 2264 int opt = 1; 2265 if (ioctl(sc->esc_tapfd, FIONBIO, &opt) < 0) { 2266 WPRINTF("tap device O_NONBLOCK failed: %d\n", errno); 2267 close(sc->esc_tapfd); 2268 sc->esc_tapfd = -1; 2269 } 2270 2271 #ifndef WITHOUT_CAPSICUM 2272 cap_rights_init(&rights, CAP_EVENT, CAP_READ, CAP_WRITE); 2273 if (caph_rights_limit(sc->esc_tapfd, &rights) == -1) 2274 errx(EX_OSERR, "Unable to apply rights for sandbox"); 2275 #endif 2276 2277 #ifdef __FreeBSD__ 2278 sc->esc_mevp = mevent_add(sc->esc_tapfd, 2279 EVF_READ, 2280 e82545_tap_callback, 2281 sc); 2282 if (sc->esc_mevp == NULL) { 2283 DPRINTF("Could not register mevent %d\n", EVF_READ); 2284 close(sc->esc_tapfd); 2285 sc->esc_tapfd = -1; 2286 } 2287 #endif 2288 } 2289 2290 static int 2291 e82545_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2292 { 2293 char nstr[80]; 2294 struct e82545_softc *sc; 2295 char *optscopy; 2296 char *vtopts; 2297 int mac_provided; 2298 2299 DPRINTF("Loading with options: %s", opts); 2300 2301 /* Setup our softc */ 2302 sc = calloc(1, sizeof(*sc)); 2303 2304 pi->pi_arg = sc; 2305 sc->esc_pi = pi; 2306 sc->esc_ctx = ctx; 2307 2308 pthread_mutex_init(&sc->esc_mtx, NULL); 2309 pthread_cond_init(&sc->esc_rx_cond, NULL); 2310 pthread_cond_init(&sc->esc_tx_cond, NULL); 2311 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc); 2312 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot, 2313 pi->pi_func); 2314 pthread_set_name_np(sc->esc_tx_tid, nstr); 2315 2316 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER); 2317 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL); 2318 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK); 2319 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET); 2320 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID); 2321 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL); 2322 2323 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL); 2324 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1); 2325 2326 /* TODO: this card also supports msi, but the freebsd driver for it 2327 * does not, so I have not implemented it. */ 2328 pci_lintr_request(pi); 2329 2330 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32, 2331 E82545_BAR_REGISTER_LEN); 2332 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32, 2333 E82545_BAR_FLASH_LEN); 2334 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO, 2335 E82545_BAR_IO_LEN); 2336 2337 /* 2338 * Attempt to open the tap device and read the MAC address 2339 * if specified. Copied from virtio-net, slightly modified. 2340 */ 2341 mac_provided = 0; 2342 sc->esc_tapfd = -1; 2343 if (opts != NULL) { 2344 int err = 0; 2345 2346 optscopy = vtopts = strdup(opts); 2347 (void) strsep(&vtopts, ","); 2348 2349 /* 2350 * Parse the list of options in the form 2351 * key1=value1,...,keyN=valueN. 2352 */ 2353 while (vtopts != NULL) { 2354 char *value = vtopts; 2355 char *key; 2356 2357 key = strsep(&value, "="); 2358 if (value == NULL) 2359 break; 2360 vtopts = value; 2361 (void) strsep(&vtopts, ","); 2362 2363 if (strcmp(key, "mac") == 0) { 2364 err = net_parsemac(value, sc->esc_mac.octet); 2365 if (err) 2366 break; 2367 mac_provided = 1; 2368 } 2369 } 2370 2371 if (strncmp(optscopy, "tap", 3) == 0 || 2372 strncmp(optscopy, "vmnet", 5) == 0) 2373 e82545_open_tap(sc, optscopy); 2374 2375 free(optscopy); 2376 } 2377 2378 if (!mac_provided) { 2379 net_genmac(pi, sc->esc_mac.octet); 2380 } 2381 2382 /* H/w initiated reset */ 2383 e82545_reset(sc, 0); 2384 2385 return (0); 2386 } 2387 2388 struct pci_devemu pci_de_e82545 = { 2389 .pe_emu = "e1000", 2390 .pe_init = e82545_init, 2391 .pe_barwrite = e82545_write, 2392 .pe_barread = e82545_read 2393 }; 2394 PCI_EMUL_SET(pci_de_e82545); 2395 2396