1 /* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 5 * Copyright (c) 2015 Peter Grehan <grehan@freebsd.org> 6 * Copyright (c) 2013 Jeremiah Lott, Avere Systems 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer 14 * in this position and unchanged. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/types.h> 36 #ifndef WITHOUT_CAPSICUM 37 #include <sys/capsicum.h> 38 #endif 39 #include <sys/limits.h> 40 #include <sys/ioctl.h> 41 #include <sys/uio.h> 42 #include <net/ethernet.h> 43 #include <netinet/in.h> 44 #include <netinet/tcp.h> 45 #ifndef __FreeBSD__ 46 #include <sys/filio.h> 47 #endif 48 49 #ifndef WITHOUT_CAPSICUM 50 #include <capsicum_helpers.h> 51 #endif 52 #include <err.h> 53 #include <errno.h> 54 #include <fcntl.h> 55 #include <md5.h> 56 #include <stdio.h> 57 #include <stdlib.h> 58 #include <string.h> 59 #include <sysexits.h> 60 #include <unistd.h> 61 #include <pthread.h> 62 #include <pthread_np.h> 63 64 #include "e1000_regs.h" 65 #include "e1000_defines.h" 66 #include "mii.h" 67 68 #include "bhyverun.h" 69 #include "config.h" 70 #include "debug.h" 71 #include "pci_emul.h" 72 #include "mevent.h" 73 #include "net_utils.h" 74 75 /* Hardware/register definitions XXX: move some to common code. */ 76 #define E82545_VENDOR_ID_INTEL 0x8086 77 #define E82545_DEV_ID_82545EM_COPPER 0x100F 78 #define E82545_SUBDEV_ID 0x1008 79 80 #define E82545_REVISION_4 4 81 82 #define E82545_MDIC_DATA_MASK 0x0000FFFF 83 #define E82545_MDIC_OP_MASK 0x0c000000 84 #define E82545_MDIC_IE 0x20000000 85 86 #define E82545_EECD_FWE_DIS 0x00000010 /* Flash writes disabled */ 87 #define E82545_EECD_FWE_EN 0x00000020 /* Flash writes enabled */ 88 #define E82545_EECD_FWE_MASK 0x00000030 /* Flash writes mask */ 89 90 #define E82545_BAR_REGISTER 0 91 #define E82545_BAR_REGISTER_LEN (128*1024) 92 #define E82545_BAR_FLASH 1 93 #define E82545_BAR_FLASH_LEN (64*1024) 94 #define E82545_BAR_IO 2 95 #define E82545_BAR_IO_LEN 8 96 97 #define E82545_IOADDR 0x00000000 98 #define E82545_IODATA 0x00000004 99 #define E82545_IO_REGISTER_MAX 0x0001FFFF 100 #define E82545_IO_FLASH_BASE 0x00080000 101 #define E82545_IO_FLASH_MAX 0x000FFFFF 102 103 #define E82545_ARRAY_ENTRY(reg, offset) (reg + (offset<<2)) 104 #define E82545_RAR_MAX 15 105 #define E82545_MTA_MAX 127 106 #define E82545_VFTA_MAX 127 107 108 /* Slightly modified from the driver versions, hardcoded for 3 opcode bits, 109 * followed by 6 address bits. 110 * TODO: make opcode bits and addr bits configurable? 111 * NVM Commands - Microwire */ 112 #define E82545_NVM_OPCODE_BITS 3 113 #define E82545_NVM_ADDR_BITS 6 114 #define E82545_NVM_DATA_BITS 16 115 #define E82545_NVM_OPADDR_BITS (E82545_NVM_OPCODE_BITS + E82545_NVM_ADDR_BITS) 116 #define E82545_NVM_ADDR_MASK ((1 << E82545_NVM_ADDR_BITS)-1) 117 #define E82545_NVM_OPCODE_MASK \ 118 (((1 << E82545_NVM_OPCODE_BITS) - 1) << E82545_NVM_ADDR_BITS) 119 #define E82545_NVM_OPCODE_READ (0x6 << E82545_NVM_ADDR_BITS) /* read */ 120 #define E82545_NVM_OPCODE_WRITE (0x5 << E82545_NVM_ADDR_BITS) /* write */ 121 #define E82545_NVM_OPCODE_ERASE (0x7 << E82545_NVM_ADDR_BITS) /* erase */ 122 #define E82545_NVM_OPCODE_EWEN (0x4 << E82545_NVM_ADDR_BITS) /* wr-enable */ 123 124 #define E82545_NVM_EEPROM_SIZE 64 /* 64 * 16-bit values == 128K */ 125 126 #define E1000_ICR_SRPD 0x00010000 127 128 /* This is an arbitrary number. There is no hard limit on the chip. */ 129 #define I82545_MAX_TXSEGS 64 130 131 /* Legacy receive descriptor */ 132 struct e1000_rx_desc { 133 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 134 uint16_t length; /* Length of data DMAed into data buffer */ 135 uint16_t csum; /* Packet checksum */ 136 uint8_t status; /* Descriptor status */ 137 uint8_t errors; /* Descriptor Errors */ 138 uint16_t special; 139 }; 140 141 /* Transmit descriptor types */ 142 #define E1000_TXD_MASK (E1000_TXD_CMD_DEXT | 0x00F00000) 143 #define E1000_TXD_TYP_L (0) 144 #define E1000_TXD_TYP_C (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_C) 145 #define E1000_TXD_TYP_D (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D) 146 147 /* Legacy transmit descriptor */ 148 struct e1000_tx_desc { 149 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 150 union { 151 uint32_t data; 152 struct { 153 uint16_t length; /* Data buffer length */ 154 uint8_t cso; /* Checksum offset */ 155 uint8_t cmd; /* Descriptor control */ 156 } flags; 157 } lower; 158 union { 159 uint32_t data; 160 struct { 161 uint8_t status; /* Descriptor status */ 162 uint8_t css; /* Checksum start */ 163 uint16_t special; 164 } fields; 165 } upper; 166 }; 167 168 /* Context descriptor */ 169 struct e1000_context_desc { 170 union { 171 uint32_t ip_config; 172 struct { 173 uint8_t ipcss; /* IP checksum start */ 174 uint8_t ipcso; /* IP checksum offset */ 175 uint16_t ipcse; /* IP checksum end */ 176 } ip_fields; 177 } lower_setup; 178 union { 179 uint32_t tcp_config; 180 struct { 181 uint8_t tucss; /* TCP checksum start */ 182 uint8_t tucso; /* TCP checksum offset */ 183 uint16_t tucse; /* TCP checksum end */ 184 } tcp_fields; 185 } upper_setup; 186 uint32_t cmd_and_length; 187 union { 188 uint32_t data; 189 struct { 190 uint8_t status; /* Descriptor status */ 191 uint8_t hdr_len; /* Header length */ 192 uint16_t mss; /* Maximum segment size */ 193 } fields; 194 } tcp_seg_setup; 195 }; 196 197 /* Data descriptor */ 198 struct e1000_data_desc { 199 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 200 union { 201 uint32_t data; 202 struct { 203 uint16_t length; /* Data buffer length */ 204 uint8_t typ_len_ext; 205 uint8_t cmd; 206 } flags; 207 } lower; 208 union { 209 uint32_t data; 210 struct { 211 uint8_t status; /* Descriptor status */ 212 uint8_t popts; /* Packet Options */ 213 uint16_t special; 214 } fields; 215 } upper; 216 }; 217 218 union e1000_tx_udesc { 219 struct e1000_tx_desc td; 220 struct e1000_context_desc cd; 221 struct e1000_data_desc dd; 222 }; 223 224 /* Tx checksum info for a packet. */ 225 struct ck_info { 226 int ck_valid; /* ck_info is valid */ 227 uint8_t ck_start; /* start byte of cksum calcuation */ 228 uint8_t ck_off; /* offset of cksum insertion */ 229 uint16_t ck_len; /* length of cksum calc: 0 is to packet-end */ 230 }; 231 232 /* 233 * Debug printf 234 */ 235 static int e82545_debug = 0; 236 #define WPRINTF(msg,params...) PRINTLN("e82545: " msg, params) 237 #define DPRINTF(msg,params...) if (e82545_debug) WPRINTF(msg, params) 238 239 #define MIN(a,b) (((a)<(b))?(a):(b)) 240 #define MAX(a,b) (((a)>(b))?(a):(b)) 241 242 /* s/w representation of the RAL/RAH regs */ 243 struct eth_uni { 244 int eu_valid; 245 int eu_addrsel; 246 struct ether_addr eu_eth; 247 }; 248 249 250 struct e82545_softc { 251 struct pci_devinst *esc_pi; 252 struct vmctx *esc_ctx; 253 struct mevent *esc_mevp; 254 struct mevent *esc_mevpitr; 255 pthread_mutex_t esc_mtx; 256 struct ether_addr esc_mac; 257 int esc_tapfd; 258 259 /* General */ 260 uint32_t esc_CTRL; /* x0000 device ctl */ 261 uint32_t esc_FCAL; /* x0028 flow ctl addr lo */ 262 uint32_t esc_FCAH; /* x002C flow ctl addr hi */ 263 uint32_t esc_FCT; /* x0030 flow ctl type */ 264 uint32_t esc_VET; /* x0038 VLAN eth type */ 265 uint32_t esc_FCTTV; /* x0170 flow ctl tx timer */ 266 uint32_t esc_LEDCTL; /* x0E00 LED control */ 267 uint32_t esc_PBA; /* x1000 pkt buffer allocation */ 268 269 /* Interrupt control */ 270 int esc_irq_asserted; 271 uint32_t esc_ICR; /* x00C0 cause read/clear */ 272 uint32_t esc_ITR; /* x00C4 intr throttling */ 273 uint32_t esc_ICS; /* x00C8 cause set */ 274 uint32_t esc_IMS; /* x00D0 mask set/read */ 275 uint32_t esc_IMC; /* x00D8 mask clear */ 276 277 /* Transmit */ 278 union e1000_tx_udesc *esc_txdesc; 279 struct e1000_context_desc esc_txctx; 280 pthread_t esc_tx_tid; 281 pthread_cond_t esc_tx_cond; 282 int esc_tx_enabled; 283 int esc_tx_active; 284 uint32_t esc_TXCW; /* x0178 transmit config */ 285 uint32_t esc_TCTL; /* x0400 transmit ctl */ 286 uint32_t esc_TIPG; /* x0410 inter-packet gap */ 287 uint16_t esc_AIT; /* x0458 Adaptive Interframe Throttle */ 288 uint64_t esc_tdba; /* verified 64-bit desc table addr */ 289 uint32_t esc_TDBAL; /* x3800 desc table addr, low bits */ 290 uint32_t esc_TDBAH; /* x3804 desc table addr, hi 32-bits */ 291 uint32_t esc_TDLEN; /* x3808 # descriptors in bytes */ 292 uint16_t esc_TDH; /* x3810 desc table head idx */ 293 uint16_t esc_TDHr; /* internal read version of TDH */ 294 uint16_t esc_TDT; /* x3818 desc table tail idx */ 295 uint32_t esc_TIDV; /* x3820 intr delay */ 296 uint32_t esc_TXDCTL; /* x3828 desc control */ 297 uint32_t esc_TADV; /* x382C intr absolute delay */ 298 299 /* L2 frame acceptance */ 300 struct eth_uni esc_uni[16]; /* 16 x unicast MAC addresses */ 301 uint32_t esc_fmcast[128]; /* Multicast filter bit-match */ 302 uint32_t esc_fvlan[128]; /* VLAN 4096-bit filter */ 303 304 /* Receive */ 305 struct e1000_rx_desc *esc_rxdesc; 306 pthread_cond_t esc_rx_cond; 307 int esc_rx_enabled; 308 int esc_rx_active; 309 int esc_rx_loopback; 310 uint32_t esc_RCTL; /* x0100 receive ctl */ 311 uint32_t esc_FCRTL; /* x2160 flow cntl thresh, low */ 312 uint32_t esc_FCRTH; /* x2168 flow cntl thresh, hi */ 313 uint64_t esc_rdba; /* verified 64-bit desc table addr */ 314 uint32_t esc_RDBAL; /* x2800 desc table addr, low bits */ 315 uint32_t esc_RDBAH; /* x2804 desc table addr, hi 32-bits*/ 316 uint32_t esc_RDLEN; /* x2808 #descriptors */ 317 uint16_t esc_RDH; /* x2810 desc table head idx */ 318 uint16_t esc_RDT; /* x2818 desc table tail idx */ 319 uint32_t esc_RDTR; /* x2820 intr delay */ 320 uint32_t esc_RXDCTL; /* x2828 desc control */ 321 uint32_t esc_RADV; /* x282C intr absolute delay */ 322 uint32_t esc_RSRPD; /* x2C00 recv small packet detect */ 323 uint32_t esc_RXCSUM; /* x5000 receive cksum ctl */ 324 325 /* IO Port register access */ 326 uint32_t io_addr; 327 328 /* Shadow copy of MDIC */ 329 uint32_t mdi_control; 330 /* Shadow copy of EECD */ 331 uint32_t eeprom_control; 332 /* Latest NVM in/out */ 333 uint16_t nvm_data; 334 uint16_t nvm_opaddr; 335 /* stats */ 336 uint32_t missed_pkt_count; /* dropped for no room in rx queue */ 337 uint32_t pkt_rx_by_size[6]; 338 uint32_t pkt_tx_by_size[6]; 339 uint32_t good_pkt_rx_count; 340 uint32_t bcast_pkt_rx_count; 341 uint32_t mcast_pkt_rx_count; 342 uint32_t good_pkt_tx_count; 343 uint32_t bcast_pkt_tx_count; 344 uint32_t mcast_pkt_tx_count; 345 uint32_t oversize_rx_count; 346 uint32_t tso_tx_count; 347 uint64_t good_octets_rx; 348 uint64_t good_octets_tx; 349 uint64_t missed_octets; /* counts missed and oversized */ 350 351 uint8_t nvm_bits:6; /* number of bits remaining in/out */ 352 uint8_t nvm_mode:2; 353 #define E82545_NVM_MODE_OPADDR 0x0 354 #define E82545_NVM_MODE_DATAIN 0x1 355 #define E82545_NVM_MODE_DATAOUT 0x2 356 /* EEPROM data */ 357 uint16_t eeprom_data[E82545_NVM_EEPROM_SIZE]; 358 }; 359 360 static void e82545_reset(struct e82545_softc *sc, int dev); 361 static void e82545_rx_enable(struct e82545_softc *sc); 362 static void e82545_rx_disable(struct e82545_softc *sc); 363 #ifdef __FreeBSD__ 364 static void e82545_rx_callback(int fd, enum ev_type type, void *param); 365 #endif 366 static void e82545_tx_start(struct e82545_softc *sc); 367 static void e82545_tx_enable(struct e82545_softc *sc); 368 static void e82545_tx_disable(struct e82545_softc *sc); 369 370 static inline int 371 e82545_size_stat_index(uint32_t size) 372 { 373 if (size <= 64) { 374 return 0; 375 } else if (size >= 1024) { 376 return 5; 377 } else { 378 /* should be 1-4 */ 379 return (ffs(size) - 6); 380 } 381 } 382 383 static void 384 e82545_init_eeprom(struct e82545_softc *sc) 385 { 386 uint16_t checksum, i; 387 388 /* mac addr */ 389 sc->eeprom_data[NVM_MAC_ADDR] = ((uint16_t)sc->esc_mac.octet[0]) | 390 (((uint16_t)sc->esc_mac.octet[1]) << 8); 391 sc->eeprom_data[NVM_MAC_ADDR+1] = ((uint16_t)sc->esc_mac.octet[2]) | 392 (((uint16_t)sc->esc_mac.octet[3]) << 8); 393 sc->eeprom_data[NVM_MAC_ADDR+2] = ((uint16_t)sc->esc_mac.octet[4]) | 394 (((uint16_t)sc->esc_mac.octet[5]) << 8); 395 396 /* pci ids */ 397 sc->eeprom_data[NVM_SUB_DEV_ID] = E82545_SUBDEV_ID; 398 sc->eeprom_data[NVM_SUB_VEN_ID] = E82545_VENDOR_ID_INTEL; 399 sc->eeprom_data[NVM_DEV_ID] = E82545_DEV_ID_82545EM_COPPER; 400 sc->eeprom_data[NVM_VEN_ID] = E82545_VENDOR_ID_INTEL; 401 402 /* fill in the checksum */ 403 checksum = 0; 404 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 405 checksum += sc->eeprom_data[i]; 406 } 407 checksum = NVM_SUM - checksum; 408 sc->eeprom_data[NVM_CHECKSUM_REG] = checksum; 409 DPRINTF("eeprom checksum: 0x%x", checksum); 410 } 411 412 static void 413 e82545_write_mdi(struct e82545_softc *sc, uint8_t reg_addr, 414 uint8_t phy_addr, uint32_t data) 415 { 416 DPRINTF("Write mdi reg:0x%x phy:0x%x data: 0x%x", reg_addr, phy_addr, data); 417 } 418 419 static uint32_t 420 e82545_read_mdi(struct e82545_softc *sc, uint8_t reg_addr, 421 uint8_t phy_addr) 422 { 423 //DPRINTF("Read mdi reg:0x%x phy:0x%x", reg_addr, phy_addr); 424 switch (reg_addr) { 425 case PHY_STATUS: 426 return (MII_SR_LINK_STATUS | MII_SR_AUTONEG_CAPS | 427 MII_SR_AUTONEG_COMPLETE); 428 case PHY_AUTONEG_ADV: 429 return NWAY_AR_SELECTOR_FIELD; 430 case PHY_LP_ABILITY: 431 return 0; 432 case PHY_1000T_STATUS: 433 return (SR_1000T_LP_FD_CAPS | SR_1000T_REMOTE_RX_STATUS | 434 SR_1000T_LOCAL_RX_STATUS); 435 case PHY_ID1: 436 return (M88E1011_I_PHY_ID >> 16) & 0xFFFF; 437 case PHY_ID2: 438 return (M88E1011_I_PHY_ID | E82545_REVISION_4) & 0xFFFF; 439 default: 440 DPRINTF("Unknown mdi read reg:0x%x phy:0x%x", reg_addr, phy_addr); 441 return 0; 442 } 443 /* not reached */ 444 } 445 446 static void 447 e82545_eecd_strobe(struct e82545_softc *sc) 448 { 449 /* Microwire state machine */ 450 /* 451 DPRINTF("eeprom state machine srtobe " 452 "0x%x 0x%x 0x%x 0x%x", 453 sc->nvm_mode, sc->nvm_bits, 454 sc->nvm_opaddr, sc->nvm_data);*/ 455 456 if (sc->nvm_bits == 0) { 457 DPRINTF("eeprom state machine not expecting data! " 458 "0x%x 0x%x 0x%x 0x%x", 459 sc->nvm_mode, sc->nvm_bits, 460 sc->nvm_opaddr, sc->nvm_data); 461 return; 462 } 463 sc->nvm_bits--; 464 if (sc->nvm_mode == E82545_NVM_MODE_DATAOUT) { 465 /* shifting out */ 466 if (sc->nvm_data & 0x8000) { 467 sc->eeprom_control |= E1000_EECD_DO; 468 } else { 469 sc->eeprom_control &= ~E1000_EECD_DO; 470 } 471 sc->nvm_data <<= 1; 472 if (sc->nvm_bits == 0) { 473 /* read done, back to opcode mode. */ 474 sc->nvm_opaddr = 0; 475 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 476 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 477 } 478 } else if (sc->nvm_mode == E82545_NVM_MODE_DATAIN) { 479 /* shifting in */ 480 sc->nvm_data <<= 1; 481 if (sc->eeprom_control & E1000_EECD_DI) { 482 sc->nvm_data |= 1; 483 } 484 if (sc->nvm_bits == 0) { 485 /* eeprom write */ 486 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 487 uint16_t addr = sc->nvm_opaddr & E82545_NVM_ADDR_MASK; 488 if (op != E82545_NVM_OPCODE_WRITE) { 489 DPRINTF("Illegal eeprom write op 0x%x", 490 sc->nvm_opaddr); 491 } else if (addr >= E82545_NVM_EEPROM_SIZE) { 492 DPRINTF("Illegal eeprom write addr 0x%x", 493 sc->nvm_opaddr); 494 } else { 495 DPRINTF("eeprom write eeprom[0x%x] = 0x%x", 496 addr, sc->nvm_data); 497 sc->eeprom_data[addr] = sc->nvm_data; 498 } 499 /* back to opcode mode */ 500 sc->nvm_opaddr = 0; 501 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 502 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 503 } 504 } else if (sc->nvm_mode == E82545_NVM_MODE_OPADDR) { 505 sc->nvm_opaddr <<= 1; 506 if (sc->eeprom_control & E1000_EECD_DI) { 507 sc->nvm_opaddr |= 1; 508 } 509 if (sc->nvm_bits == 0) { 510 uint16_t op = sc->nvm_opaddr & E82545_NVM_OPCODE_MASK; 511 switch (op) { 512 case E82545_NVM_OPCODE_EWEN: 513 DPRINTF("eeprom write enable: 0x%x", 514 sc->nvm_opaddr); 515 /* back to opcode mode */ 516 sc->nvm_opaddr = 0; 517 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 518 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 519 break; 520 case E82545_NVM_OPCODE_READ: 521 { 522 uint16_t addr = sc->nvm_opaddr & 523 E82545_NVM_ADDR_MASK; 524 sc->nvm_mode = E82545_NVM_MODE_DATAOUT; 525 sc->nvm_bits = E82545_NVM_DATA_BITS; 526 if (addr < E82545_NVM_EEPROM_SIZE) { 527 sc->nvm_data = sc->eeprom_data[addr]; 528 DPRINTF("eeprom read: eeprom[0x%x] = 0x%x", 529 addr, sc->nvm_data); 530 } else { 531 DPRINTF("eeprom illegal read: 0x%x", 532 sc->nvm_opaddr); 533 sc->nvm_data = 0; 534 } 535 break; 536 } 537 case E82545_NVM_OPCODE_WRITE: 538 sc->nvm_mode = E82545_NVM_MODE_DATAIN; 539 sc->nvm_bits = E82545_NVM_DATA_BITS; 540 sc->nvm_data = 0; 541 break; 542 default: 543 DPRINTF("eeprom unknown op: 0x%x", 544 sc->nvm_opaddr); 545 /* back to opcode mode */ 546 sc->nvm_opaddr = 0; 547 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 548 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 549 } 550 } 551 } else { 552 DPRINTF("eeprom state machine wrong state! " 553 "0x%x 0x%x 0x%x 0x%x", 554 sc->nvm_mode, sc->nvm_bits, 555 sc->nvm_opaddr, sc->nvm_data); 556 } 557 } 558 559 #ifdef __FreeBSD__ 560 static void 561 e82545_itr_callback(int fd, enum ev_type type, void *param) 562 { 563 uint32_t new; 564 struct e82545_softc *sc = param; 565 566 pthread_mutex_lock(&sc->esc_mtx); 567 new = sc->esc_ICR & sc->esc_IMS; 568 if (new && !sc->esc_irq_asserted) { 569 DPRINTF("itr callback: lintr assert %x", new); 570 sc->esc_irq_asserted = 1; 571 pci_lintr_assert(sc->esc_pi); 572 } else { 573 mevent_delete(sc->esc_mevpitr); 574 sc->esc_mevpitr = NULL; 575 } 576 pthread_mutex_unlock(&sc->esc_mtx); 577 } 578 #endif 579 580 static void 581 e82545_icr_assert(struct e82545_softc *sc, uint32_t bits) 582 { 583 uint32_t new; 584 585 DPRINTF("icr assert: 0x%x", bits); 586 587 /* 588 * An interrupt is only generated if bits are set that 589 * aren't already in the ICR, these bits are unmasked, 590 * and there isn't an interrupt already pending. 591 */ 592 new = bits & ~sc->esc_ICR & sc->esc_IMS; 593 sc->esc_ICR |= bits; 594 595 if (new == 0) { 596 DPRINTF("icr assert: masked %x, ims %x", new, sc->esc_IMS); 597 } else if (sc->esc_mevpitr != NULL) { 598 DPRINTF("icr assert: throttled %x, ims %x", new, sc->esc_IMS); 599 } else if (!sc->esc_irq_asserted) { 600 DPRINTF("icr assert: lintr assert %x", new); 601 sc->esc_irq_asserted = 1; 602 pci_lintr_assert(sc->esc_pi); 603 if (sc->esc_ITR != 0) { 604 #ifdef __FreeBSD__ 605 sc->esc_mevpitr = mevent_add( 606 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 607 EVF_TIMER, e82545_itr_callback, sc); 608 #endif 609 } 610 } 611 } 612 613 static void 614 e82545_ims_change(struct e82545_softc *sc, uint32_t bits) 615 { 616 uint32_t new; 617 618 /* 619 * Changing the mask may allow previously asserted 620 * but masked interrupt requests to generate an interrupt. 621 */ 622 new = bits & sc->esc_ICR & ~sc->esc_IMS; 623 sc->esc_IMS |= bits; 624 625 if (new == 0) { 626 DPRINTF("ims change: masked %x, ims %x", new, sc->esc_IMS); 627 } else if (sc->esc_mevpitr != NULL) { 628 DPRINTF("ims change: throttled %x, ims %x", new, sc->esc_IMS); 629 } else if (!sc->esc_irq_asserted) { 630 DPRINTF("ims change: lintr assert %x", new); 631 sc->esc_irq_asserted = 1; 632 pci_lintr_assert(sc->esc_pi); 633 if (sc->esc_ITR != 0) { 634 #ifdef __FreeBSD__ 635 sc->esc_mevpitr = mevent_add( 636 (sc->esc_ITR + 3905) / 3906, /* 256ns -> 1ms */ 637 EVF_TIMER, e82545_itr_callback, sc); 638 #endif 639 } 640 } 641 } 642 643 static void 644 e82545_icr_deassert(struct e82545_softc *sc, uint32_t bits) 645 { 646 647 DPRINTF("icr deassert: 0x%x", bits); 648 sc->esc_ICR &= ~bits; 649 650 /* 651 * If there are no longer any interrupt sources and there 652 * was an asserted interrupt, clear it 653 */ 654 if (sc->esc_irq_asserted && !(sc->esc_ICR & sc->esc_IMS)) { 655 DPRINTF("icr deassert: lintr deassert %x", bits); 656 pci_lintr_deassert(sc->esc_pi); 657 sc->esc_irq_asserted = 0; 658 } 659 } 660 661 static void 662 e82545_intr_write(struct e82545_softc *sc, uint32_t offset, uint32_t value) 663 { 664 665 DPRINTF("intr_write: off %x, val %x", offset, value); 666 667 switch (offset) { 668 case E1000_ICR: 669 e82545_icr_deassert(sc, value); 670 break; 671 case E1000_ITR: 672 sc->esc_ITR = value; 673 break; 674 case E1000_ICS: 675 sc->esc_ICS = value; /* not used: store for debug */ 676 e82545_icr_assert(sc, value); 677 break; 678 case E1000_IMS: 679 e82545_ims_change(sc, value); 680 break; 681 case E1000_IMC: 682 sc->esc_IMC = value; /* for debug */ 683 sc->esc_IMS &= ~value; 684 // XXX clear interrupts if all ICR bits now masked 685 // and interrupt was pending ? 686 break; 687 default: 688 break; 689 } 690 } 691 692 static uint32_t 693 e82545_intr_read(struct e82545_softc *sc, uint32_t offset) 694 { 695 uint32_t retval; 696 697 retval = 0; 698 699 DPRINTF("intr_read: off %x", offset); 700 701 switch (offset) { 702 case E1000_ICR: 703 retval = sc->esc_ICR; 704 sc->esc_ICR = 0; 705 e82545_icr_deassert(sc, ~0); 706 break; 707 case E1000_ITR: 708 retval = sc->esc_ITR; 709 break; 710 case E1000_ICS: 711 /* write-only register */ 712 break; 713 case E1000_IMS: 714 retval = sc->esc_IMS; 715 break; 716 case E1000_IMC: 717 /* write-only register */ 718 break; 719 default: 720 break; 721 } 722 723 return (retval); 724 } 725 726 static void 727 e82545_devctl(struct e82545_softc *sc, uint32_t val) 728 { 729 730 sc->esc_CTRL = val & ~E1000_CTRL_RST; 731 732 if (val & E1000_CTRL_RST) { 733 DPRINTF("e1k: s/w reset, ctl %x", val); 734 e82545_reset(sc, 1); 735 } 736 /* XXX check for phy reset ? */ 737 } 738 739 static void 740 e82545_rx_update_rdba(struct e82545_softc *sc) 741 { 742 743 /* XXX verify desc base/len within phys mem range */ 744 sc->esc_rdba = (uint64_t)sc->esc_RDBAH << 32 | 745 sc->esc_RDBAL; 746 747 /* Cache host mapping of guest descriptor array */ 748 sc->esc_rxdesc = paddr_guest2host(sc->esc_ctx, 749 sc->esc_rdba, sc->esc_RDLEN); 750 } 751 752 static void 753 e82545_rx_ctl(struct e82545_softc *sc, uint32_t val) 754 { 755 int on; 756 757 on = ((val & E1000_RCTL_EN) == E1000_RCTL_EN); 758 759 /* Save RCTL after stripping reserved bits 31:27,24,21,14,11:10,0 */ 760 sc->esc_RCTL = val & ~0xF9204c01; 761 762 DPRINTF("rx_ctl - %s RCTL %x, val %x", 763 on ? "on" : "off", sc->esc_RCTL, val); 764 765 /* state change requested */ 766 if (on != sc->esc_rx_enabled) { 767 if (on) { 768 /* Catch disallowed/unimplemented settings */ 769 //assert(!(val & E1000_RCTL_LBM_TCVR)); 770 771 if (sc->esc_RCTL & E1000_RCTL_LBM_TCVR) { 772 sc->esc_rx_loopback = 1; 773 } else { 774 sc->esc_rx_loopback = 0; 775 } 776 777 e82545_rx_update_rdba(sc); 778 e82545_rx_enable(sc); 779 } else { 780 e82545_rx_disable(sc); 781 sc->esc_rx_loopback = 0; 782 sc->esc_rdba = 0; 783 sc->esc_rxdesc = NULL; 784 } 785 } 786 } 787 788 static void 789 e82545_tx_update_tdba(struct e82545_softc *sc) 790 { 791 792 /* XXX verify desc base/len within phys mem range */ 793 sc->esc_tdba = (uint64_t)sc->esc_TDBAH << 32 | sc->esc_TDBAL; 794 795 /* Cache host mapping of guest descriptor array */ 796 sc->esc_txdesc = paddr_guest2host(sc->esc_ctx, sc->esc_tdba, 797 sc->esc_TDLEN); 798 } 799 800 static void 801 e82545_tx_ctl(struct e82545_softc *sc, uint32_t val) 802 { 803 int on; 804 805 on = ((val & E1000_TCTL_EN) == E1000_TCTL_EN); 806 807 /* ignore TCTL_EN settings that don't change state */ 808 if (on == sc->esc_tx_enabled) 809 return; 810 811 if (on) { 812 e82545_tx_update_tdba(sc); 813 e82545_tx_enable(sc); 814 } else { 815 e82545_tx_disable(sc); 816 sc->esc_tdba = 0; 817 sc->esc_txdesc = NULL; 818 } 819 820 /* Save TCTL value after stripping reserved bits 31:25,23,2,0 */ 821 sc->esc_TCTL = val & ~0xFE800005; 822 } 823 824 int 825 e82545_bufsz(uint32_t rctl) 826 { 827 828 switch (rctl & (E1000_RCTL_BSEX | E1000_RCTL_SZ_256)) { 829 case (E1000_RCTL_SZ_2048): return (2048); 830 case (E1000_RCTL_SZ_1024): return (1024); 831 case (E1000_RCTL_SZ_512): return (512); 832 case (E1000_RCTL_SZ_256): return (256); 833 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_16384): return (16384); 834 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_8192): return (8192); 835 case (E1000_RCTL_BSEX|E1000_RCTL_SZ_4096): return (4096); 836 } 837 return (256); /* Forbidden value. */ 838 } 839 840 #ifdef __FreeBSD__ 841 static uint8_t dummybuf[2048]; 842 843 /* XXX one packet at a time until this is debugged */ 844 static void 845 e82545_rx_callback(int fd, enum ev_type type, void *param) 846 { 847 struct e82545_softc *sc = param; 848 struct e1000_rx_desc *rxd; 849 struct iovec vec[64]; 850 int left, len, lim, maxpktsz, maxpktdesc, bufsz, i, n, size; 851 uint32_t cause = 0; 852 uint16_t *tp, tag, head; 853 854 pthread_mutex_lock(&sc->esc_mtx); 855 DPRINTF("rx_run: head %x, tail %x", sc->esc_RDH, sc->esc_RDT); 856 857 if (!sc->esc_rx_enabled || sc->esc_rx_loopback) { 858 DPRINTF("rx disabled (!%d || %d) -- packet(s) dropped", 859 sc->esc_rx_enabled, sc->esc_rx_loopback); 860 while (read(sc->esc_tapfd, dummybuf, sizeof(dummybuf)) > 0) { 861 } 862 goto done1; 863 } 864 bufsz = e82545_bufsz(sc->esc_RCTL); 865 maxpktsz = (sc->esc_RCTL & E1000_RCTL_LPE) ? 16384 : 1522; 866 maxpktdesc = (maxpktsz + bufsz - 1) / bufsz; 867 size = sc->esc_RDLEN / 16; 868 head = sc->esc_RDH; 869 left = (size + sc->esc_RDT - head) % size; 870 if (left < maxpktdesc) { 871 DPRINTF("rx overflow (%d < %d) -- packet(s) dropped", 872 left, maxpktdesc); 873 while (read(sc->esc_tapfd, dummybuf, sizeof(dummybuf)) > 0) { 874 } 875 goto done1; 876 } 877 878 sc->esc_rx_active = 1; 879 pthread_mutex_unlock(&sc->esc_mtx); 880 881 for (lim = size / 4; lim > 0 && left >= maxpktdesc; lim -= n) { 882 883 /* Grab rx descriptor pointed to by the head pointer */ 884 for (i = 0; i < maxpktdesc; i++) { 885 rxd = &sc->esc_rxdesc[(head + i) % size]; 886 vec[i].iov_base = paddr_guest2host(sc->esc_ctx, 887 rxd->buffer_addr, bufsz); 888 vec[i].iov_len = bufsz; 889 } 890 len = readv(sc->esc_tapfd, vec, maxpktdesc); 891 if (len <= 0) { 892 DPRINTF("tap: readv() returned %d\n", len); 893 goto done; 894 } 895 896 /* 897 * Adjust the packet length based on whether the CRC needs 898 * to be stripped or if the packet is less than the minimum 899 * eth packet size. 900 */ 901 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 902 len = ETHER_MIN_LEN - ETHER_CRC_LEN; 903 if (!(sc->esc_RCTL & E1000_RCTL_SECRC)) 904 len += ETHER_CRC_LEN; 905 n = (len + bufsz - 1) / bufsz; 906 907 DPRINTF("packet read %d bytes, %d segs, head %d", 908 len, n, head); 909 910 /* Apply VLAN filter. */ 911 tp = (uint16_t *)vec[0].iov_base + 6; 912 if ((sc->esc_RCTL & E1000_RCTL_VFE) && 913 (ntohs(tp[0]) == sc->esc_VET)) { 914 tag = ntohs(tp[1]) & 0x0fff; 915 if ((sc->esc_fvlan[tag >> 5] & 916 (1 << (tag & 0x1f))) != 0) { 917 DPRINTF("known VLAN %d", tag); 918 } else { 919 DPRINTF("unknown VLAN %d", tag); 920 n = 0; 921 continue; 922 } 923 } 924 925 /* Update all consumed descriptors. */ 926 for (i = 0; i < n - 1; i++) { 927 rxd = &sc->esc_rxdesc[(head + i) % size]; 928 rxd->length = bufsz; 929 rxd->csum = 0; 930 rxd->errors = 0; 931 rxd->special = 0; 932 rxd->status = E1000_RXD_STAT_DD; 933 } 934 rxd = &sc->esc_rxdesc[(head + i) % size]; 935 rxd->length = len % bufsz; 936 rxd->csum = 0; 937 rxd->errors = 0; 938 rxd->special = 0; 939 /* XXX signal no checksum for now */ 940 rxd->status = E1000_RXD_STAT_PIF | E1000_RXD_STAT_IXSM | 941 E1000_RXD_STAT_EOP | E1000_RXD_STAT_DD; 942 943 /* Schedule receive interrupts. */ 944 if (len <= sc->esc_RSRPD) { 945 cause |= E1000_ICR_SRPD | E1000_ICR_RXT0; 946 } else { 947 /* XXX: RDRT and RADV timers should be here. */ 948 cause |= E1000_ICR_RXT0; 949 } 950 951 head = (head + n) % size; 952 left -= n; 953 } 954 955 done: 956 pthread_mutex_lock(&sc->esc_mtx); 957 sc->esc_rx_active = 0; 958 if (sc->esc_rx_enabled == 0) 959 pthread_cond_signal(&sc->esc_rx_cond); 960 961 sc->esc_RDH = head; 962 /* Respect E1000_RCTL_RDMTS */ 963 left = (size + sc->esc_RDT - head) % size; 964 if (left < (size >> (((sc->esc_RCTL >> 8) & 3) + 1))) 965 cause |= E1000_ICR_RXDMT0; 966 /* Assert all accumulated interrupts. */ 967 if (cause != 0) 968 e82545_icr_assert(sc, cause); 969 done1: 970 DPRINTF("rx_run done: head %x, tail %x", sc->esc_RDH, sc->esc_RDT); 971 pthread_mutex_unlock(&sc->esc_mtx); 972 } 973 #endif 974 975 static uint16_t 976 e82545_carry(uint32_t sum) 977 { 978 979 sum = (sum & 0xFFFF) + (sum >> 16); 980 if (sum > 0xFFFF) 981 sum -= 0xFFFF; 982 return (sum); 983 } 984 985 static uint16_t 986 #ifdef __FreeBSD__ 987 e82545_buf_checksum(uint8_t *buf, int len) 988 #else 989 e82545_buf_checksum(caddr_t buf, int len) 990 #endif 991 { 992 int i; 993 uint32_t sum = 0; 994 995 /* Checksum all the pairs of bytes first... */ 996 for (i = 0; i < (len & ~1U); i += 2) 997 sum += *((u_int16_t *)(buf + i)); 998 999 /* 1000 * If there's a single byte left over, checksum it, too. 1001 * Network byte order is big-endian, so the remaining byte is 1002 * the high byte. 1003 */ 1004 if (i < len) 1005 sum += htons(buf[i] << 8); 1006 1007 return (e82545_carry(sum)); 1008 } 1009 1010 static uint16_t 1011 e82545_iov_checksum(struct iovec *iov, int iovcnt, int off, int len) 1012 { 1013 int now, odd; 1014 uint32_t sum = 0, s; 1015 1016 /* Skip completely unneeded vectors. */ 1017 while (iovcnt > 0 && iov->iov_len <= off && off > 0) { 1018 off -= iov->iov_len; 1019 iov++; 1020 iovcnt--; 1021 } 1022 1023 /* Calculate checksum of requested range. */ 1024 odd = 0; 1025 while (len > 0 && iovcnt > 0) { 1026 now = MIN(len, iov->iov_len - off); 1027 s = e82545_buf_checksum(iov->iov_base + off, now); 1028 sum += odd ? (s << 8) : s; 1029 odd ^= (now & 1); 1030 len -= now; 1031 off = 0; 1032 iov++; 1033 iovcnt--; 1034 } 1035 1036 return (e82545_carry(sum)); 1037 } 1038 1039 /* 1040 * Return the transmit descriptor type. 1041 */ 1042 int 1043 e82545_txdesc_type(uint32_t lower) 1044 { 1045 int type; 1046 1047 type = 0; 1048 1049 if (lower & E1000_TXD_CMD_DEXT) 1050 type = lower & E1000_TXD_MASK; 1051 1052 return (type); 1053 } 1054 1055 static void 1056 e82545_transmit_checksum(struct iovec *iov, int iovcnt, struct ck_info *ck) 1057 { 1058 uint16_t cksum; 1059 int cklen; 1060 1061 DPRINTF("tx cksum: iovcnt/s/off/len %d/%d/%d/%d", 1062 iovcnt, ck->ck_start, ck->ck_off, ck->ck_len); 1063 cklen = ck->ck_len ? ck->ck_len - ck->ck_start + 1 : INT_MAX; 1064 cksum = e82545_iov_checksum(iov, iovcnt, ck->ck_start, cklen); 1065 *(uint16_t *)((uint8_t *)iov[0].iov_base + ck->ck_off) = ~cksum; 1066 } 1067 1068 static void 1069 e82545_transmit_backend(struct e82545_softc *sc, struct iovec *iov, int iovcnt) 1070 { 1071 1072 if (sc->esc_tapfd == -1) 1073 return; 1074 1075 (void) writev(sc->esc_tapfd, iov, iovcnt); 1076 } 1077 1078 static void 1079 e82545_transmit_done(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1080 uint16_t dsize, int *tdwb) 1081 { 1082 union e1000_tx_udesc *dsc; 1083 1084 for ( ; head != tail; head = (head + 1) % dsize) { 1085 dsc = &sc->esc_txdesc[head]; 1086 if (dsc->td.lower.data & E1000_TXD_CMD_RS) { 1087 dsc->td.upper.data |= E1000_TXD_STAT_DD; 1088 *tdwb = 1; 1089 } 1090 } 1091 } 1092 1093 static int 1094 e82545_transmit(struct e82545_softc *sc, uint16_t head, uint16_t tail, 1095 uint16_t dsize, uint16_t *rhead, int *tdwb) 1096 { 1097 #ifdef __FreeBSD__ 1098 uint8_t *hdr, *hdrp; 1099 #else 1100 caddr_t hdr, hdrp; 1101 #endif 1102 struct iovec iovb[I82545_MAX_TXSEGS + 2]; 1103 struct iovec tiov[I82545_MAX_TXSEGS + 2]; 1104 struct e1000_context_desc *cd; 1105 struct ck_info ckinfo[2]; 1106 struct iovec *iov; 1107 union e1000_tx_udesc *dsc; 1108 int desc, dtype, len, ntype, iovcnt, tlen, hdrlen, vlen, tcp, tso; 1109 int mss, paylen, seg, tiovcnt, left, now, nleft, nnow, pv, pvoff; 1110 uint32_t tcpsum, tcpseq; 1111 uint16_t ipcs, tcpcs, ipid, ohead; 1112 1113 ckinfo[0].ck_valid = ckinfo[1].ck_valid = 0; 1114 iovcnt = 0; 1115 tlen = 0; 1116 ntype = 0; 1117 tso = 0; 1118 ohead = head; 1119 hdr = NULL; 1120 1121 /* iovb[0/1] may be used for writable copy of headers. */ 1122 iov = &iovb[2]; 1123 1124 for (desc = 0; ; desc++, head = (head + 1) % dsize) { 1125 if (head == tail) { 1126 *rhead = head; 1127 return (0); 1128 } 1129 dsc = &sc->esc_txdesc[head]; 1130 dtype = e82545_txdesc_type(dsc->td.lower.data); 1131 1132 if (desc == 0) { 1133 switch (dtype) { 1134 case E1000_TXD_TYP_C: 1135 DPRINTF("tx ctxt desc idx %d: %016jx " 1136 "%08x%08x", 1137 head, dsc->td.buffer_addr, 1138 dsc->td.upper.data, dsc->td.lower.data); 1139 /* Save context and return */ 1140 sc->esc_txctx = dsc->cd; 1141 goto done; 1142 case E1000_TXD_TYP_L: 1143 DPRINTF("tx legacy desc idx %d: %08x%08x", 1144 head, dsc->td.upper.data, dsc->td.lower.data); 1145 /* 1146 * legacy cksum start valid in first descriptor 1147 */ 1148 ntype = dtype; 1149 ckinfo[0].ck_start = dsc->td.upper.fields.css; 1150 break; 1151 case E1000_TXD_TYP_D: 1152 DPRINTF("tx data desc idx %d: %08x%08x", 1153 head, dsc->td.upper.data, dsc->td.lower.data); 1154 ntype = dtype; 1155 break; 1156 default: 1157 break; 1158 } 1159 } else { 1160 /* Descriptor type must be consistent */ 1161 assert(dtype == ntype); 1162 DPRINTF("tx next desc idx %d: %08x%08x", 1163 head, dsc->td.upper.data, dsc->td.lower.data); 1164 } 1165 1166 len = (dtype == E1000_TXD_TYP_L) ? dsc->td.lower.flags.length : 1167 dsc->dd.lower.data & 0xFFFFF; 1168 1169 if (len > 0) { 1170 /* Strip checksum supplied by guest. */ 1171 if ((dsc->td.lower.data & E1000_TXD_CMD_EOP) != 0 && 1172 (dsc->td.lower.data & E1000_TXD_CMD_IFCS) == 0) 1173 len -= 2; 1174 tlen += len; 1175 if (iovcnt < I82545_MAX_TXSEGS) { 1176 iov[iovcnt].iov_base = paddr_guest2host( 1177 sc->esc_ctx, dsc->td.buffer_addr, len); 1178 iov[iovcnt].iov_len = len; 1179 } 1180 iovcnt++; 1181 } 1182 1183 /* 1184 * Pull out info that is valid in the final descriptor 1185 * and exit descriptor loop. 1186 */ 1187 if (dsc->td.lower.data & E1000_TXD_CMD_EOP) { 1188 if (dtype == E1000_TXD_TYP_L) { 1189 if (dsc->td.lower.data & E1000_TXD_CMD_IC) { 1190 ckinfo[0].ck_valid = 1; 1191 ckinfo[0].ck_off = 1192 dsc->td.lower.flags.cso; 1193 ckinfo[0].ck_len = 0; 1194 } 1195 } else { 1196 cd = &sc->esc_txctx; 1197 if (dsc->dd.lower.data & E1000_TXD_CMD_TSE) 1198 tso = 1; 1199 if (dsc->dd.upper.fields.popts & 1200 E1000_TXD_POPTS_IXSM) 1201 ckinfo[0].ck_valid = 1; 1202 if (dsc->dd.upper.fields.popts & 1203 E1000_TXD_POPTS_IXSM || tso) { 1204 ckinfo[0].ck_start = 1205 cd->lower_setup.ip_fields.ipcss; 1206 ckinfo[0].ck_off = 1207 cd->lower_setup.ip_fields.ipcso; 1208 ckinfo[0].ck_len = 1209 cd->lower_setup.ip_fields.ipcse; 1210 } 1211 if (dsc->dd.upper.fields.popts & 1212 E1000_TXD_POPTS_TXSM) 1213 ckinfo[1].ck_valid = 1; 1214 if (dsc->dd.upper.fields.popts & 1215 E1000_TXD_POPTS_TXSM || tso) { 1216 ckinfo[1].ck_start = 1217 cd->upper_setup.tcp_fields.tucss; 1218 ckinfo[1].ck_off = 1219 cd->upper_setup.tcp_fields.tucso; 1220 ckinfo[1].ck_len = 1221 cd->upper_setup.tcp_fields.tucse; 1222 } 1223 } 1224 break; 1225 } 1226 } 1227 1228 if (iovcnt > I82545_MAX_TXSEGS) { 1229 WPRINTF("tx too many descriptors (%d > %d) -- dropped", 1230 iovcnt, I82545_MAX_TXSEGS); 1231 goto done; 1232 } 1233 1234 hdrlen = vlen = 0; 1235 /* Estimate writable space for VLAN header insertion. */ 1236 if ((sc->esc_CTRL & E1000_CTRL_VME) && 1237 (dsc->td.lower.data & E1000_TXD_CMD_VLE)) { 1238 hdrlen = ETHER_ADDR_LEN*2; 1239 vlen = ETHER_VLAN_ENCAP_LEN; 1240 } 1241 if (!tso) { 1242 /* Estimate required writable space for checksums. */ 1243 if (ckinfo[0].ck_valid) 1244 hdrlen = MAX(hdrlen, ckinfo[0].ck_off + 2); 1245 if (ckinfo[1].ck_valid) 1246 hdrlen = MAX(hdrlen, ckinfo[1].ck_off + 2); 1247 /* Round up writable space to the first vector. */ 1248 if (hdrlen != 0 && iov[0].iov_len > hdrlen && 1249 iov[0].iov_len < hdrlen + 100) 1250 hdrlen = iov[0].iov_len; 1251 } else { 1252 /* In case of TSO header length provided by software. */ 1253 hdrlen = sc->esc_txctx.tcp_seg_setup.fields.hdr_len; 1254 } 1255 1256 /* Allocate, fill and prepend writable header vector. */ 1257 if (hdrlen != 0) { 1258 hdr = __builtin_alloca(hdrlen + vlen); 1259 hdr += vlen; 1260 for (left = hdrlen, hdrp = hdr; left > 0; 1261 left -= now, hdrp += now) { 1262 now = MIN(left, iov->iov_len); 1263 memcpy(hdrp, iov->iov_base, now); 1264 iov->iov_base += now; 1265 iov->iov_len -= now; 1266 if (iov->iov_len == 0) { 1267 iov++; 1268 iovcnt--; 1269 } 1270 } 1271 iov--; 1272 iovcnt++; 1273 iov->iov_base = hdr; 1274 iov->iov_len = hdrlen; 1275 } 1276 1277 /* Insert VLAN tag. */ 1278 if (vlen != 0) { 1279 hdr -= ETHER_VLAN_ENCAP_LEN; 1280 memmove(hdr, hdr + ETHER_VLAN_ENCAP_LEN, ETHER_ADDR_LEN*2); 1281 hdrlen += ETHER_VLAN_ENCAP_LEN; 1282 hdr[ETHER_ADDR_LEN*2 + 0] = sc->esc_VET >> 8; 1283 hdr[ETHER_ADDR_LEN*2 + 1] = sc->esc_VET & 0xff; 1284 hdr[ETHER_ADDR_LEN*2 + 2] = dsc->td.upper.fields.special >> 8; 1285 hdr[ETHER_ADDR_LEN*2 + 3] = dsc->td.upper.fields.special & 0xff; 1286 iov->iov_base = hdr; 1287 iov->iov_len += ETHER_VLAN_ENCAP_LEN; 1288 /* Correct checksum offsets after VLAN tag insertion. */ 1289 ckinfo[0].ck_start += ETHER_VLAN_ENCAP_LEN; 1290 ckinfo[0].ck_off += ETHER_VLAN_ENCAP_LEN; 1291 if (ckinfo[0].ck_len != 0) 1292 ckinfo[0].ck_len += ETHER_VLAN_ENCAP_LEN; 1293 ckinfo[1].ck_start += ETHER_VLAN_ENCAP_LEN; 1294 ckinfo[1].ck_off += ETHER_VLAN_ENCAP_LEN; 1295 if (ckinfo[1].ck_len != 0) 1296 ckinfo[1].ck_len += ETHER_VLAN_ENCAP_LEN; 1297 } 1298 1299 /* Simple non-TSO case. */ 1300 if (!tso) { 1301 /* Calculate checksums and transmit. */ 1302 if (ckinfo[0].ck_valid) 1303 e82545_transmit_checksum(iov, iovcnt, &ckinfo[0]); 1304 if (ckinfo[1].ck_valid) 1305 e82545_transmit_checksum(iov, iovcnt, &ckinfo[1]); 1306 e82545_transmit_backend(sc, iov, iovcnt); 1307 goto done; 1308 } 1309 1310 /* Doing TSO. */ 1311 tcp = (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_TCP) != 0; 1312 mss = sc->esc_txctx.tcp_seg_setup.fields.mss; 1313 paylen = (sc->esc_txctx.cmd_and_length & 0x000fffff); 1314 DPRINTF("tx %s segmentation offload %d+%d/%d bytes %d iovs\r\n", 1315 tcp ? "TCP" : "UDP", hdrlen, paylen, mss, iovcnt); 1316 ipid = ntohs(*(uint16_t *)&hdr[ckinfo[0].ck_start + 4]); 1317 tcpseq = ntohl(*(uint32_t *)&hdr[ckinfo[1].ck_start + 4]); 1318 ipcs = *(uint16_t *)&hdr[ckinfo[0].ck_off]; 1319 tcpcs = 0; 1320 if (ckinfo[1].ck_valid) /* Save partial pseudo-header checksum. */ 1321 tcpcs = *(uint16_t *)&hdr[ckinfo[1].ck_off]; 1322 pv = 1; 1323 pvoff = 0; 1324 for (seg = 0, left = paylen; left > 0; seg++, left -= now) { 1325 now = MIN(left, mss); 1326 1327 /* Construct IOVs for the segment. */ 1328 /* Include whole original header. */ 1329 tiov[0].iov_base = hdr; 1330 tiov[0].iov_len = hdrlen; 1331 tiovcnt = 1; 1332 /* Include respective part of payload IOV. */ 1333 for (nleft = now; pv < iovcnt && nleft > 0; nleft -= nnow) { 1334 nnow = MIN(nleft, iov[pv].iov_len - pvoff); 1335 tiov[tiovcnt].iov_base = iov[pv].iov_base + pvoff; 1336 tiov[tiovcnt++].iov_len = nnow; 1337 if (pvoff + nnow == iov[pv].iov_len) { 1338 pv++; 1339 pvoff = 0; 1340 } else 1341 pvoff += nnow; 1342 } 1343 DPRINTF("tx segment %d %d+%d bytes %d iovs\r\n", 1344 seg, hdrlen, now, tiovcnt); 1345 1346 /* Update IP header. */ 1347 if (sc->esc_txctx.cmd_and_length & E1000_TXD_CMD_IP) { 1348 /* IPv4 -- set length and ID */ 1349 *(uint16_t *)&hdr[ckinfo[0].ck_start + 2] = 1350 htons(hdrlen - ckinfo[0].ck_start + now); 1351 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1352 htons(ipid + seg); 1353 } else { 1354 /* IPv6 -- set length */ 1355 *(uint16_t *)&hdr[ckinfo[0].ck_start + 4] = 1356 htons(hdrlen - ckinfo[0].ck_start - 40 + 1357 now); 1358 } 1359 1360 /* Update pseudo-header checksum. */ 1361 tcpsum = tcpcs; 1362 tcpsum += htons(hdrlen - ckinfo[1].ck_start + now); 1363 1364 /* Update TCP/UDP headers. */ 1365 if (tcp) { 1366 /* Update sequence number and FIN/PUSH flags. */ 1367 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1368 htonl(tcpseq + paylen - left); 1369 if (now < left) { 1370 hdr[ckinfo[1].ck_start + 13] &= 1371 ~(TH_FIN | TH_PUSH); 1372 } 1373 } else { 1374 /* Update payload length. */ 1375 *(uint32_t *)&hdr[ckinfo[1].ck_start + 4] = 1376 hdrlen - ckinfo[1].ck_start + now; 1377 } 1378 1379 /* Calculate checksums and transmit. */ 1380 if (ckinfo[0].ck_valid) { 1381 *(uint16_t *)&hdr[ckinfo[0].ck_off] = ipcs; 1382 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[0]); 1383 } 1384 if (ckinfo[1].ck_valid) { 1385 *(uint16_t *)&hdr[ckinfo[1].ck_off] = 1386 e82545_carry(tcpsum); 1387 e82545_transmit_checksum(tiov, tiovcnt, &ckinfo[1]); 1388 } 1389 e82545_transmit_backend(sc, tiov, tiovcnt); 1390 } 1391 1392 done: 1393 head = (head + 1) % dsize; 1394 e82545_transmit_done(sc, ohead, head, dsize, tdwb); 1395 1396 *rhead = head; 1397 return (desc + 1); 1398 } 1399 1400 static void 1401 e82545_tx_run(struct e82545_softc *sc) 1402 { 1403 uint32_t cause; 1404 uint16_t head, rhead, tail, size; 1405 int lim, tdwb, sent; 1406 1407 head = sc->esc_TDH; 1408 tail = sc->esc_TDT; 1409 size = sc->esc_TDLEN / 16; 1410 DPRINTF("tx_run: head %x, rhead %x, tail %x", 1411 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1412 1413 pthread_mutex_unlock(&sc->esc_mtx); 1414 rhead = head; 1415 tdwb = 0; 1416 for (lim = size / 4; sc->esc_tx_enabled && lim > 0; lim -= sent) { 1417 sent = e82545_transmit(sc, head, tail, size, &rhead, &tdwb); 1418 if (sent == 0) 1419 break; 1420 head = rhead; 1421 } 1422 pthread_mutex_lock(&sc->esc_mtx); 1423 1424 sc->esc_TDH = head; 1425 sc->esc_TDHr = rhead; 1426 cause = 0; 1427 if (tdwb) 1428 cause |= E1000_ICR_TXDW; 1429 if (lim != size / 4 && sc->esc_TDH == sc->esc_TDT) 1430 cause |= E1000_ICR_TXQE; 1431 if (cause) 1432 e82545_icr_assert(sc, cause); 1433 1434 DPRINTF("tx_run done: head %x, rhead %x, tail %x", 1435 sc->esc_TDH, sc->esc_TDHr, sc->esc_TDT); 1436 } 1437 1438 static void * 1439 e82545_tx_thread(void *param) 1440 { 1441 struct e82545_softc *sc = param; 1442 1443 pthread_mutex_lock(&sc->esc_mtx); 1444 for (;;) { 1445 while (!sc->esc_tx_enabled || sc->esc_TDHr == sc->esc_TDT) { 1446 if (sc->esc_tx_enabled && sc->esc_TDHr != sc->esc_TDT) 1447 break; 1448 sc->esc_tx_active = 0; 1449 if (sc->esc_tx_enabled == 0) 1450 pthread_cond_signal(&sc->esc_tx_cond); 1451 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1452 } 1453 sc->esc_tx_active = 1; 1454 1455 /* Process some tx descriptors. Lock dropped inside. */ 1456 e82545_tx_run(sc); 1457 } 1458 #ifndef __FreeBSD__ 1459 return (NULL); 1460 #endif 1461 } 1462 1463 static void 1464 e82545_tx_start(struct e82545_softc *sc) 1465 { 1466 1467 if (sc->esc_tx_active == 0) 1468 pthread_cond_signal(&sc->esc_tx_cond); 1469 } 1470 1471 static void 1472 e82545_tx_enable(struct e82545_softc *sc) 1473 { 1474 1475 sc->esc_tx_enabled = 1; 1476 } 1477 1478 static void 1479 e82545_tx_disable(struct e82545_softc *sc) 1480 { 1481 1482 sc->esc_tx_enabled = 0; 1483 while (sc->esc_tx_active) 1484 pthread_cond_wait(&sc->esc_tx_cond, &sc->esc_mtx); 1485 } 1486 1487 static void 1488 e82545_rx_enable(struct e82545_softc *sc) 1489 { 1490 1491 sc->esc_rx_enabled = 1; 1492 } 1493 1494 static void 1495 e82545_rx_disable(struct e82545_softc *sc) 1496 { 1497 1498 sc->esc_rx_enabled = 0; 1499 while (sc->esc_rx_active) 1500 pthread_cond_wait(&sc->esc_rx_cond, &sc->esc_mtx); 1501 } 1502 1503 static void 1504 e82545_write_ra(struct e82545_softc *sc, int reg, uint32_t wval) 1505 { 1506 struct eth_uni *eu; 1507 int idx; 1508 1509 idx = reg >> 1; 1510 assert(idx < 15); 1511 1512 eu = &sc->esc_uni[idx]; 1513 1514 if (reg & 0x1) { 1515 /* RAH */ 1516 eu->eu_valid = ((wval & E1000_RAH_AV) == E1000_RAH_AV); 1517 eu->eu_addrsel = (wval >> 16) & 0x3; 1518 eu->eu_eth.octet[5] = wval >> 8; 1519 eu->eu_eth.octet[4] = wval; 1520 } else { 1521 /* RAL */ 1522 eu->eu_eth.octet[3] = wval >> 24; 1523 eu->eu_eth.octet[2] = wval >> 16; 1524 eu->eu_eth.octet[1] = wval >> 8; 1525 eu->eu_eth.octet[0] = wval; 1526 } 1527 } 1528 1529 static uint32_t 1530 e82545_read_ra(struct e82545_softc *sc, int reg) 1531 { 1532 struct eth_uni *eu; 1533 uint32_t retval; 1534 int idx; 1535 1536 idx = reg >> 1; 1537 assert(idx < 15); 1538 1539 eu = &sc->esc_uni[idx]; 1540 1541 if (reg & 0x1) { 1542 /* RAH */ 1543 retval = (eu->eu_valid << 31) | 1544 (eu->eu_addrsel << 16) | 1545 (eu->eu_eth.octet[5] << 8) | 1546 eu->eu_eth.octet[4]; 1547 } else { 1548 /* RAL */ 1549 retval = (eu->eu_eth.octet[3] << 24) | 1550 (eu->eu_eth.octet[2] << 16) | 1551 (eu->eu_eth.octet[1] << 8) | 1552 eu->eu_eth.octet[0]; 1553 } 1554 1555 return (retval); 1556 } 1557 1558 static void 1559 e82545_write_register(struct e82545_softc *sc, uint32_t offset, uint32_t value) 1560 { 1561 int ridx; 1562 1563 if (offset & 0x3) { 1564 DPRINTF("Unaligned register write offset:0x%x value:0x%x", offset, value); 1565 return; 1566 } 1567 DPRINTF("Register write: 0x%x value: 0x%x", offset, value); 1568 1569 switch (offset) { 1570 case E1000_CTRL: 1571 case E1000_CTRL_DUP: 1572 e82545_devctl(sc, value); 1573 break; 1574 case E1000_FCAL: 1575 sc->esc_FCAL = value; 1576 break; 1577 case E1000_FCAH: 1578 sc->esc_FCAH = value & ~0xFFFF0000; 1579 break; 1580 case E1000_FCT: 1581 sc->esc_FCT = value & ~0xFFFF0000; 1582 break; 1583 case E1000_VET: 1584 sc->esc_VET = value & ~0xFFFF0000; 1585 break; 1586 case E1000_FCTTV: 1587 sc->esc_FCTTV = value & ~0xFFFF0000; 1588 break; 1589 case E1000_LEDCTL: 1590 sc->esc_LEDCTL = value & ~0x30303000; 1591 break; 1592 case E1000_PBA: 1593 sc->esc_PBA = value & 0x0000FF80; 1594 break; 1595 case E1000_ICR: 1596 case E1000_ITR: 1597 case E1000_ICS: 1598 case E1000_IMS: 1599 case E1000_IMC: 1600 e82545_intr_write(sc, offset, value); 1601 break; 1602 case E1000_RCTL: 1603 e82545_rx_ctl(sc, value); 1604 break; 1605 case E1000_FCRTL: 1606 sc->esc_FCRTL = value & ~0xFFFF0007; 1607 break; 1608 case E1000_FCRTH: 1609 sc->esc_FCRTH = value & ~0xFFFF0007; 1610 break; 1611 case E1000_RDBAL(0): 1612 sc->esc_RDBAL = value & ~0xF; 1613 if (sc->esc_rx_enabled) { 1614 /* Apparently legal: update cached address */ 1615 e82545_rx_update_rdba(sc); 1616 } 1617 break; 1618 case E1000_RDBAH(0): 1619 assert(!sc->esc_rx_enabled); 1620 sc->esc_RDBAH = value; 1621 break; 1622 case E1000_RDLEN(0): 1623 assert(!sc->esc_rx_enabled); 1624 sc->esc_RDLEN = value & ~0xFFF0007F; 1625 break; 1626 case E1000_RDH(0): 1627 /* XXX should only ever be zero ? Range check ? */ 1628 sc->esc_RDH = value; 1629 break; 1630 case E1000_RDT(0): 1631 /* XXX if this opens up the rx ring, do something ? */ 1632 sc->esc_RDT = value; 1633 break; 1634 case E1000_RDTR: 1635 /* ignore FPD bit 31 */ 1636 sc->esc_RDTR = value & ~0xFFFF0000; 1637 break; 1638 case E1000_RXDCTL(0): 1639 sc->esc_RXDCTL = value & ~0xFEC0C0C0; 1640 break; 1641 case E1000_RADV: 1642 sc->esc_RADV = value & ~0xFFFF0000; 1643 break; 1644 case E1000_RSRPD: 1645 sc->esc_RSRPD = value & ~0xFFFFF000; 1646 break; 1647 case E1000_RXCSUM: 1648 sc->esc_RXCSUM = value & ~0xFFFFF800; 1649 break; 1650 case E1000_TXCW: 1651 sc->esc_TXCW = value & ~0x3FFF0000; 1652 break; 1653 case E1000_TCTL: 1654 e82545_tx_ctl(sc, value); 1655 break; 1656 case E1000_TIPG: 1657 sc->esc_TIPG = value; 1658 break; 1659 case E1000_AIT: 1660 sc->esc_AIT = value; 1661 break; 1662 case E1000_TDBAL(0): 1663 sc->esc_TDBAL = value & ~0xF; 1664 if (sc->esc_tx_enabled) 1665 e82545_tx_update_tdba(sc); 1666 break; 1667 case E1000_TDBAH(0): 1668 sc->esc_TDBAH = value; 1669 if (sc->esc_tx_enabled) 1670 e82545_tx_update_tdba(sc); 1671 break; 1672 case E1000_TDLEN(0): 1673 sc->esc_TDLEN = value & ~0xFFF0007F; 1674 if (sc->esc_tx_enabled) 1675 e82545_tx_update_tdba(sc); 1676 break; 1677 case E1000_TDH(0): 1678 //assert(!sc->esc_tx_enabled); 1679 /* XXX should only ever be zero ? Range check ? */ 1680 sc->esc_TDHr = sc->esc_TDH = value; 1681 break; 1682 case E1000_TDT(0): 1683 /* XXX range check ? */ 1684 sc->esc_TDT = value; 1685 if (sc->esc_tx_enabled) 1686 e82545_tx_start(sc); 1687 break; 1688 case E1000_TIDV: 1689 sc->esc_TIDV = value & ~0xFFFF0000; 1690 break; 1691 case E1000_TXDCTL(0): 1692 //assert(!sc->esc_tx_enabled); 1693 sc->esc_TXDCTL = value & ~0xC0C0C0; 1694 break; 1695 case E1000_TADV: 1696 sc->esc_TADV = value & ~0xFFFF0000; 1697 break; 1698 case E1000_RAL(0) ... E1000_RAH(15): 1699 /* convert to u32 offset */ 1700 ridx = (offset - E1000_RAL(0)) >> 2; 1701 e82545_write_ra(sc, ridx, value); 1702 break; 1703 case E1000_MTA ... (E1000_MTA + (127*4)): 1704 sc->esc_fmcast[(offset - E1000_MTA) >> 2] = value; 1705 break; 1706 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1707 sc->esc_fvlan[(offset - E1000_VFTA) >> 2] = value; 1708 break; 1709 case E1000_EECD: 1710 { 1711 //DPRINTF("EECD write 0x%x -> 0x%x", sc->eeprom_control, value); 1712 /* edge triggered low->high */ 1713 uint32_t eecd_strobe = ((sc->eeprom_control & E1000_EECD_SK) ? 1714 0 : (value & E1000_EECD_SK)); 1715 uint32_t eecd_mask = (E1000_EECD_SK|E1000_EECD_CS| 1716 E1000_EECD_DI|E1000_EECD_REQ); 1717 sc->eeprom_control &= ~eecd_mask; 1718 sc->eeprom_control |= (value & eecd_mask); 1719 /* grant/revoke immediately */ 1720 if (value & E1000_EECD_REQ) { 1721 sc->eeprom_control |= E1000_EECD_GNT; 1722 } else { 1723 sc->eeprom_control &= ~E1000_EECD_GNT; 1724 } 1725 if (eecd_strobe && (sc->eeprom_control & E1000_EECD_CS)) { 1726 e82545_eecd_strobe(sc); 1727 } 1728 return; 1729 } 1730 case E1000_MDIC: 1731 { 1732 uint8_t reg_addr = (uint8_t)((value & E1000_MDIC_REG_MASK) >> 1733 E1000_MDIC_REG_SHIFT); 1734 uint8_t phy_addr = (uint8_t)((value & E1000_MDIC_PHY_MASK) >> 1735 E1000_MDIC_PHY_SHIFT); 1736 sc->mdi_control = 1737 (value & ~(E1000_MDIC_ERROR|E1000_MDIC_DEST)); 1738 if ((value & E1000_MDIC_READY) != 0) { 1739 DPRINTF("Incorrect MDIC ready bit: 0x%x", value); 1740 return; 1741 } 1742 switch (value & E82545_MDIC_OP_MASK) { 1743 case E1000_MDIC_OP_READ: 1744 sc->mdi_control &= ~E82545_MDIC_DATA_MASK; 1745 sc->mdi_control |= e82545_read_mdi(sc, reg_addr, phy_addr); 1746 break; 1747 case E1000_MDIC_OP_WRITE: 1748 e82545_write_mdi(sc, reg_addr, phy_addr, 1749 value & E82545_MDIC_DATA_MASK); 1750 break; 1751 default: 1752 DPRINTF("Unknown MDIC op: 0x%x", value); 1753 return; 1754 } 1755 /* TODO: barrier? */ 1756 sc->mdi_control |= E1000_MDIC_READY; 1757 if (value & E82545_MDIC_IE) { 1758 // TODO: generate interrupt 1759 } 1760 return; 1761 } 1762 case E1000_MANC: 1763 case E1000_STATUS: 1764 return; 1765 default: 1766 DPRINTF("Unknown write register: 0x%x value:%x", offset, value); 1767 return; 1768 } 1769 } 1770 1771 static uint32_t 1772 e82545_read_register(struct e82545_softc *sc, uint32_t offset) 1773 { 1774 uint32_t retval; 1775 int ridx; 1776 1777 if (offset & 0x3) { 1778 DPRINTF("Unaligned register read offset:0x%x", offset); 1779 return 0; 1780 } 1781 1782 DPRINTF("Register read: 0x%x", offset); 1783 1784 switch (offset) { 1785 case E1000_CTRL: 1786 retval = sc->esc_CTRL; 1787 break; 1788 case E1000_STATUS: 1789 retval = E1000_STATUS_FD | E1000_STATUS_LU | 1790 E1000_STATUS_SPEED_1000; 1791 break; 1792 case E1000_FCAL: 1793 retval = sc->esc_FCAL; 1794 break; 1795 case E1000_FCAH: 1796 retval = sc->esc_FCAH; 1797 break; 1798 case E1000_FCT: 1799 retval = sc->esc_FCT; 1800 break; 1801 case E1000_VET: 1802 retval = sc->esc_VET; 1803 break; 1804 case E1000_FCTTV: 1805 retval = sc->esc_FCTTV; 1806 break; 1807 case E1000_LEDCTL: 1808 retval = sc->esc_LEDCTL; 1809 break; 1810 case E1000_PBA: 1811 retval = sc->esc_PBA; 1812 break; 1813 case E1000_ICR: 1814 case E1000_ITR: 1815 case E1000_ICS: 1816 case E1000_IMS: 1817 case E1000_IMC: 1818 retval = e82545_intr_read(sc, offset); 1819 break; 1820 case E1000_RCTL: 1821 retval = sc->esc_RCTL; 1822 break; 1823 case E1000_FCRTL: 1824 retval = sc->esc_FCRTL; 1825 break; 1826 case E1000_FCRTH: 1827 retval = sc->esc_FCRTH; 1828 break; 1829 case E1000_RDBAL(0): 1830 retval = sc->esc_RDBAL; 1831 break; 1832 case E1000_RDBAH(0): 1833 retval = sc->esc_RDBAH; 1834 break; 1835 case E1000_RDLEN(0): 1836 retval = sc->esc_RDLEN; 1837 break; 1838 case E1000_RDH(0): 1839 retval = sc->esc_RDH; 1840 break; 1841 case E1000_RDT(0): 1842 retval = sc->esc_RDT; 1843 break; 1844 case E1000_RDTR: 1845 retval = sc->esc_RDTR; 1846 break; 1847 case E1000_RXDCTL(0): 1848 retval = sc->esc_RXDCTL; 1849 break; 1850 case E1000_RADV: 1851 retval = sc->esc_RADV; 1852 break; 1853 case E1000_RSRPD: 1854 retval = sc->esc_RSRPD; 1855 break; 1856 case E1000_RXCSUM: 1857 retval = sc->esc_RXCSUM; 1858 break; 1859 case E1000_TXCW: 1860 retval = sc->esc_TXCW; 1861 break; 1862 case E1000_TCTL: 1863 retval = sc->esc_TCTL; 1864 break; 1865 case E1000_TIPG: 1866 retval = sc->esc_TIPG; 1867 break; 1868 case E1000_AIT: 1869 retval = sc->esc_AIT; 1870 break; 1871 case E1000_TDBAL(0): 1872 retval = sc->esc_TDBAL; 1873 break; 1874 case E1000_TDBAH(0): 1875 retval = sc->esc_TDBAH; 1876 break; 1877 case E1000_TDLEN(0): 1878 retval = sc->esc_TDLEN; 1879 break; 1880 case E1000_TDH(0): 1881 retval = sc->esc_TDH; 1882 break; 1883 case E1000_TDT(0): 1884 retval = sc->esc_TDT; 1885 break; 1886 case E1000_TIDV: 1887 retval = sc->esc_TIDV; 1888 break; 1889 case E1000_TXDCTL(0): 1890 retval = sc->esc_TXDCTL; 1891 break; 1892 case E1000_TADV: 1893 retval = sc->esc_TADV; 1894 break; 1895 case E1000_RAL(0) ... E1000_RAH(15): 1896 /* convert to u32 offset */ 1897 ridx = (offset - E1000_RAL(0)) >> 2; 1898 retval = e82545_read_ra(sc, ridx); 1899 break; 1900 case E1000_MTA ... (E1000_MTA + (127*4)): 1901 retval = sc->esc_fmcast[(offset - E1000_MTA) >> 2]; 1902 break; 1903 case E1000_VFTA ... (E1000_VFTA + (127*4)): 1904 retval = sc->esc_fvlan[(offset - E1000_VFTA) >> 2]; 1905 break; 1906 case E1000_EECD: 1907 //DPRINTF("EECD read %x", sc->eeprom_control); 1908 retval = sc->eeprom_control; 1909 break; 1910 case E1000_MDIC: 1911 retval = sc->mdi_control; 1912 break; 1913 case E1000_MANC: 1914 retval = 0; 1915 break; 1916 /* stats that we emulate. */ 1917 case E1000_MPC: 1918 retval = sc->missed_pkt_count; 1919 break; 1920 case E1000_PRC64: 1921 retval = sc->pkt_rx_by_size[0]; 1922 break; 1923 case E1000_PRC127: 1924 retval = sc->pkt_rx_by_size[1]; 1925 break; 1926 case E1000_PRC255: 1927 retval = sc->pkt_rx_by_size[2]; 1928 break; 1929 case E1000_PRC511: 1930 retval = sc->pkt_rx_by_size[3]; 1931 break; 1932 case E1000_PRC1023: 1933 retval = sc->pkt_rx_by_size[4]; 1934 break; 1935 case E1000_PRC1522: 1936 retval = sc->pkt_rx_by_size[5]; 1937 break; 1938 case E1000_GPRC: 1939 retval = sc->good_pkt_rx_count; 1940 break; 1941 case E1000_BPRC: 1942 retval = sc->bcast_pkt_rx_count; 1943 break; 1944 case E1000_MPRC: 1945 retval = sc->mcast_pkt_rx_count; 1946 break; 1947 case E1000_GPTC: 1948 case E1000_TPT: 1949 retval = sc->good_pkt_tx_count; 1950 break; 1951 case E1000_GORCL: 1952 retval = (uint32_t)sc->good_octets_rx; 1953 break; 1954 case E1000_GORCH: 1955 retval = (uint32_t)(sc->good_octets_rx >> 32); 1956 break; 1957 case E1000_TOTL: 1958 case E1000_GOTCL: 1959 retval = (uint32_t)sc->good_octets_tx; 1960 break; 1961 case E1000_TOTH: 1962 case E1000_GOTCH: 1963 retval = (uint32_t)(sc->good_octets_tx >> 32); 1964 break; 1965 case E1000_ROC: 1966 retval = sc->oversize_rx_count; 1967 break; 1968 case E1000_TORL: 1969 retval = (uint32_t)(sc->good_octets_rx + sc->missed_octets); 1970 break; 1971 case E1000_TORH: 1972 retval = (uint32_t)((sc->good_octets_rx + 1973 sc->missed_octets) >> 32); 1974 break; 1975 case E1000_TPR: 1976 retval = sc->good_pkt_rx_count + sc->missed_pkt_count + 1977 sc->oversize_rx_count; 1978 break; 1979 case E1000_PTC64: 1980 retval = sc->pkt_tx_by_size[0]; 1981 break; 1982 case E1000_PTC127: 1983 retval = sc->pkt_tx_by_size[1]; 1984 break; 1985 case E1000_PTC255: 1986 retval = sc->pkt_tx_by_size[2]; 1987 break; 1988 case E1000_PTC511: 1989 retval = sc->pkt_tx_by_size[3]; 1990 break; 1991 case E1000_PTC1023: 1992 retval = sc->pkt_tx_by_size[4]; 1993 break; 1994 case E1000_PTC1522: 1995 retval = sc->pkt_tx_by_size[5]; 1996 break; 1997 case E1000_MPTC: 1998 retval = sc->mcast_pkt_tx_count; 1999 break; 2000 case E1000_BPTC: 2001 retval = sc->bcast_pkt_tx_count; 2002 break; 2003 case E1000_TSCTC: 2004 retval = sc->tso_tx_count; 2005 break; 2006 /* stats that are always 0. */ 2007 case E1000_CRCERRS: 2008 case E1000_ALGNERRC: 2009 case E1000_SYMERRS: 2010 case E1000_RXERRC: 2011 case E1000_SCC: 2012 case E1000_ECOL: 2013 case E1000_MCC: 2014 case E1000_LATECOL: 2015 case E1000_COLC: 2016 case E1000_DC: 2017 case E1000_TNCRS: 2018 case E1000_SEC: 2019 case E1000_CEXTERR: 2020 case E1000_RLEC: 2021 case E1000_XONRXC: 2022 case E1000_XONTXC: 2023 case E1000_XOFFRXC: 2024 case E1000_XOFFTXC: 2025 case E1000_FCRUC: 2026 case E1000_RNBC: 2027 case E1000_RUC: 2028 case E1000_RFC: 2029 case E1000_RJC: 2030 case E1000_MGTPRC: 2031 case E1000_MGTPDC: 2032 case E1000_MGTPTC: 2033 case E1000_TSCTFC: 2034 retval = 0; 2035 break; 2036 default: 2037 DPRINTF("Unknown read register: 0x%x", offset); 2038 retval = 0; 2039 break; 2040 } 2041 2042 return (retval); 2043 } 2044 2045 static void 2046 e82545_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2047 uint64_t offset, int size, uint64_t value) 2048 { 2049 struct e82545_softc *sc; 2050 2051 //DPRINTF("Write bar:%d offset:0x%lx value:0x%lx size:%d", baridx, offset, value, size); 2052 2053 sc = pi->pi_arg; 2054 2055 pthread_mutex_lock(&sc->esc_mtx); 2056 2057 switch (baridx) { 2058 case E82545_BAR_IO: 2059 switch (offset) { 2060 case E82545_IOADDR: 2061 if (size != 4) { 2062 DPRINTF("Wrong io addr write sz:%d value:0x%lx", size, value); 2063 } else 2064 sc->io_addr = (uint32_t)value; 2065 break; 2066 case E82545_IODATA: 2067 if (size != 4) { 2068 DPRINTF("Wrong io data write size:%d value:0x%lx", size, value); 2069 } else if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2070 DPRINTF("Non-register io write addr:0x%x value:0x%lx", sc->io_addr, value); 2071 } else 2072 e82545_write_register(sc, sc->io_addr, 2073 (uint32_t)value); 2074 break; 2075 default: 2076 DPRINTF("Unknown io bar write offset:0x%lx value:0x%lx size:%d", offset, value, size); 2077 break; 2078 } 2079 break; 2080 case E82545_BAR_REGISTER: 2081 if (size != 4) { 2082 DPRINTF("Wrong register write size:%d offset:0x%lx value:0x%lx", size, offset, value); 2083 } else 2084 e82545_write_register(sc, (uint32_t)offset, 2085 (uint32_t)value); 2086 break; 2087 default: 2088 DPRINTF("Unknown write bar:%d off:0x%lx val:0x%lx size:%d", 2089 baridx, offset, value, size); 2090 } 2091 2092 pthread_mutex_unlock(&sc->esc_mtx); 2093 } 2094 2095 static uint64_t 2096 e82545_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2097 uint64_t offset, int size) 2098 { 2099 struct e82545_softc *sc; 2100 uint64_t retval; 2101 2102 //DPRINTF("Read bar:%d offset:0x%lx size:%d", baridx, offset, size); 2103 sc = pi->pi_arg; 2104 retval = 0; 2105 2106 pthread_mutex_lock(&sc->esc_mtx); 2107 2108 switch (baridx) { 2109 case E82545_BAR_IO: 2110 switch (offset) { 2111 case E82545_IOADDR: 2112 if (size != 4) { 2113 DPRINTF("Wrong io addr read sz:%d", size); 2114 } else 2115 retval = sc->io_addr; 2116 break; 2117 case E82545_IODATA: 2118 if (size != 4) { 2119 DPRINTF("Wrong io data read sz:%d", size); 2120 } 2121 if (sc->io_addr > E82545_IO_REGISTER_MAX) { 2122 DPRINTF("Non-register io read addr:0x%x", 2123 sc->io_addr); 2124 } else 2125 retval = e82545_read_register(sc, sc->io_addr); 2126 break; 2127 default: 2128 DPRINTF("Unknown io bar read offset:0x%lx size:%d", 2129 offset, size); 2130 break; 2131 } 2132 break; 2133 case E82545_BAR_REGISTER: 2134 if (size != 4) { 2135 DPRINTF("Wrong register read size:%d offset:0x%lx", 2136 size, offset); 2137 } else 2138 retval = e82545_read_register(sc, (uint32_t)offset); 2139 break; 2140 default: 2141 DPRINTF("Unknown read bar:%d offset:0x%lx size:%d", 2142 baridx, offset, size); 2143 break; 2144 } 2145 2146 pthread_mutex_unlock(&sc->esc_mtx); 2147 2148 return (retval); 2149 } 2150 2151 static void 2152 e82545_reset(struct e82545_softc *sc, int drvr) 2153 { 2154 int i; 2155 2156 e82545_rx_disable(sc); 2157 e82545_tx_disable(sc); 2158 2159 /* clear outstanding interrupts */ 2160 if (sc->esc_irq_asserted) 2161 pci_lintr_deassert(sc->esc_pi); 2162 2163 /* misc */ 2164 if (!drvr) { 2165 sc->esc_FCAL = 0; 2166 sc->esc_FCAH = 0; 2167 sc->esc_FCT = 0; 2168 sc->esc_VET = 0; 2169 sc->esc_FCTTV = 0; 2170 } 2171 sc->esc_LEDCTL = 0x07061302; 2172 sc->esc_PBA = 0x00100030; 2173 2174 /* start nvm in opcode mode. */ 2175 sc->nvm_opaddr = 0; 2176 sc->nvm_mode = E82545_NVM_MODE_OPADDR; 2177 sc->nvm_bits = E82545_NVM_OPADDR_BITS; 2178 sc->eeprom_control = E1000_EECD_PRES | E82545_EECD_FWE_EN; 2179 e82545_init_eeprom(sc); 2180 2181 /* interrupt */ 2182 sc->esc_ICR = 0; 2183 sc->esc_ITR = 250; 2184 sc->esc_ICS = 0; 2185 sc->esc_IMS = 0; 2186 sc->esc_IMC = 0; 2187 2188 /* L2 filters */ 2189 if (!drvr) { 2190 memset(sc->esc_fvlan, 0, sizeof(sc->esc_fvlan)); 2191 memset(sc->esc_fmcast, 0, sizeof(sc->esc_fmcast)); 2192 memset(sc->esc_uni, 0, sizeof(sc->esc_uni)); 2193 2194 /* XXX not necessary on 82545 ?? */ 2195 sc->esc_uni[0].eu_valid = 1; 2196 memcpy(sc->esc_uni[0].eu_eth.octet, sc->esc_mac.octet, 2197 ETHER_ADDR_LEN); 2198 } else { 2199 /* Clear RAH valid bits */ 2200 for (i = 0; i < 16; i++) 2201 sc->esc_uni[i].eu_valid = 0; 2202 } 2203 2204 /* receive */ 2205 if (!drvr) { 2206 sc->esc_RDBAL = 0; 2207 sc->esc_RDBAH = 0; 2208 } 2209 sc->esc_RCTL = 0; 2210 sc->esc_FCRTL = 0; 2211 sc->esc_FCRTH = 0; 2212 sc->esc_RDLEN = 0; 2213 sc->esc_RDH = 0; 2214 sc->esc_RDT = 0; 2215 sc->esc_RDTR = 0; 2216 sc->esc_RXDCTL = (1 << 24) | (1 << 16); /* default GRAN/WTHRESH */ 2217 sc->esc_RADV = 0; 2218 sc->esc_RXCSUM = 0; 2219 2220 /* transmit */ 2221 if (!drvr) { 2222 sc->esc_TDBAL = 0; 2223 sc->esc_TDBAH = 0; 2224 sc->esc_TIPG = 0; 2225 sc->esc_AIT = 0; 2226 sc->esc_TIDV = 0; 2227 sc->esc_TADV = 0; 2228 } 2229 sc->esc_tdba = 0; 2230 sc->esc_txdesc = NULL; 2231 sc->esc_TXCW = 0; 2232 sc->esc_TCTL = 0; 2233 sc->esc_TDLEN = 0; 2234 sc->esc_TDT = 0; 2235 sc->esc_TDHr = sc->esc_TDH = 0; 2236 sc->esc_TXDCTL = 0; 2237 } 2238 2239 static void 2240 e82545_open_tap(struct e82545_softc *sc, const char *path) 2241 { 2242 char tbuf[80]; 2243 #ifndef WITHOUT_CAPSICUM 2244 cap_rights_t rights; 2245 #endif 2246 2247 if (path == NULL) { 2248 sc->esc_tapfd = -1; 2249 return; 2250 } 2251 2252 strcpy(tbuf, "/dev/"); 2253 strlcat(tbuf, path, sizeof(tbuf)); 2254 2255 sc->esc_tapfd = open(tbuf, O_RDWR); 2256 if (sc->esc_tapfd == -1) { 2257 DPRINTF("unable to open tap device %s\n", path); 2258 exit(4); 2259 } 2260 2261 /* 2262 * Set non-blocking and register for read 2263 * notifications with the event loop 2264 */ 2265 int opt = 1; 2266 if (ioctl(sc->esc_tapfd, FIONBIO, &opt) < 0) { 2267 WPRINTF("tap device O_NONBLOCK failed: %d\n", errno); 2268 close(sc->esc_tapfd); 2269 sc->esc_tapfd = -1; 2270 } 2271 2272 #ifndef WITHOUT_CAPSICUM 2273 cap_rights_init(&rights, CAP_EVENT, CAP_READ, CAP_WRITE); 2274 if (caph_rights_limit(sc->esc_tapfd, &rights) == -1) 2275 errx(EX_OSERR, "Unable to apply rights for sandbox"); 2276 #endif 2277 2278 #ifdef __FreeBSD__ 2279 sc->esc_mevp = mevent_add(sc->esc_tapfd, 2280 EVF_READ, 2281 e82545_rx_callback, 2282 sc); 2283 if (sc->esc_mevp == NULL) { 2284 DPRINTF("Could not register mevent %d\n", EVF_READ); 2285 close(sc->esc_tapfd); 2286 sc->esc_tapfd = -1; 2287 } 2288 #endif 2289 } 2290 2291 static int 2292 e82545_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl) 2293 { 2294 char nstr[80]; 2295 struct e82545_softc *sc; 2296 const char *mac; 2297 int err; 2298 2299 /* Setup our softc */ 2300 sc = calloc(1, sizeof(*sc)); 2301 2302 pi->pi_arg = sc; 2303 sc->esc_pi = pi; 2304 sc->esc_ctx = ctx; 2305 2306 pthread_mutex_init(&sc->esc_mtx, NULL); 2307 pthread_cond_init(&sc->esc_rx_cond, NULL); 2308 pthread_cond_init(&sc->esc_tx_cond, NULL); 2309 pthread_create(&sc->esc_tx_tid, NULL, e82545_tx_thread, sc); 2310 snprintf(nstr, sizeof(nstr), "e82545-%d:%d tx", pi->pi_slot, 2311 pi->pi_func); 2312 pthread_set_name_np(sc->esc_tx_tid, nstr); 2313 2314 pci_set_cfgdata16(pi, PCIR_DEVICE, E82545_DEV_ID_82545EM_COPPER); 2315 pci_set_cfgdata16(pi, PCIR_VENDOR, E82545_VENDOR_ID_INTEL); 2316 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK); 2317 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_NETWORK_ETHERNET); 2318 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, E82545_SUBDEV_ID); 2319 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, E82545_VENDOR_ID_INTEL); 2320 2321 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL); 2322 pci_set_cfgdata8(pi, PCIR_INTPIN, 0x1); 2323 2324 /* TODO: this card also supports msi, but the freebsd driver for it 2325 * does not, so I have not implemented it. */ 2326 pci_lintr_request(pi); 2327 2328 pci_emul_alloc_bar(pi, E82545_BAR_REGISTER, PCIBAR_MEM32, 2329 E82545_BAR_REGISTER_LEN); 2330 pci_emul_alloc_bar(pi, E82545_BAR_FLASH, PCIBAR_MEM32, 2331 E82545_BAR_FLASH_LEN); 2332 pci_emul_alloc_bar(pi, E82545_BAR_IO, PCIBAR_IO, 2333 E82545_BAR_IO_LEN); 2334 2335 mac = get_config_value_node(nvl, "mac"); 2336 if (mac != NULL) { 2337 err = net_parsemac(mac, sc->esc_mac.octet); 2338 if (err) { 2339 free(sc); 2340 return (err); 2341 } 2342 } else 2343 net_genmac(pi, sc->esc_mac.octet); 2344 2345 const char *tap = get_config_value_node(nvl, "tap"); 2346 if (tap != NULL && (strncmp(tap, "tap", 3) == 0 || 2347 strncmp(tap, "vmnet", 5) == 0)) 2348 e82545_open_tap(sc, tap); 2349 2350 /* H/w initiated reset */ 2351 e82545_reset(sc, 0); 2352 2353 return (0); 2354 } 2355 2356 #ifndef __FreeBSD__ 2357 static int 2358 e82545_legacy_config(nvlist_t *nvl, const char *opt) 2359 { 2360 char *config, *name, *tofree, *value; 2361 2362 if (opt == NULL) 2363 return (0); 2364 2365 config = tofree = strdup(opt); 2366 while ((name = strsep(&config, ",")) != NULL) { 2367 value = strchr(name, '='); 2368 if (value != NULL) { 2369 *value++ = '\0'; 2370 set_config_value_node(nvl, name, value); 2371 } else { 2372 set_config_value_node(nvl, "tap", name); 2373 } 2374 } 2375 free(tofree); 2376 return (0); 2377 } 2378 #endif 2379 2380 struct pci_devemu pci_de_e82545 = { 2381 .pe_emu = "e1000", 2382 .pe_init = e82545_init, 2383 #ifdef __FreeBSD__ 2384 .pe_legacy_config = netbe_legacy_config, 2385 #else 2386 .pe_legacy_config = e82545_legacy_config, 2387 #endif 2388 .pe_barwrite = e82545_write, 2389 .pe_barread = e82545_read 2390 }; 2391 PCI_EMUL_SET(pci_de_e82545); 2392 2393