1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org> 5 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/linker_set.h> 37 #include <sys/stat.h> 38 #include <sys/uio.h> 39 #include <sys/ioctl.h> 40 #include <sys/disk.h> 41 #include <sys/ata.h> 42 #include <sys/endian.h> 43 44 #include <errno.h> 45 #include <fcntl.h> 46 #include <stdio.h> 47 #include <stdlib.h> 48 #include <stdint.h> 49 #include <string.h> 50 #include <strings.h> 51 #include <unistd.h> 52 #include <assert.h> 53 #include <pthread.h> 54 #include <pthread_np.h> 55 #include <inttypes.h> 56 #include <md5.h> 57 58 #include "bhyverun.h" 59 #include "pci_emul.h" 60 #include "ahci.h" 61 #include "block_if.h" 62 63 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */ 64 #define MAX_PORTS 32 /* AHCI supports 32 ports */ 65 66 #define PxSIG_ATA 0x00000101 /* ATA drive */ 67 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */ 68 69 enum sata_fis_type { 70 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */ 71 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */ 72 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */ 73 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */ 74 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */ 75 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */ 76 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */ 77 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */ 78 }; 79 80 /* 81 * SCSI opcodes 82 */ 83 #define TEST_UNIT_READY 0x00 84 #define REQUEST_SENSE 0x03 85 #define INQUIRY 0x12 86 #define START_STOP_UNIT 0x1B 87 #define PREVENT_ALLOW 0x1E 88 #define READ_CAPACITY 0x25 89 #define READ_10 0x28 90 #define POSITION_TO_ELEMENT 0x2B 91 #define READ_TOC 0x43 92 #define GET_EVENT_STATUS_NOTIFICATION 0x4A 93 #define MODE_SENSE_10 0x5A 94 #define REPORT_LUNS 0xA0 95 #define READ_12 0xA8 96 #define READ_CD 0xBE 97 98 /* 99 * SCSI mode page codes 100 */ 101 #define MODEPAGE_RW_ERROR_RECOVERY 0x01 102 #define MODEPAGE_CD_CAPABILITIES 0x2A 103 104 /* 105 * ATA commands 106 */ 107 #define ATA_SF_ENAB_SATA_SF 0x10 108 #define ATA_SATA_SF_AN 0x05 109 #define ATA_SF_DIS_SATA_SF 0x90 110 111 /* 112 * Debug printf 113 */ 114 #ifdef AHCI_DEBUG 115 static FILE *dbg; 116 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) 117 #else 118 #define DPRINTF(format, arg...) 119 #endif 120 #define WPRINTF(format, arg...) printf(format, ##arg) 121 122 #define AHCI_PORT_IDENT 20 + 1 123 124 struct ahci_ioreq { 125 struct blockif_req io_req; 126 struct ahci_port *io_pr; 127 STAILQ_ENTRY(ahci_ioreq) io_flist; 128 TAILQ_ENTRY(ahci_ioreq) io_blist; 129 uint8_t *cfis; 130 uint32_t len; 131 uint32_t done; 132 int slot; 133 int more; 134 }; 135 136 struct ahci_port { 137 struct blockif_ctxt *bctx; 138 struct pci_ahci_softc *pr_sc; 139 uint8_t *cmd_lst; 140 uint8_t *rfis; 141 char ident[AHCI_PORT_IDENT]; 142 int port; 143 int atapi; 144 int reset; 145 int waitforclear; 146 int mult_sectors; 147 uint8_t xfermode; 148 uint8_t err_cfis[20]; 149 uint8_t sense_key; 150 uint8_t asc; 151 u_int ccs; 152 uint32_t pending; 153 154 uint32_t clb; 155 uint32_t clbu; 156 uint32_t fb; 157 uint32_t fbu; 158 uint32_t is; 159 uint32_t ie; 160 uint32_t cmd; 161 uint32_t unused0; 162 uint32_t tfd; 163 uint32_t sig; 164 uint32_t ssts; 165 uint32_t sctl; 166 uint32_t serr; 167 uint32_t sact; 168 uint32_t ci; 169 uint32_t sntf; 170 uint32_t fbs; 171 172 /* 173 * i/o request info 174 */ 175 struct ahci_ioreq *ioreq; 176 int ioqsz; 177 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd; 178 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd; 179 }; 180 181 struct ahci_cmd_hdr { 182 uint16_t flags; 183 uint16_t prdtl; 184 uint32_t prdbc; 185 uint64_t ctba; 186 uint32_t reserved[4]; 187 }; 188 189 struct ahci_prdt_entry { 190 uint64_t dba; 191 uint32_t reserved; 192 #define DBCMASK 0x3fffff 193 uint32_t dbc; 194 }; 195 196 struct pci_ahci_softc { 197 struct pci_devinst *asc_pi; 198 pthread_mutex_t mtx; 199 int ports; 200 uint32_t cap; 201 uint32_t ghc; 202 uint32_t is; 203 uint32_t pi; 204 uint32_t vs; 205 uint32_t ccc_ctl; 206 uint32_t ccc_pts; 207 uint32_t em_loc; 208 uint32_t em_ctl; 209 uint32_t cap2; 210 uint32_t bohc; 211 uint32_t lintr; 212 struct ahci_port port[MAX_PORTS]; 213 }; 214 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx) 215 216 static void ahci_handle_port(struct ahci_port *p); 217 218 static inline void lba_to_msf(uint8_t *buf, int lba) 219 { 220 lba += 150; 221 buf[0] = (lba / 75) / 60; 222 buf[1] = (lba / 75) % 60; 223 buf[2] = lba % 75; 224 } 225 226 /* 227 * Generate HBA interrupts on global IS register write. 228 */ 229 static void 230 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask) 231 { 232 struct pci_devinst *pi = sc->asc_pi; 233 struct ahci_port *p; 234 int i, nmsg; 235 uint32_t mmask; 236 237 /* Update global IS from PxIS/PxIE. */ 238 for (i = 0; i < sc->ports; i++) { 239 p = &sc->port[i]; 240 if (p->is & p->ie) 241 sc->is |= (1 << i); 242 } 243 DPRINTF("%s(%08x) %08x", __func__, mask, sc->is); 244 245 /* If there is nothing enabled -- clear legacy interrupt and exit. */ 246 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) { 247 if (sc->lintr) { 248 pci_lintr_deassert(pi); 249 sc->lintr = 0; 250 } 251 return; 252 } 253 254 /* If there is anything and no MSI -- assert legacy interrupt. */ 255 nmsg = pci_msi_maxmsgnum(pi); 256 if (nmsg == 0) { 257 if (!sc->lintr) { 258 sc->lintr = 1; 259 pci_lintr_assert(pi); 260 } 261 return; 262 } 263 264 /* Assert respective MSIs for ports that were touched. */ 265 for (i = 0; i < nmsg; i++) { 266 if (sc->ports <= nmsg || i < nmsg - 1) 267 mmask = 1 << i; 268 else 269 mmask = 0xffffffff << i; 270 if (sc->is & mask && mmask & mask) 271 pci_generate_msi(pi, i); 272 } 273 } 274 275 /* 276 * Generate HBA interrupt on specific port event. 277 */ 278 static void 279 ahci_port_intr(struct ahci_port *p) 280 { 281 struct pci_ahci_softc *sc = p->pr_sc; 282 struct pci_devinst *pi = sc->asc_pi; 283 int nmsg; 284 285 DPRINTF("%s(%d) %08x/%08x %08x", __func__, 286 p->port, p->is, p->ie, sc->is); 287 288 /* If there is nothing enabled -- we are done. */ 289 if ((p->is & p->ie) == 0) 290 return; 291 292 /* In case of non-shared MSI always generate interrupt. */ 293 nmsg = pci_msi_maxmsgnum(pi); 294 if (sc->ports <= nmsg || p->port < nmsg - 1) { 295 sc->is |= (1 << p->port); 296 if ((sc->ghc & AHCI_GHC_IE) == 0) 297 return; 298 pci_generate_msi(pi, p->port); 299 return; 300 } 301 302 /* If IS for this port is already set -- do nothing. */ 303 if (sc->is & (1 << p->port)) 304 return; 305 306 sc->is |= (1 << p->port); 307 308 /* If interrupts are enabled -- generate one. */ 309 if ((sc->ghc & AHCI_GHC_IE) == 0) 310 return; 311 if (nmsg > 0) { 312 pci_generate_msi(pi, nmsg - 1); 313 } else if (!sc->lintr) { 314 sc->lintr = 1; 315 pci_lintr_assert(pi); 316 } 317 } 318 319 static void 320 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis) 321 { 322 int offset, len, irq; 323 324 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE)) 325 return; 326 327 switch (ft) { 328 case FIS_TYPE_REGD2H: 329 offset = 0x40; 330 len = 20; 331 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0; 332 break; 333 case FIS_TYPE_SETDEVBITS: 334 offset = 0x58; 335 len = 8; 336 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0; 337 break; 338 case FIS_TYPE_PIOSETUP: 339 offset = 0x20; 340 len = 20; 341 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0; 342 break; 343 default: 344 WPRINTF("unsupported fis type %d", ft); 345 return; 346 } 347 if (fis[2] & ATA_S_ERROR) { 348 p->waitforclear = 1; 349 irq |= AHCI_P_IX_TFE; 350 } 351 memcpy(p->rfis + offset, fis, len); 352 if (irq) { 353 if (~p->is & irq) { 354 p->is |= irq; 355 ahci_port_intr(p); 356 } 357 } 358 } 359 360 static void 361 ahci_write_fis_piosetup(struct ahci_port *p) 362 { 363 uint8_t fis[20]; 364 365 memset(fis, 0, sizeof(fis)); 366 fis[0] = FIS_TYPE_PIOSETUP; 367 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis); 368 } 369 370 static void 371 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 372 { 373 uint8_t fis[8]; 374 uint8_t error; 375 376 error = (tfd >> 8) & 0xff; 377 tfd &= 0x77; 378 memset(fis, 0, sizeof(fis)); 379 fis[0] = FIS_TYPE_SETDEVBITS; 380 fis[1] = (1 << 6); 381 fis[2] = tfd; 382 fis[3] = error; 383 if (fis[2] & ATA_S_ERROR) { 384 p->err_cfis[0] = slot; 385 p->err_cfis[2] = tfd; 386 p->err_cfis[3] = error; 387 memcpy(&p->err_cfis[4], cfis + 4, 16); 388 } else { 389 *(uint32_t *)(fis + 4) = (1 << slot); 390 p->sact &= ~(1 << slot); 391 } 392 p->tfd &= ~0x77; 393 p->tfd |= tfd; 394 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis); 395 } 396 397 static void 398 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 399 { 400 uint8_t fis[20]; 401 uint8_t error; 402 403 error = (tfd >> 8) & 0xff; 404 memset(fis, 0, sizeof(fis)); 405 fis[0] = FIS_TYPE_REGD2H; 406 fis[1] = (1 << 6); 407 fis[2] = tfd & 0xff; 408 fis[3] = error; 409 fis[4] = cfis[4]; 410 fis[5] = cfis[5]; 411 fis[6] = cfis[6]; 412 fis[7] = cfis[7]; 413 fis[8] = cfis[8]; 414 fis[9] = cfis[9]; 415 fis[10] = cfis[10]; 416 fis[11] = cfis[11]; 417 fis[12] = cfis[12]; 418 fis[13] = cfis[13]; 419 if (fis[2] & ATA_S_ERROR) { 420 p->err_cfis[0] = 0x80; 421 p->err_cfis[2] = tfd & 0xff; 422 p->err_cfis[3] = error; 423 memcpy(&p->err_cfis[4], cfis + 4, 16); 424 } else 425 p->ci &= ~(1 << slot); 426 p->tfd = tfd; 427 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 428 } 429 430 static void 431 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot) 432 { 433 uint8_t fis[20]; 434 435 p->tfd = ATA_S_READY | ATA_S_DSC; 436 memset(fis, 0, sizeof(fis)); 437 fis[0] = FIS_TYPE_REGD2H; 438 fis[1] = 0; /* No interrupt */ 439 fis[2] = p->tfd; /* Status */ 440 fis[3] = 0; /* No error */ 441 p->ci &= ~(1 << slot); 442 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 443 } 444 445 static void 446 ahci_write_reset_fis_d2h(struct ahci_port *p) 447 { 448 uint8_t fis[20]; 449 450 memset(fis, 0, sizeof(fis)); 451 fis[0] = FIS_TYPE_REGD2H; 452 fis[3] = 1; 453 fis[4] = 1; 454 if (p->atapi) { 455 fis[5] = 0x14; 456 fis[6] = 0xeb; 457 } 458 fis[12] = 1; 459 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 460 } 461 462 static void 463 ahci_check_stopped(struct ahci_port *p) 464 { 465 /* 466 * If we are no longer processing the command list and nothing 467 * is in-flight, clear the running bit, the current command 468 * slot, the command issue and active bits. 469 */ 470 if (!(p->cmd & AHCI_P_CMD_ST)) { 471 if (p->pending == 0) { 472 p->ccs = 0; 473 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK); 474 p->ci = 0; 475 p->sact = 0; 476 p->waitforclear = 0; 477 } 478 } 479 } 480 481 static void 482 ahci_port_stop(struct ahci_port *p) 483 { 484 struct ahci_ioreq *aior; 485 uint8_t *cfis; 486 int slot; 487 int error; 488 489 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx)); 490 491 TAILQ_FOREACH(aior, &p->iobhd, io_blist) { 492 /* 493 * Try to cancel the outstanding blockif request. 494 */ 495 error = blockif_cancel(p->bctx, &aior->io_req); 496 if (error != 0) 497 continue; 498 499 slot = aior->slot; 500 cfis = aior->cfis; 501 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 502 cfis[2] == ATA_READ_FPDMA_QUEUED || 503 cfis[2] == ATA_SEND_FPDMA_QUEUED) 504 p->sact &= ~(1 << slot); /* NCQ */ 505 else 506 p->ci &= ~(1 << slot); 507 508 /* 509 * This command is now done. 510 */ 511 p->pending &= ~(1 << slot); 512 513 /* 514 * Delete the blockif request from the busy list 515 */ 516 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 517 518 /* 519 * Move the blockif request back to the free list 520 */ 521 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 522 } 523 524 ahci_check_stopped(p); 525 } 526 527 static void 528 ahci_port_reset(struct ahci_port *pr) 529 { 530 pr->serr = 0; 531 pr->sact = 0; 532 pr->xfermode = ATA_UDMA6; 533 pr->mult_sectors = 128; 534 535 if (!pr->bctx) { 536 pr->ssts = ATA_SS_DET_NO_DEVICE; 537 pr->sig = 0xFFFFFFFF; 538 pr->tfd = 0x7F; 539 return; 540 } 541 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE; 542 if (pr->sctl & ATA_SC_SPD_MASK) 543 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK); 544 else 545 pr->ssts |= ATA_SS_SPD_GEN3; 546 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA; 547 if (!pr->atapi) { 548 pr->sig = PxSIG_ATA; 549 pr->tfd |= ATA_S_READY; 550 } else 551 pr->sig = PxSIG_ATAPI; 552 ahci_write_reset_fis_d2h(pr); 553 } 554 555 static void 556 ahci_reset(struct pci_ahci_softc *sc) 557 { 558 int i; 559 560 sc->ghc = AHCI_GHC_AE; 561 sc->is = 0; 562 563 if (sc->lintr) { 564 pci_lintr_deassert(sc->asc_pi); 565 sc->lintr = 0; 566 } 567 568 for (i = 0; i < sc->ports; i++) { 569 sc->port[i].ie = 0; 570 sc->port[i].is = 0; 571 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD); 572 if (sc->port[i].bctx) 573 sc->port[i].cmd |= AHCI_P_CMD_CPS; 574 sc->port[i].sctl = 0; 575 ahci_port_reset(&sc->port[i]); 576 } 577 } 578 579 static void 580 ata_string(uint8_t *dest, const char *src, int len) 581 { 582 int i; 583 584 for (i = 0; i < len; i++) { 585 if (*src) 586 dest[i ^ 1] = *src++; 587 else 588 dest[i ^ 1] = ' '; 589 } 590 } 591 592 static void 593 atapi_string(uint8_t *dest, const char *src, int len) 594 { 595 int i; 596 597 for (i = 0; i < len; i++) { 598 if (*src) 599 dest[i] = *src++; 600 else 601 dest[i] = ' '; 602 } 603 } 604 605 /* 606 * Build up the iovec based on the PRDT, 'done' and 'len'. 607 */ 608 static void 609 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior, 610 struct ahci_prdt_entry *prdt, uint16_t prdtl) 611 { 612 struct blockif_req *breq = &aior->io_req; 613 int i, j, skip, todo, left, extra; 614 uint32_t dbcsz; 615 616 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */ 617 skip = aior->done; 618 left = aior->len - aior->done; 619 todo = 0; 620 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0; 621 i++, prdt++) { 622 dbcsz = (prdt->dbc & DBCMASK) + 1; 623 /* Skip already done part of the PRDT */ 624 if (dbcsz <= skip) { 625 skip -= dbcsz; 626 continue; 627 } 628 dbcsz -= skip; 629 if (dbcsz > left) 630 dbcsz = left; 631 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc), 632 prdt->dba + skip, dbcsz); 633 breq->br_iov[j].iov_len = dbcsz; 634 todo += dbcsz; 635 left -= dbcsz; 636 skip = 0; 637 j++; 638 } 639 640 /* If we got limited by IOV length, round I/O down to sector size. */ 641 if (j == BLOCKIF_IOV_MAX) { 642 extra = todo % blockif_sectsz(p->bctx); 643 todo -= extra; 644 assert(todo > 0); 645 while (extra > 0) { 646 if (breq->br_iov[j - 1].iov_len > extra) { 647 breq->br_iov[j - 1].iov_len -= extra; 648 break; 649 } 650 extra -= breq->br_iov[j - 1].iov_len; 651 j--; 652 } 653 } 654 655 breq->br_iovcnt = j; 656 breq->br_resid = todo; 657 aior->done += todo; 658 aior->more = (aior->done < aior->len && i < prdtl); 659 } 660 661 static void 662 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 663 { 664 struct ahci_ioreq *aior; 665 struct blockif_req *breq; 666 struct ahci_prdt_entry *prdt; 667 struct ahci_cmd_hdr *hdr; 668 uint64_t lba; 669 uint32_t len; 670 int err, first, ncq, readop; 671 672 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 673 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 674 ncq = 0; 675 readop = 1; 676 first = (done == 0); 677 678 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 || 679 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 || 680 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 || 681 cfis[2] == ATA_WRITE_FPDMA_QUEUED) 682 readop = 0; 683 684 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 685 cfis[2] == ATA_READ_FPDMA_QUEUED) { 686 lba = ((uint64_t)cfis[10] << 40) | 687 ((uint64_t)cfis[9] << 32) | 688 ((uint64_t)cfis[8] << 24) | 689 ((uint64_t)cfis[6] << 16) | 690 ((uint64_t)cfis[5] << 8) | 691 cfis[4]; 692 len = cfis[11] << 8 | cfis[3]; 693 if (!len) 694 len = 65536; 695 ncq = 1; 696 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 || 697 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 || 698 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) { 699 lba = ((uint64_t)cfis[10] << 40) | 700 ((uint64_t)cfis[9] << 32) | 701 ((uint64_t)cfis[8] << 24) | 702 ((uint64_t)cfis[6] << 16) | 703 ((uint64_t)cfis[5] << 8) | 704 cfis[4]; 705 len = cfis[13] << 8 | cfis[12]; 706 if (!len) 707 len = 65536; 708 } else { 709 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) | 710 (cfis[5] << 8) | cfis[4]; 711 len = cfis[12]; 712 if (!len) 713 len = 256; 714 } 715 lba *= blockif_sectsz(p->bctx); 716 len *= blockif_sectsz(p->bctx); 717 718 /* Pull request off free list */ 719 aior = STAILQ_FIRST(&p->iofhd); 720 assert(aior != NULL); 721 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 722 723 aior->cfis = cfis; 724 aior->slot = slot; 725 aior->len = len; 726 aior->done = done; 727 breq = &aior->io_req; 728 breq->br_offset = lba + done; 729 ahci_build_iov(p, aior, prdt, hdr->prdtl); 730 731 /* Mark this command in-flight. */ 732 p->pending |= 1 << slot; 733 734 /* Stuff request onto busy list. */ 735 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 736 737 if (ncq && first) 738 ahci_write_fis_d2h_ncq(p, slot); 739 740 if (readop) 741 err = blockif_read(p->bctx, breq); 742 else 743 err = blockif_write(p->bctx, breq); 744 assert(err == 0); 745 } 746 747 static void 748 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis) 749 { 750 struct ahci_ioreq *aior; 751 struct blockif_req *breq; 752 int err; 753 754 /* 755 * Pull request off free list 756 */ 757 aior = STAILQ_FIRST(&p->iofhd); 758 assert(aior != NULL); 759 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 760 aior->cfis = cfis; 761 aior->slot = slot; 762 aior->len = 0; 763 aior->done = 0; 764 aior->more = 0; 765 breq = &aior->io_req; 766 767 /* 768 * Mark this command in-flight. 769 */ 770 p->pending |= 1 << slot; 771 772 /* 773 * Stuff request onto busy list 774 */ 775 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 776 777 err = blockif_flush(p->bctx, breq); 778 assert(err == 0); 779 } 780 781 static inline void 782 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 783 void *buf, int size) 784 { 785 struct ahci_cmd_hdr *hdr; 786 struct ahci_prdt_entry *prdt; 787 void *to; 788 int i, len; 789 790 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 791 len = size; 792 to = buf; 793 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 794 for (i = 0; i < hdr->prdtl && len; i++) { 795 uint8_t *ptr; 796 uint32_t dbcsz; 797 int sublen; 798 799 dbcsz = (prdt->dbc & DBCMASK) + 1; 800 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 801 sublen = MIN(len, dbcsz); 802 memcpy(to, ptr, sublen); 803 len -= sublen; 804 to += sublen; 805 prdt++; 806 } 807 } 808 809 static void 810 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 811 { 812 struct ahci_ioreq *aior; 813 struct blockif_req *breq; 814 uint8_t *entry; 815 uint64_t elba; 816 uint32_t len, elen; 817 int err, first, ncq; 818 uint8_t buf[512]; 819 820 first = (done == 0); 821 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) { 822 len = (uint16_t)cfis[13] << 8 | cfis[12]; 823 len *= 512; 824 ncq = 0; 825 } else { /* ATA_SEND_FPDMA_QUEUED */ 826 len = (uint16_t)cfis[11] << 8 | cfis[3]; 827 len *= 512; 828 ncq = 1; 829 } 830 read_prdt(p, slot, cfis, buf, sizeof(buf)); 831 832 next: 833 entry = &buf[done]; 834 elba = ((uint64_t)entry[5] << 40) | 835 ((uint64_t)entry[4] << 32) | 836 ((uint64_t)entry[3] << 24) | 837 ((uint64_t)entry[2] << 16) | 838 ((uint64_t)entry[1] << 8) | 839 entry[0]; 840 elen = (uint16_t)entry[7] << 8 | entry[6]; 841 done += 8; 842 if (elen == 0) { 843 if (done >= len) { 844 if (ncq) { 845 if (first) 846 ahci_write_fis_d2h_ncq(p, slot); 847 ahci_write_fis_sdb(p, slot, cfis, 848 ATA_S_READY | ATA_S_DSC); 849 } else { 850 ahci_write_fis_d2h(p, slot, cfis, 851 ATA_S_READY | ATA_S_DSC); 852 } 853 p->pending &= ~(1 << slot); 854 ahci_check_stopped(p); 855 if (!first) 856 ahci_handle_port(p); 857 return; 858 } 859 goto next; 860 } 861 862 /* 863 * Pull request off free list 864 */ 865 aior = STAILQ_FIRST(&p->iofhd); 866 assert(aior != NULL); 867 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 868 aior->cfis = cfis; 869 aior->slot = slot; 870 aior->len = len; 871 aior->done = done; 872 aior->more = (len != done); 873 874 breq = &aior->io_req; 875 breq->br_offset = elba * blockif_sectsz(p->bctx); 876 breq->br_resid = elen * blockif_sectsz(p->bctx); 877 878 /* 879 * Mark this command in-flight. 880 */ 881 p->pending |= 1 << slot; 882 883 /* 884 * Stuff request onto busy list 885 */ 886 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 887 888 if (ncq && first) 889 ahci_write_fis_d2h_ncq(p, slot); 890 891 err = blockif_delete(p->bctx, breq); 892 assert(err == 0); 893 } 894 895 static inline void 896 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 897 void *buf, int size) 898 { 899 struct ahci_cmd_hdr *hdr; 900 struct ahci_prdt_entry *prdt; 901 void *from; 902 int i, len; 903 904 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 905 len = size; 906 from = buf; 907 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 908 for (i = 0; i < hdr->prdtl && len; i++) { 909 uint8_t *ptr; 910 uint32_t dbcsz; 911 int sublen; 912 913 dbcsz = (prdt->dbc & DBCMASK) + 1; 914 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 915 sublen = MIN(len, dbcsz); 916 memcpy(ptr, from, sublen); 917 len -= sublen; 918 from += sublen; 919 prdt++; 920 } 921 hdr->prdbc = size - len; 922 } 923 924 static void 925 ahci_checksum(uint8_t *buf, int size) 926 { 927 int i; 928 uint8_t sum = 0; 929 930 for (i = 0; i < size - 1; i++) 931 sum += buf[i]; 932 buf[size - 1] = 0x100 - sum; 933 } 934 935 static void 936 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis) 937 { 938 struct ahci_cmd_hdr *hdr; 939 uint32_t buf[128]; 940 uint8_t *buf8 = (uint8_t *)buf; 941 uint16_t *buf16 = (uint16_t *)buf; 942 943 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 944 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 || 945 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) { 946 ahci_write_fis_d2h(p, slot, cfis, 947 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 948 return; 949 } 950 951 memset(buf, 0, sizeof(buf)); 952 if (cfis[4] == 0x00) { /* Log directory */ 953 buf16[0x00] = 1; /* Version -- 1 */ 954 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */ 955 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */ 956 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */ 957 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis)); 958 ahci_checksum(buf8, sizeof(buf)); 959 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */ 960 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) { 961 buf[0x00] = 1; /* SFQ DSM supported */ 962 buf[0x01] = 1; /* SFQ DSM TRIM supported */ 963 } 964 } else { 965 ahci_write_fis_d2h(p, slot, cfis, 966 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 967 return; 968 } 969 970 if (cfis[2] == ATA_READ_LOG_EXT) 971 ahci_write_fis_piosetup(p); 972 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 973 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 974 } 975 976 static void 977 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis) 978 { 979 struct ahci_cmd_hdr *hdr; 980 981 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 982 if (p->atapi || hdr->prdtl == 0) { 983 ahci_write_fis_d2h(p, slot, cfis, 984 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 985 } else { 986 uint16_t buf[256]; 987 uint64_t sectors; 988 int sectsz, psectsz, psectoff, candelete, ro; 989 uint16_t cyl; 990 uint8_t sech, heads; 991 992 ro = blockif_is_ro(p->bctx); 993 candelete = blockif_candelete(p->bctx); 994 sectsz = blockif_sectsz(p->bctx); 995 sectors = blockif_size(p->bctx) / sectsz; 996 blockif_chs(p->bctx, &cyl, &heads, &sech); 997 blockif_psectsz(p->bctx, &psectsz, &psectoff); 998 memset(buf, 0, sizeof(buf)); 999 buf[0] = 0x0040; 1000 buf[1] = cyl; 1001 buf[3] = heads; 1002 buf[6] = sech; 1003 ata_string((uint8_t *)(buf+10), p->ident, 20); 1004 ata_string((uint8_t *)(buf+23), "001", 8); 1005 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40); 1006 buf[47] = (0x8000 | 128); 1007 buf[48] = 0; 1008 buf[49] = (1 << 8 | 1 << 9 | 1 << 11); 1009 buf[50] = (1 << 14); 1010 buf[53] = (1 << 1 | 1 << 2); 1011 if (p->mult_sectors) 1012 buf[59] = (0x100 | p->mult_sectors); 1013 if (sectors <= 0x0fffffff) { 1014 buf[60] = sectors; 1015 buf[61] = (sectors >> 16); 1016 } else { 1017 buf[60] = 0xffff; 1018 buf[61] = 0x0fff; 1019 } 1020 buf[63] = 0x7; 1021 if (p->xfermode & ATA_WDMA0) 1022 buf[63] |= (1 << ((p->xfermode & 7) + 8)); 1023 buf[64] = 0x3; 1024 buf[65] = 120; 1025 buf[66] = 120; 1026 buf[67] = 120; 1027 buf[68] = 120; 1028 buf[69] = 0; 1029 buf[75] = 31; 1030 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 | 1031 ATA_SUPPORT_NCQ); 1032 buf[77] = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED | 1033 (p->ssts & ATA_SS_SPD_MASK) >> 3); 1034 buf[80] = 0x3f0; 1035 buf[81] = 0x28; 1036 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE| 1037 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP); 1038 buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE | 1039 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14); 1040 buf[84] = (1 << 14); 1041 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE| 1042 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP); 1043 buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE | 1044 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15); 1045 buf[87] = (1 << 14); 1046 buf[88] = 0x7f; 1047 if (p->xfermode & ATA_UDMA0) 1048 buf[88] |= (1 << ((p->xfermode & 7) + 8)); 1049 buf[100] = sectors; 1050 buf[101] = (sectors >> 16); 1051 buf[102] = (sectors >> 32); 1052 buf[103] = (sectors >> 48); 1053 if (candelete && !ro) { 1054 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT; 1055 buf[105] = 1; 1056 buf[169] = ATA_SUPPORT_DSM_TRIM; 1057 } 1058 buf[106] = 0x4000; 1059 buf[209] = 0x4000; 1060 if (psectsz > sectsz) { 1061 buf[106] |= 0x2000; 1062 buf[106] |= ffsl(psectsz / sectsz) - 1; 1063 buf[209] |= (psectoff / sectsz); 1064 } 1065 if (sectsz > 512) { 1066 buf[106] |= 0x1000; 1067 buf[117] = sectsz / 2; 1068 buf[118] = ((sectsz / 2) >> 16); 1069 } 1070 buf[119] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14); 1071 buf[120] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14); 1072 buf[222] = 0x1020; 1073 buf[255] = 0x00a5; 1074 ahci_checksum((uint8_t *)buf, sizeof(buf)); 1075 ahci_write_fis_piosetup(p); 1076 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 1077 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 1078 } 1079 } 1080 1081 static void 1082 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis) 1083 { 1084 if (!p->atapi) { 1085 ahci_write_fis_d2h(p, slot, cfis, 1086 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1087 } else { 1088 uint16_t buf[256]; 1089 1090 memset(buf, 0, sizeof(buf)); 1091 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5); 1092 ata_string((uint8_t *)(buf+10), p->ident, 20); 1093 ata_string((uint8_t *)(buf+23), "001", 8); 1094 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40); 1095 buf[49] = (1 << 9 | 1 << 8); 1096 buf[50] = (1 << 14 | 1); 1097 buf[53] = (1 << 2 | 1 << 1); 1098 buf[62] = 0x3f; 1099 buf[63] = 7; 1100 if (p->xfermode & ATA_WDMA0) 1101 buf[63] |= (1 << ((p->xfermode & 7) + 8)); 1102 buf[64] = 3; 1103 buf[65] = 120; 1104 buf[66] = 120; 1105 buf[67] = 120; 1106 buf[68] = 120; 1107 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3); 1108 buf[77] = ((p->ssts & ATA_SS_SPD_MASK) >> 3); 1109 buf[78] = (1 << 5); 1110 buf[80] = 0x3f0; 1111 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET | 1112 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP); 1113 buf[83] = (1 << 14); 1114 buf[84] = (1 << 14); 1115 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET | 1116 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP); 1117 buf[87] = (1 << 14); 1118 buf[88] = 0x7f; 1119 if (p->xfermode & ATA_UDMA0) 1120 buf[88] |= (1 << ((p->xfermode & 7) + 8)); 1121 buf[222] = 0x1020; 1122 buf[255] = 0x00a5; 1123 ahci_checksum((uint8_t *)buf, sizeof(buf)); 1124 ahci_write_fis_piosetup(p); 1125 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 1126 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 1127 } 1128 } 1129 1130 static void 1131 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis) 1132 { 1133 uint8_t buf[36]; 1134 uint8_t *acmd; 1135 int len; 1136 uint32_t tfd; 1137 1138 acmd = cfis + 0x40; 1139 1140 if (acmd[1] & 1) { /* VPD */ 1141 if (acmd[2] == 0) { /* Supported VPD pages */ 1142 buf[0] = 0x05; 1143 buf[1] = 0; 1144 buf[2] = 0; 1145 buf[3] = 1; 1146 buf[4] = 0; 1147 len = 4 + buf[3]; 1148 } else { 1149 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1150 p->asc = 0x24; 1151 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1152 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1153 ahci_write_fis_d2h(p, slot, cfis, tfd); 1154 return; 1155 } 1156 } else { 1157 buf[0] = 0x05; 1158 buf[1] = 0x80; 1159 buf[2] = 0x00; 1160 buf[3] = 0x21; 1161 buf[4] = 31; 1162 buf[5] = 0; 1163 buf[6] = 0; 1164 buf[7] = 0; 1165 atapi_string(buf + 8, "BHYVE", 8); 1166 atapi_string(buf + 16, "BHYVE DVD-ROM", 16); 1167 atapi_string(buf + 32, "001", 4); 1168 len = sizeof(buf); 1169 } 1170 1171 if (len > acmd[4]) 1172 len = acmd[4]; 1173 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1174 write_prdt(p, slot, cfis, buf, len); 1175 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1176 } 1177 1178 static void 1179 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis) 1180 { 1181 uint8_t buf[8]; 1182 uint64_t sectors; 1183 1184 sectors = blockif_size(p->bctx) / 2048; 1185 be32enc(buf, sectors - 1); 1186 be32enc(buf + 4, 2048); 1187 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1188 write_prdt(p, slot, cfis, buf, sizeof(buf)); 1189 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1190 } 1191 1192 static void 1193 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis) 1194 { 1195 uint8_t *acmd; 1196 uint8_t format; 1197 int len; 1198 1199 acmd = cfis + 0x40; 1200 1201 len = be16dec(acmd + 7); 1202 format = acmd[9] >> 6; 1203 switch (format) { 1204 case 0: 1205 { 1206 int msf, size; 1207 uint64_t sectors; 1208 uint8_t start_track, buf[20], *bp; 1209 1210 msf = (acmd[1] >> 1) & 1; 1211 start_track = acmd[6]; 1212 if (start_track > 1 && start_track != 0xaa) { 1213 uint32_t tfd; 1214 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1215 p->asc = 0x24; 1216 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1217 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1218 ahci_write_fis_d2h(p, slot, cfis, tfd); 1219 return; 1220 } 1221 bp = buf + 2; 1222 *bp++ = 1; 1223 *bp++ = 1; 1224 if (start_track <= 1) { 1225 *bp++ = 0; 1226 *bp++ = 0x14; 1227 *bp++ = 1; 1228 *bp++ = 0; 1229 if (msf) { 1230 *bp++ = 0; 1231 lba_to_msf(bp, 0); 1232 bp += 3; 1233 } else { 1234 *bp++ = 0; 1235 *bp++ = 0; 1236 *bp++ = 0; 1237 *bp++ = 0; 1238 } 1239 } 1240 *bp++ = 0; 1241 *bp++ = 0x14; 1242 *bp++ = 0xaa; 1243 *bp++ = 0; 1244 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1245 sectors >>= 2; 1246 if (msf) { 1247 *bp++ = 0; 1248 lba_to_msf(bp, sectors); 1249 bp += 3; 1250 } else { 1251 be32enc(bp, sectors); 1252 bp += 4; 1253 } 1254 size = bp - buf; 1255 be16enc(buf, size - 2); 1256 if (len > size) 1257 len = size; 1258 write_prdt(p, slot, cfis, buf, len); 1259 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1260 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1261 break; 1262 } 1263 case 1: 1264 { 1265 uint8_t buf[12]; 1266 1267 memset(buf, 0, sizeof(buf)); 1268 buf[1] = 0xa; 1269 buf[2] = 0x1; 1270 buf[3] = 0x1; 1271 if (len > sizeof(buf)) 1272 len = sizeof(buf); 1273 write_prdt(p, slot, cfis, buf, len); 1274 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1275 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1276 break; 1277 } 1278 case 2: 1279 { 1280 int msf, size; 1281 uint64_t sectors; 1282 uint8_t *bp, buf[50]; 1283 1284 msf = (acmd[1] >> 1) & 1; 1285 bp = buf + 2; 1286 *bp++ = 1; 1287 *bp++ = 1; 1288 1289 *bp++ = 1; 1290 *bp++ = 0x14; 1291 *bp++ = 0; 1292 *bp++ = 0xa0; 1293 *bp++ = 0; 1294 *bp++ = 0; 1295 *bp++ = 0; 1296 *bp++ = 0; 1297 *bp++ = 1; 1298 *bp++ = 0; 1299 *bp++ = 0; 1300 1301 *bp++ = 1; 1302 *bp++ = 0x14; 1303 *bp++ = 0; 1304 *bp++ = 0xa1; 1305 *bp++ = 0; 1306 *bp++ = 0; 1307 *bp++ = 0; 1308 *bp++ = 0; 1309 *bp++ = 1; 1310 *bp++ = 0; 1311 *bp++ = 0; 1312 1313 *bp++ = 1; 1314 *bp++ = 0x14; 1315 *bp++ = 0; 1316 *bp++ = 0xa2; 1317 *bp++ = 0; 1318 *bp++ = 0; 1319 *bp++ = 0; 1320 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1321 sectors >>= 2; 1322 if (msf) { 1323 *bp++ = 0; 1324 lba_to_msf(bp, sectors); 1325 bp += 3; 1326 } else { 1327 be32enc(bp, sectors); 1328 bp += 4; 1329 } 1330 1331 *bp++ = 1; 1332 *bp++ = 0x14; 1333 *bp++ = 0; 1334 *bp++ = 1; 1335 *bp++ = 0; 1336 *bp++ = 0; 1337 *bp++ = 0; 1338 if (msf) { 1339 *bp++ = 0; 1340 lba_to_msf(bp, 0); 1341 bp += 3; 1342 } else { 1343 *bp++ = 0; 1344 *bp++ = 0; 1345 *bp++ = 0; 1346 *bp++ = 0; 1347 } 1348 1349 size = bp - buf; 1350 be16enc(buf, size - 2); 1351 if (len > size) 1352 len = size; 1353 write_prdt(p, slot, cfis, buf, len); 1354 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1355 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1356 break; 1357 } 1358 default: 1359 { 1360 uint32_t tfd; 1361 1362 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1363 p->asc = 0x24; 1364 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1365 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1366 ahci_write_fis_d2h(p, slot, cfis, tfd); 1367 break; 1368 } 1369 } 1370 } 1371 1372 static void 1373 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis) 1374 { 1375 uint8_t buf[16]; 1376 1377 memset(buf, 0, sizeof(buf)); 1378 buf[3] = 8; 1379 1380 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1381 write_prdt(p, slot, cfis, buf, sizeof(buf)); 1382 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1383 } 1384 1385 static void 1386 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 1387 { 1388 struct ahci_ioreq *aior; 1389 struct ahci_cmd_hdr *hdr; 1390 struct ahci_prdt_entry *prdt; 1391 struct blockif_req *breq; 1392 uint8_t *acmd; 1393 uint64_t lba; 1394 uint32_t len; 1395 int err; 1396 1397 acmd = cfis + 0x40; 1398 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1399 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1400 1401 lba = be32dec(acmd + 2); 1402 if (acmd[0] == READ_10) 1403 len = be16dec(acmd + 7); 1404 else 1405 len = be32dec(acmd + 6); 1406 if (len == 0) { 1407 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1408 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1409 } 1410 lba *= 2048; 1411 len *= 2048; 1412 1413 /* 1414 * Pull request off free list 1415 */ 1416 aior = STAILQ_FIRST(&p->iofhd); 1417 assert(aior != NULL); 1418 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 1419 aior->cfis = cfis; 1420 aior->slot = slot; 1421 aior->len = len; 1422 aior->done = done; 1423 breq = &aior->io_req; 1424 breq->br_offset = lba + done; 1425 ahci_build_iov(p, aior, prdt, hdr->prdtl); 1426 1427 /* Mark this command in-flight. */ 1428 p->pending |= 1 << slot; 1429 1430 /* Stuff request onto busy list. */ 1431 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 1432 1433 err = blockif_read(p->bctx, breq); 1434 assert(err == 0); 1435 } 1436 1437 static void 1438 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1439 { 1440 uint8_t buf[64]; 1441 uint8_t *acmd; 1442 int len; 1443 1444 acmd = cfis + 0x40; 1445 len = acmd[4]; 1446 if (len > sizeof(buf)) 1447 len = sizeof(buf); 1448 memset(buf, 0, len); 1449 buf[0] = 0x70 | (1 << 7); 1450 buf[2] = p->sense_key; 1451 buf[7] = 10; 1452 buf[12] = p->asc; 1453 write_prdt(p, slot, cfis, buf, len); 1454 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1455 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1456 } 1457 1458 static void 1459 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis) 1460 { 1461 uint8_t *acmd = cfis + 0x40; 1462 uint32_t tfd; 1463 1464 switch (acmd[4] & 3) { 1465 case 0: 1466 case 1: 1467 case 3: 1468 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1469 tfd = ATA_S_READY | ATA_S_DSC; 1470 break; 1471 case 2: 1472 /* TODO eject media */ 1473 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1474 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1475 p->asc = 0x53; 1476 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1477 break; 1478 } 1479 ahci_write_fis_d2h(p, slot, cfis, tfd); 1480 } 1481 1482 static void 1483 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1484 { 1485 uint8_t *acmd; 1486 uint32_t tfd = 0; 1487 uint8_t pc, code; 1488 int len; 1489 1490 acmd = cfis + 0x40; 1491 len = be16dec(acmd + 7); 1492 pc = acmd[2] >> 6; 1493 code = acmd[2] & 0x3f; 1494 1495 switch (pc) { 1496 case 0: 1497 switch (code) { 1498 case MODEPAGE_RW_ERROR_RECOVERY: 1499 { 1500 uint8_t buf[16]; 1501 1502 if (len > sizeof(buf)) 1503 len = sizeof(buf); 1504 1505 memset(buf, 0, sizeof(buf)); 1506 be16enc(buf, 16 - 2); 1507 buf[2] = 0x70; 1508 buf[8] = 0x01; 1509 buf[9] = 16 - 10; 1510 buf[11] = 0x05; 1511 write_prdt(p, slot, cfis, buf, len); 1512 tfd = ATA_S_READY | ATA_S_DSC; 1513 break; 1514 } 1515 case MODEPAGE_CD_CAPABILITIES: 1516 { 1517 uint8_t buf[30]; 1518 1519 if (len > sizeof(buf)) 1520 len = sizeof(buf); 1521 1522 memset(buf, 0, sizeof(buf)); 1523 be16enc(buf, 30 - 2); 1524 buf[2] = 0x70; 1525 buf[8] = 0x2A; 1526 buf[9] = 30 - 10; 1527 buf[10] = 0x08; 1528 buf[12] = 0x71; 1529 be16enc(&buf[18], 2); 1530 be16enc(&buf[20], 512); 1531 write_prdt(p, slot, cfis, buf, len); 1532 tfd = ATA_S_READY | ATA_S_DSC; 1533 break; 1534 } 1535 default: 1536 goto error; 1537 break; 1538 } 1539 break; 1540 case 3: 1541 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1542 p->asc = 0x39; 1543 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1544 break; 1545 error: 1546 case 1: 1547 case 2: 1548 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1549 p->asc = 0x24; 1550 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1551 break; 1552 } 1553 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1554 ahci_write_fis_d2h(p, slot, cfis, tfd); 1555 } 1556 1557 static void 1558 atapi_get_event_status_notification(struct ahci_port *p, int slot, 1559 uint8_t *cfis) 1560 { 1561 uint8_t *acmd; 1562 uint32_t tfd; 1563 1564 acmd = cfis + 0x40; 1565 1566 /* we don't support asynchronous operation */ 1567 if (!(acmd[1] & 1)) { 1568 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1569 p->asc = 0x24; 1570 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1571 } else { 1572 uint8_t buf[8]; 1573 int len; 1574 1575 len = be16dec(acmd + 7); 1576 if (len > sizeof(buf)) 1577 len = sizeof(buf); 1578 1579 memset(buf, 0, sizeof(buf)); 1580 be16enc(buf, 8 - 2); 1581 buf[2] = 0x04; 1582 buf[3] = 0x10; 1583 buf[5] = 0x02; 1584 write_prdt(p, slot, cfis, buf, len); 1585 tfd = ATA_S_READY | ATA_S_DSC; 1586 } 1587 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1588 ahci_write_fis_d2h(p, slot, cfis, tfd); 1589 } 1590 1591 static void 1592 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1593 { 1594 uint8_t *acmd; 1595 1596 acmd = cfis + 0x40; 1597 1598 #ifdef AHCI_DEBUG 1599 { 1600 int i; 1601 DPRINTF("ACMD:"); 1602 for (i = 0; i < 16; i++) 1603 DPRINTF("%02x ", acmd[i]); 1604 DPRINTF(""); 1605 } 1606 #endif 1607 1608 switch (acmd[0]) { 1609 case TEST_UNIT_READY: 1610 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1611 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1612 break; 1613 case INQUIRY: 1614 atapi_inquiry(p, slot, cfis); 1615 break; 1616 case READ_CAPACITY: 1617 atapi_read_capacity(p, slot, cfis); 1618 break; 1619 case PREVENT_ALLOW: 1620 /* TODO */ 1621 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1622 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1623 break; 1624 case READ_TOC: 1625 atapi_read_toc(p, slot, cfis); 1626 break; 1627 case REPORT_LUNS: 1628 atapi_report_luns(p, slot, cfis); 1629 break; 1630 case READ_10: 1631 case READ_12: 1632 atapi_read(p, slot, cfis, 0); 1633 break; 1634 case REQUEST_SENSE: 1635 atapi_request_sense(p, slot, cfis); 1636 break; 1637 case START_STOP_UNIT: 1638 atapi_start_stop_unit(p, slot, cfis); 1639 break; 1640 case MODE_SENSE_10: 1641 atapi_mode_sense(p, slot, cfis); 1642 break; 1643 case GET_EVENT_STATUS_NOTIFICATION: 1644 atapi_get_event_status_notification(p, slot, cfis); 1645 break; 1646 default: 1647 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1648 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1649 p->asc = 0x20; 1650 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) | 1651 ATA_S_READY | ATA_S_ERROR); 1652 break; 1653 } 1654 } 1655 1656 static void 1657 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1658 { 1659 1660 p->tfd |= ATA_S_BUSY; 1661 switch (cfis[2]) { 1662 case ATA_ATA_IDENTIFY: 1663 handle_identify(p, slot, cfis); 1664 break; 1665 case ATA_SETFEATURES: 1666 { 1667 switch (cfis[3]) { 1668 case ATA_SF_ENAB_SATA_SF: 1669 switch (cfis[12]) { 1670 case ATA_SATA_SF_AN: 1671 p->tfd = ATA_S_DSC | ATA_S_READY; 1672 break; 1673 default: 1674 p->tfd = ATA_S_ERROR | ATA_S_READY; 1675 p->tfd |= (ATA_ERROR_ABORT << 8); 1676 break; 1677 } 1678 break; 1679 case ATA_SF_ENAB_WCACHE: 1680 case ATA_SF_DIS_WCACHE: 1681 case ATA_SF_ENAB_RCACHE: 1682 case ATA_SF_DIS_RCACHE: 1683 p->tfd = ATA_S_DSC | ATA_S_READY; 1684 break; 1685 case ATA_SF_SETXFER: 1686 { 1687 switch (cfis[12] & 0xf8) { 1688 case ATA_PIO: 1689 case ATA_PIO0: 1690 break; 1691 case ATA_WDMA0: 1692 case ATA_UDMA0: 1693 p->xfermode = (cfis[12] & 0x7); 1694 break; 1695 } 1696 p->tfd = ATA_S_DSC | ATA_S_READY; 1697 break; 1698 } 1699 default: 1700 p->tfd = ATA_S_ERROR | ATA_S_READY; 1701 p->tfd |= (ATA_ERROR_ABORT << 8); 1702 break; 1703 } 1704 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1705 break; 1706 } 1707 case ATA_SET_MULTI: 1708 if (cfis[12] != 0 && 1709 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) { 1710 p->tfd = ATA_S_ERROR | ATA_S_READY; 1711 p->tfd |= (ATA_ERROR_ABORT << 8); 1712 } else { 1713 p->mult_sectors = cfis[12]; 1714 p->tfd = ATA_S_DSC | ATA_S_READY; 1715 } 1716 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1717 break; 1718 case ATA_READ: 1719 case ATA_WRITE: 1720 case ATA_READ48: 1721 case ATA_WRITE48: 1722 case ATA_READ_MUL: 1723 case ATA_WRITE_MUL: 1724 case ATA_READ_MUL48: 1725 case ATA_WRITE_MUL48: 1726 case ATA_READ_DMA: 1727 case ATA_WRITE_DMA: 1728 case ATA_READ_DMA48: 1729 case ATA_WRITE_DMA48: 1730 case ATA_READ_FPDMA_QUEUED: 1731 case ATA_WRITE_FPDMA_QUEUED: 1732 ahci_handle_rw(p, slot, cfis, 0); 1733 break; 1734 case ATA_FLUSHCACHE: 1735 case ATA_FLUSHCACHE48: 1736 ahci_handle_flush(p, slot, cfis); 1737 break; 1738 case ATA_DATA_SET_MANAGEMENT: 1739 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM && 1740 cfis[13] == 0 && cfis[12] == 1) { 1741 ahci_handle_dsm_trim(p, slot, cfis, 0); 1742 break; 1743 } 1744 ahci_write_fis_d2h(p, slot, cfis, 1745 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1746 break; 1747 case ATA_SEND_FPDMA_QUEUED: 1748 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM && 1749 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM && 1750 cfis[11] == 0 && cfis[3] == 1) { 1751 ahci_handle_dsm_trim(p, slot, cfis, 0); 1752 break; 1753 } 1754 ahci_write_fis_d2h(p, slot, cfis, 1755 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1756 break; 1757 case ATA_READ_LOG_EXT: 1758 case ATA_READ_LOG_DMA_EXT: 1759 ahci_handle_read_log(p, slot, cfis); 1760 break; 1761 case ATA_SECURITY_FREEZE_LOCK: 1762 case ATA_SMART_CMD: 1763 case ATA_NOP: 1764 ahci_write_fis_d2h(p, slot, cfis, 1765 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1766 break; 1767 case ATA_CHECK_POWER_MODE: 1768 cfis[12] = 0xff; /* always on */ 1769 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1770 break; 1771 case ATA_STANDBY_CMD: 1772 case ATA_STANDBY_IMMEDIATE: 1773 case ATA_IDLE_CMD: 1774 case ATA_IDLE_IMMEDIATE: 1775 case ATA_SLEEP: 1776 case ATA_READ_VERIFY: 1777 case ATA_READ_VERIFY48: 1778 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1779 break; 1780 case ATA_ATAPI_IDENTIFY: 1781 handle_atapi_identify(p, slot, cfis); 1782 break; 1783 case ATA_PACKET_CMD: 1784 if (!p->atapi) { 1785 ahci_write_fis_d2h(p, slot, cfis, 1786 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1787 } else 1788 handle_packet_cmd(p, slot, cfis); 1789 break; 1790 default: 1791 WPRINTF("Unsupported cmd:%02x", cfis[2]); 1792 ahci_write_fis_d2h(p, slot, cfis, 1793 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1794 break; 1795 } 1796 } 1797 1798 static void 1799 ahci_handle_slot(struct ahci_port *p, int slot) 1800 { 1801 struct ahci_cmd_hdr *hdr; 1802 #ifdef AHCI_DEBUG 1803 struct ahci_prdt_entry *prdt; 1804 #endif 1805 struct pci_ahci_softc *sc; 1806 uint8_t *cfis; 1807 #ifdef AHCI_DEBUG 1808 int cfl, i; 1809 #endif 1810 1811 sc = p->pr_sc; 1812 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1813 #ifdef AHCI_DEBUG 1814 cfl = (hdr->flags & 0x1f) * 4; 1815 #endif 1816 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba, 1817 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); 1818 #ifdef AHCI_DEBUG 1819 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1820 1821 DPRINTF("cfis:"); 1822 for (i = 0; i < cfl; i++) { 1823 if (i % 10 == 0) 1824 DPRINTF(""); 1825 DPRINTF("%02x ", cfis[i]); 1826 } 1827 DPRINTF(""); 1828 1829 for (i = 0; i < hdr->prdtl; i++) { 1830 DPRINTF("%d@%08"PRIx64"", prdt->dbc & 0x3fffff, prdt->dba); 1831 prdt++; 1832 } 1833 #endif 1834 1835 if (cfis[0] != FIS_TYPE_REGH2D) { 1836 WPRINTF("Not a H2D FIS:%02x", cfis[0]); 1837 return; 1838 } 1839 1840 if (cfis[1] & 0x80) { 1841 ahci_handle_cmd(p, slot, cfis); 1842 } else { 1843 if (cfis[15] & (1 << 2)) 1844 p->reset = 1; 1845 else if (p->reset) { 1846 p->reset = 0; 1847 ahci_port_reset(p); 1848 } 1849 p->ci &= ~(1 << slot); 1850 } 1851 } 1852 1853 static void 1854 ahci_handle_port(struct ahci_port *p) 1855 { 1856 1857 if (!(p->cmd & AHCI_P_CMD_ST)) 1858 return; 1859 1860 /* 1861 * Search for any new commands to issue ignoring those that 1862 * are already in-flight. Stop if device is busy or in error. 1863 */ 1864 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) { 1865 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0) 1866 break; 1867 if (p->waitforclear) 1868 break; 1869 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) { 1870 p->cmd &= ~AHCI_P_CMD_CCS_MASK; 1871 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT; 1872 ahci_handle_slot(p, p->ccs); 1873 } 1874 } 1875 } 1876 1877 /* 1878 * blockif callback routine - this runs in the context of the blockif 1879 * i/o thread, so the mutex needs to be acquired. 1880 */ 1881 static void 1882 ata_ioreq_cb(struct blockif_req *br, int err) 1883 { 1884 struct ahci_cmd_hdr *hdr; 1885 struct ahci_ioreq *aior; 1886 struct ahci_port *p; 1887 struct pci_ahci_softc *sc; 1888 uint32_t tfd; 1889 uint8_t *cfis; 1890 int slot, ncq, dsm; 1891 1892 DPRINTF("%s %d", __func__, err); 1893 1894 ncq = dsm = 0; 1895 aior = br->br_param; 1896 p = aior->io_pr; 1897 cfis = aior->cfis; 1898 slot = aior->slot; 1899 sc = p->pr_sc; 1900 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1901 1902 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 1903 cfis[2] == ATA_READ_FPDMA_QUEUED || 1904 cfis[2] == ATA_SEND_FPDMA_QUEUED) 1905 ncq = 1; 1906 if (cfis[2] == ATA_DATA_SET_MANAGEMENT || 1907 (cfis[2] == ATA_SEND_FPDMA_QUEUED && 1908 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM)) 1909 dsm = 1; 1910 1911 pthread_mutex_lock(&sc->mtx); 1912 1913 /* 1914 * Delete the blockif request from the busy list 1915 */ 1916 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1917 1918 /* 1919 * Move the blockif request back to the free list 1920 */ 1921 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1922 1923 if (!err) 1924 hdr->prdbc = aior->done; 1925 1926 if (!err && aior->more) { 1927 if (dsm) 1928 ahci_handle_dsm_trim(p, slot, cfis, aior->done); 1929 else 1930 ahci_handle_rw(p, slot, cfis, aior->done); 1931 goto out; 1932 } 1933 1934 if (!err) 1935 tfd = ATA_S_READY | ATA_S_DSC; 1936 else 1937 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1938 if (ncq) 1939 ahci_write_fis_sdb(p, slot, cfis, tfd); 1940 else 1941 ahci_write_fis_d2h(p, slot, cfis, tfd); 1942 1943 /* 1944 * This command is now complete. 1945 */ 1946 p->pending &= ~(1 << slot); 1947 1948 ahci_check_stopped(p); 1949 ahci_handle_port(p); 1950 out: 1951 pthread_mutex_unlock(&sc->mtx); 1952 DPRINTF("%s exit", __func__); 1953 } 1954 1955 static void 1956 atapi_ioreq_cb(struct blockif_req *br, int err) 1957 { 1958 struct ahci_cmd_hdr *hdr; 1959 struct ahci_ioreq *aior; 1960 struct ahci_port *p; 1961 struct pci_ahci_softc *sc; 1962 uint8_t *cfis; 1963 uint32_t tfd; 1964 int slot; 1965 1966 DPRINTF("%s %d", __func__, err); 1967 1968 aior = br->br_param; 1969 p = aior->io_pr; 1970 cfis = aior->cfis; 1971 slot = aior->slot; 1972 sc = p->pr_sc; 1973 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE); 1974 1975 pthread_mutex_lock(&sc->mtx); 1976 1977 /* 1978 * Delete the blockif request from the busy list 1979 */ 1980 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1981 1982 /* 1983 * Move the blockif request back to the free list 1984 */ 1985 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1986 1987 if (!err) 1988 hdr->prdbc = aior->done; 1989 1990 if (!err && aior->more) { 1991 atapi_read(p, slot, cfis, aior->done); 1992 goto out; 1993 } 1994 1995 if (!err) { 1996 tfd = ATA_S_READY | ATA_S_DSC; 1997 } else { 1998 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1999 p->asc = 0x21; 2000 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 2001 } 2002 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 2003 ahci_write_fis_d2h(p, slot, cfis, tfd); 2004 2005 /* 2006 * This command is now complete. 2007 */ 2008 p->pending &= ~(1 << slot); 2009 2010 ahci_check_stopped(p); 2011 ahci_handle_port(p); 2012 out: 2013 pthread_mutex_unlock(&sc->mtx); 2014 DPRINTF("%s exit", __func__); 2015 } 2016 2017 static void 2018 pci_ahci_ioreq_init(struct ahci_port *pr) 2019 { 2020 struct ahci_ioreq *vr; 2021 int i; 2022 2023 pr->ioqsz = blockif_queuesz(pr->bctx); 2024 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq)); 2025 STAILQ_INIT(&pr->iofhd); 2026 2027 /* 2028 * Add all i/o request entries to the free queue 2029 */ 2030 for (i = 0; i < pr->ioqsz; i++) { 2031 vr = &pr->ioreq[i]; 2032 vr->io_pr = pr; 2033 if (!pr->atapi) 2034 vr->io_req.br_callback = ata_ioreq_cb; 2035 else 2036 vr->io_req.br_callback = atapi_ioreq_cb; 2037 vr->io_req.br_param = vr; 2038 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist); 2039 } 2040 2041 TAILQ_INIT(&pr->iobhd); 2042 } 2043 2044 static void 2045 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 2046 { 2047 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 2048 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 2049 struct ahci_port *p = &sc->port[port]; 2050 2051 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"", 2052 port, offset, value); 2053 2054 switch (offset) { 2055 case AHCI_P_CLB: 2056 p->clb = value; 2057 break; 2058 case AHCI_P_CLBU: 2059 p->clbu = value; 2060 break; 2061 case AHCI_P_FB: 2062 p->fb = value; 2063 break; 2064 case AHCI_P_FBU: 2065 p->fbu = value; 2066 break; 2067 case AHCI_P_IS: 2068 p->is &= ~value; 2069 ahci_port_intr(p); 2070 break; 2071 case AHCI_P_IE: 2072 p->ie = value & 0xFDC000FF; 2073 ahci_port_intr(p); 2074 break; 2075 case AHCI_P_CMD: 2076 { 2077 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD | 2078 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE | 2079 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE | 2080 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK); 2081 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD | 2082 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE | 2083 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE | 2084 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value; 2085 2086 if (!(value & AHCI_P_CMD_ST)) { 2087 ahci_port_stop(p); 2088 } else { 2089 uint64_t clb; 2090 2091 p->cmd |= AHCI_P_CMD_CR; 2092 clb = (uint64_t)p->clbu << 32 | p->clb; 2093 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb, 2094 AHCI_CL_SIZE * AHCI_MAX_SLOTS); 2095 } 2096 2097 if (value & AHCI_P_CMD_FRE) { 2098 uint64_t fb; 2099 2100 p->cmd |= AHCI_P_CMD_FR; 2101 fb = (uint64_t)p->fbu << 32 | p->fb; 2102 /* we don't support FBSCP, so rfis size is 256Bytes */ 2103 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256); 2104 } else { 2105 p->cmd &= ~AHCI_P_CMD_FR; 2106 } 2107 2108 if (value & AHCI_P_CMD_CLO) { 2109 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ); 2110 p->cmd &= ~AHCI_P_CMD_CLO; 2111 } 2112 2113 if (value & AHCI_P_CMD_ICC_MASK) { 2114 p->cmd &= ~AHCI_P_CMD_ICC_MASK; 2115 } 2116 2117 ahci_handle_port(p); 2118 break; 2119 } 2120 case AHCI_P_TFD: 2121 case AHCI_P_SIG: 2122 case AHCI_P_SSTS: 2123 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"", offset); 2124 break; 2125 case AHCI_P_SCTL: 2126 p->sctl = value; 2127 if (!(p->cmd & AHCI_P_CMD_ST)) { 2128 if (value & ATA_SC_DET_RESET) 2129 ahci_port_reset(p); 2130 } 2131 break; 2132 case AHCI_P_SERR: 2133 p->serr &= ~value; 2134 break; 2135 case AHCI_P_SACT: 2136 p->sact |= value; 2137 break; 2138 case AHCI_P_CI: 2139 p->ci |= value; 2140 ahci_handle_port(p); 2141 break; 2142 case AHCI_P_SNTF: 2143 case AHCI_P_FBS: 2144 default: 2145 break; 2146 } 2147 } 2148 2149 static void 2150 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 2151 { 2152 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"", 2153 offset, value); 2154 2155 switch (offset) { 2156 case AHCI_CAP: 2157 case AHCI_PI: 2158 case AHCI_VS: 2159 case AHCI_CAP2: 2160 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"", offset); 2161 break; 2162 case AHCI_GHC: 2163 if (value & AHCI_GHC_HR) { 2164 ahci_reset(sc); 2165 break; 2166 } 2167 if (value & AHCI_GHC_IE) 2168 sc->ghc |= AHCI_GHC_IE; 2169 else 2170 sc->ghc &= ~AHCI_GHC_IE; 2171 ahci_generate_intr(sc, 0xffffffff); 2172 break; 2173 case AHCI_IS: 2174 sc->is &= ~value; 2175 ahci_generate_intr(sc, value); 2176 break; 2177 default: 2178 break; 2179 } 2180 } 2181 2182 static void 2183 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 2184 int baridx, uint64_t offset, int size, uint64_t value) 2185 { 2186 struct pci_ahci_softc *sc = pi->pi_arg; 2187 2188 assert(baridx == 5); 2189 assert((offset % 4) == 0 && size == 4); 2190 2191 pthread_mutex_lock(&sc->mtx); 2192 2193 if (offset < AHCI_OFFSET) 2194 pci_ahci_host_write(sc, offset, value); 2195 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 2196 pci_ahci_port_write(sc, offset, value); 2197 else 2198 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"", offset); 2199 2200 pthread_mutex_unlock(&sc->mtx); 2201 } 2202 2203 static uint64_t 2204 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset) 2205 { 2206 uint32_t value; 2207 2208 switch (offset) { 2209 case AHCI_CAP: 2210 case AHCI_GHC: 2211 case AHCI_IS: 2212 case AHCI_PI: 2213 case AHCI_VS: 2214 case AHCI_CCCC: 2215 case AHCI_CCCP: 2216 case AHCI_EM_LOC: 2217 case AHCI_EM_CTL: 2218 case AHCI_CAP2: 2219 { 2220 uint32_t *p = &sc->cap; 2221 p += (offset - AHCI_CAP) / sizeof(uint32_t); 2222 value = *p; 2223 break; 2224 } 2225 default: 2226 value = 0; 2227 break; 2228 } 2229 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x", 2230 offset, value); 2231 2232 return (value); 2233 } 2234 2235 static uint64_t 2236 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset) 2237 { 2238 uint32_t value; 2239 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 2240 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 2241 2242 switch (offset) { 2243 case AHCI_P_CLB: 2244 case AHCI_P_CLBU: 2245 case AHCI_P_FB: 2246 case AHCI_P_FBU: 2247 case AHCI_P_IS: 2248 case AHCI_P_IE: 2249 case AHCI_P_CMD: 2250 case AHCI_P_TFD: 2251 case AHCI_P_SIG: 2252 case AHCI_P_SSTS: 2253 case AHCI_P_SCTL: 2254 case AHCI_P_SERR: 2255 case AHCI_P_SACT: 2256 case AHCI_P_CI: 2257 case AHCI_P_SNTF: 2258 case AHCI_P_FBS: 2259 { 2260 uint32_t *p= &sc->port[port].clb; 2261 p += (offset - AHCI_P_CLB) / sizeof(uint32_t); 2262 value = *p; 2263 break; 2264 } 2265 default: 2266 value = 0; 2267 break; 2268 } 2269 2270 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x", 2271 port, offset, value); 2272 2273 return value; 2274 } 2275 2276 static uint64_t 2277 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2278 uint64_t regoff, int size) 2279 { 2280 struct pci_ahci_softc *sc = pi->pi_arg; 2281 uint64_t offset; 2282 uint32_t value; 2283 2284 assert(baridx == 5); 2285 assert(size == 1 || size == 2 || size == 4); 2286 assert((regoff & (size - 1)) == 0); 2287 2288 pthread_mutex_lock(&sc->mtx); 2289 2290 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */ 2291 if (offset < AHCI_OFFSET) 2292 value = pci_ahci_host_read(sc, offset); 2293 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 2294 value = pci_ahci_port_read(sc, offset); 2295 else { 2296 value = 0; 2297 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"", 2298 regoff); 2299 } 2300 value >>= 8 * (regoff & 0x3); 2301 2302 pthread_mutex_unlock(&sc->mtx); 2303 2304 return (value); 2305 } 2306 2307 static int 2308 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi) 2309 { 2310 char bident[sizeof("XX:XX:XX")]; 2311 struct blockif_ctxt *bctxt; 2312 struct pci_ahci_softc *sc; 2313 int ret, slots, p; 2314 MD5_CTX mdctx; 2315 u_char digest[16]; 2316 char *next, *next2; 2317 2318 ret = 0; 2319 2320 #ifdef AHCI_DEBUG 2321 dbg = fopen("/tmp/log", "w+"); 2322 #endif 2323 2324 sc = calloc(1, sizeof(struct pci_ahci_softc)); 2325 pi->pi_arg = sc; 2326 sc->asc_pi = pi; 2327 pthread_mutex_init(&sc->mtx, NULL); 2328 sc->ports = 0; 2329 sc->pi = 0; 2330 slots = 32; 2331 2332 for (p = 0; p < MAX_PORTS && opts != NULL; p++, opts = next) { 2333 /* Identify and cut off type of present port. */ 2334 if (strncmp(opts, "hd:", 3) == 0) { 2335 atapi = 0; 2336 opts += 3; 2337 } else if (strncmp(opts, "cd:", 3) == 0) { 2338 atapi = 1; 2339 opts += 3; 2340 } 2341 2342 /* Find and cut off the next port options. */ 2343 next = strstr(opts, ",hd:"); 2344 next2 = strstr(opts, ",cd:"); 2345 if (next == NULL || (next2 != NULL && next2 < next)) 2346 next = next2; 2347 if (next != NULL) { 2348 next[0] = 0; 2349 next++; 2350 } 2351 2352 if (opts[0] == 0) 2353 continue; 2354 2355 /* 2356 * Attempt to open the backing image. Use the PCI slot/func 2357 * and the port number for the identifier string. 2358 */ 2359 snprintf(bident, sizeof(bident), "%d:%d:%d", pi->pi_slot, 2360 pi->pi_func, p); 2361 bctxt = blockif_open(opts, bident); 2362 if (bctxt == NULL) { 2363 sc->ports = p; 2364 ret = 1; 2365 goto open_fail; 2366 } 2367 sc->port[p].bctx = bctxt; 2368 sc->port[p].pr_sc = sc; 2369 sc->port[p].port = p; 2370 sc->port[p].atapi = atapi; 2371 2372 #ifndef __FreeBSD__ 2373 /* 2374 * Attempt to enable the write cache for this device, as the 2375 * guest will issue FLUSH commands when it requires durability. 2376 * 2377 * Failure here is fine, since an always-sync device will not 2378 * have an impact on correctness. 2379 */ 2380 (void) blockif_set_wce(bctxt, 1); 2381 #endif 2382 2383 /* 2384 * Create an identifier for the backing file. 2385 * Use parts of the md5 sum of the filename 2386 */ 2387 MD5Init(&mdctx); 2388 MD5Update(&mdctx, opts, strlen(opts)); 2389 MD5Final(digest, &mdctx); 2390 snprintf(sc->port[p].ident, AHCI_PORT_IDENT, 2391 "BHYVE-%02X%02X-%02X%02X-%02X%02X", 2392 digest[0], digest[1], digest[2], digest[3], digest[4], 2393 digest[5]); 2394 2395 /* 2396 * Allocate blockif request structures and add them 2397 * to the free list 2398 */ 2399 pci_ahci_ioreq_init(&sc->port[p]); 2400 2401 sc->pi |= (1 << p); 2402 if (sc->port[p].ioqsz < slots) 2403 slots = sc->port[p].ioqsz; 2404 } 2405 sc->ports = p; 2406 2407 /* Intel ICH8 AHCI */ 2408 --slots; 2409 if (sc->ports < DEF_PORTS) 2410 sc->ports = DEF_PORTS; 2411 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF | 2412 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP | 2413 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)| 2414 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC | 2415 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1); 2416 2417 sc->vs = 0x10300; 2418 sc->cap2 = AHCI_CAP2_APST; 2419 ahci_reset(sc); 2420 2421 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821); 2422 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 2423 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE); 2424 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA); 2425 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0); 2426 p = MIN(sc->ports, 16); 2427 p = flsl(p) - ((p & (p - 1)) ? 0 : 1); 2428 pci_emul_add_msicap(pi, 1 << p); 2429 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32, 2430 AHCI_OFFSET + sc->ports * AHCI_STEP); 2431 2432 pci_lintr_request(pi); 2433 2434 open_fail: 2435 if (ret) { 2436 for (p = 0; p < sc->ports; p++) { 2437 if (sc->port[p].bctx != NULL) 2438 blockif_close(sc->port[p].bctx); 2439 } 2440 free(sc); 2441 } 2442 2443 return (ret); 2444 } 2445 2446 static int 2447 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2448 { 2449 2450 return (pci_ahci_init(ctx, pi, opts, 0)); 2451 } 2452 2453 static int 2454 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2455 { 2456 2457 return (pci_ahci_init(ctx, pi, opts, 1)); 2458 } 2459 2460 /* 2461 * Use separate emulation names to distinguish drive and atapi devices 2462 */ 2463 struct pci_devemu pci_de_ahci = { 2464 .pe_emu = "ahci", 2465 .pe_init = pci_ahci_hd_init, 2466 .pe_barwrite = pci_ahci_write, 2467 .pe_barread = pci_ahci_read 2468 }; 2469 PCI_EMUL_SET(pci_de_ahci); 2470 2471 struct pci_devemu pci_de_ahci_hd = { 2472 .pe_emu = "ahci-hd", 2473 .pe_init = pci_ahci_hd_init, 2474 .pe_barwrite = pci_ahci_write, 2475 .pe_barread = pci_ahci_read 2476 }; 2477 PCI_EMUL_SET(pci_de_ahci_hd); 2478 2479 struct pci_devemu pci_de_ahci_cd = { 2480 .pe_emu = "ahci-cd", 2481 .pe_init = pci_ahci_atapi_init, 2482 .pe_barwrite = pci_ahci_write, 2483 .pe_barread = pci_ahci_read 2484 }; 2485 PCI_EMUL_SET(pci_de_ahci_cd); 2486