xref: /illumos-gate/usr/src/uts/common/sys/scsi/adapters/mpi/mpi2_cnfg.h (revision cde3e94d79d833480d2f3ba69f901b918878fd65)
1 /*-
2  * Copyright (c) 2012-2015 LSI Corp.
3  * Copyright (c) 2013-2016 Avago Technologies
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of the author nor the names of any co-contributors
15  *    may be used to endorse or promote products derived from this software
16  *    without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  */
30 
31 /*
32  *  Copyright (c) 2000-2015 LSI Corporation.
33  *  Copyright (c) 2013-2016 Avago Technologies
34  *  All rights reserved.
35  *
36  *
37  *           Name:  mpi2_cnfg.h
38  *          Title:  MPI Configuration messages and pages
39  *  Creation Date:  November 10, 2006
40  *
41  *    mpi2_cnfg.h Version:  02.00.39
42  *
43  *  NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
44  *        prefix are for use only on MPI v2.5 products, and must not be used
45  *        with MPI v2.0 products. Unless otherwise noted, names beginning with
46  *        MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
47  *
48  *  Version History
49  *  ---------------
50  *
51  *  Date      Version   Description
52  *  --------  --------  ------------------------------------------------------
53  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
54  *  06-04-07  02.00.01  Added defines for SAS IO Unit Page 2 PhyFlags.
55  *                      Added Manufacturing Page 11.
56  *                      Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
57  *                      define.
58  *  06-26-07  02.00.02  Adding generic structure for product-specific
59  *                      Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
60  *                      Rework of BIOS Page 2 configuration page.
61  *                      Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
62  *                      forms.
63  *                      Added configuration pages IOC Page 8 and Driver
64  *                      Persistent Mapping Page 0.
65  *  08-31-07  02.00.03  Modified configuration pages dealing with Integrated
66  *                      RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
67  *                      RAID Physical Disk Pages 0 and 1, RAID Configuration
68  *                      Page 0).
69  *                      Added new value for AccessStatus field of SAS Device
70  *                      Page 0 (_SATA_NEEDS_INITIALIZATION).
71  *  10-31-07  02.00.04  Added missing SEPDevHandle field to
72  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
73  *  12-18-07  02.00.05  Modified IO Unit Page 0 to use 32-bit version fields for
74  *                      NVDATA.
75  *                      Modified IOC Page 7 to use masks and added field for
76  *                      SASBroadcastPrimitiveMasks.
77  *                      Added MPI2_CONFIG_PAGE_BIOS_4.
78  *                      Added MPI2_CONFIG_PAGE_LOG_0.
79  *  02-29-08  02.00.06  Modified various names to make them 32-character unique.
80  *                      Added SAS Device IDs.
81  *                      Updated Integrated RAID configuration pages including
82  *                      Manufacturing Page 4, IOC Page 6, and RAID Configuration
83  *                      Page 0.
84  *  05-21-08  02.00.07  Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
85  *                      Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
86  *                      Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
87  *                      Added missing MaxNumRoutedSasAddresses field to
88  *                      MPI2_CONFIG_PAGE_EXPANDER_0.
89  *                      Added SAS Port Page 0.
90  *                      Modified structure layout for
91  *                      MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
92  *  06-27-08  02.00.08  Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
93  *                      MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
94  *  10-02-08  02.00.09  Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
95  *                      to 0x000000FF.
96  *                      Added two new values for the Physical Disk Coercion Size
97  *                      bits in the Flags field of Manufacturing Page 4.
98  *                      Added product-specific Manufacturing pages 16 to 31.
99  *                      Modified Flags bits for controlling write cache on SATA
100  *                      drives in IO Unit Page 1.
101  *                      Added new bit to AdditionalControlFlags of SAS IO Unit
102  *                      Page 1 to control Invalid Topology Correction.
103  *                      Added additional defines for RAID Volume Page 0
104  *                      VolumeStatusFlags field.
105  *                      Modified meaning of RAID Volume Page 0 VolumeSettings
106  *                      define for auto-configure of hot-swap drives.
107  *                      Added SupportedPhysDisks field to RAID Volume Page 1 and
108  *                      added related defines.
109  *                      Added PhysDiskAttributes field (and related defines) to
110  *                      RAID Physical Disk Page 0.
111  *                      Added MPI2_SAS_PHYINFO_PHY_VACANT define.
112  *                      Added three new DiscoveryStatus bits for SAS IO Unit
113  *                      Page 0 and SAS Expander Page 0.
114  *                      Removed multiplexing information from SAS IO Unit pages.
115  *                      Added BootDeviceWaitTime field to SAS IO Unit Page 4.
116  *                      Removed Zone Address Resolved bit from PhyInfo and from
117  *                      Expander Page 0 Flags field.
118  *                      Added two new AccessStatus values to SAS Device Page 0
119  *                      for indicating routing problems. Added 3 reserved words
120  *                      to this page.
121  *  01-19-09  02.00.10  Fixed defines for GPIOVal field of IO Unit Page 3.
122  *                      Inserted missing reserved field into structure for IOC
123  *                      Page 6.
124  *                      Added more pending task bits to RAID Volume Page 0
125  *                      VolumeStatusFlags defines.
126  *                      Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
127  *                      Added a new DiscoveryStatus bit for SAS IO Unit Page 0
128  *                      and SAS Expander Page 0 to flag a downstream initiator
129  *                      when in simplified routing mode.
130  *                      Removed SATA Init Failure defines for DiscoveryStatus
131  *                      fields of SAS IO Unit Page 0 and SAS Expander Page 0.
132  *                      Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
133  *                      Added PortGroups, DmaGroup, and ControlGroup fields to
134  *                      SAS Device Page 0.
135  *  05-06-09  02.00.11  Added structures and defines for IO Unit Page 5 and IO
136  *                      Unit Page 6.
137  *                      Added expander reduced functionality data to SAS
138  *                      Expander Page 0.
139  *                      Added SAS PHY Page 2 and SAS PHY Page 3.
140  *  07-30-09  02.00.12  Added IO Unit Page 7.
141  *                      Added new device ids.
142  *                      Added SAS IO Unit Page 5.
143  *                      Added partial and slumber power management capable flags
144  *                      to SAS Device Page 0 Flags field.
145  *                      Added PhyInfo defines for power condition.
146  *                      Added Ethernet configuration pages.
147  *  10-28-09  02.00.13  Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
148  *                      Added SAS PHY Page 4 structure and defines.
149  *  02-10-10  02.00.14  Modified the comments for the configuration page
150  *                      structures that contain an array of data. The host
151  *                      should use the "count" field in the page data (e.g. the
152  *                      NumPhys field) to determine the number of valid elements
153  *                      in the array.
154  *                      Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
155  *                      Added PowerManagementCapabilities to IO Unit Page 7.
156  *                      Added PortWidthModGroup field to
157  *                      MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
158  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
159  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
160  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
161  *  05-12-10  02.00.15  Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
162  *                      define.
163  *                      Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
164  *                      Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
165  *  08-11-10  02.00.16  Removed IO Unit Page 1 device path (multi-pathing)
166  *                      defines.
167  *  11-10-10  02.00.17  Added ReceptacleID field (replacing Reserved1) to
168  *                      MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
169  *                      the Pinout field.
170  *                      Added BoardTemperature and BoardTemperatureUnits fields
171  *                      to MPI2_CONFIG_PAGE_IO_UNIT_7.
172  *                      Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
173  *                      and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
174  *  02-23-11  02.00.18  Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
175  *                      Added IO Unit Page 8, IO Unit Page 9,
176  *                      and IO Unit Page 10.
177  *                      Added SASNotifyPrimitiveMasks field to
178  *                      MPI2_CONFIG_PAGE_IOC_7.
179  *  03-09-11  02.00.19  Fixed IO Unit Page 10 (to match the spec).
180  *  05-25-11  02.00.20  Cleaned up a few comments.
181  *  08-24-11  02.00.21  Marked the IO Unit Page 7 PowerManagementCapabilities
182  *                      for PCIe link as obsolete.
183  *                      Added SpinupFlags field containing a Disable Spin-up bit
184  *                      to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
185  *                      Unit Page 4.
186  *  11-18-11  02.00.22  Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
187  *                      Added UEFIVersion field to BIOS Page 1 and defined new
188  *                      BiosOptions bits.
189  *                      Incorporating additions for MPI v2.5.
190  *  11-27-12  02.00.23  Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
191  *                      Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
192  *  12-20-12  02.00.24  Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
193  *                      obsolete for MPI v2.5 and later.
194  *                      Added some defines for 12G SAS speeds.
195  *  04-09-13  02.00.25  Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
196  *                      Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
197  *                      match the specification.
198  *  08-19-13  02.00.26  Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
199  *                      future use.
200  *  12-05-13  02.00.27  Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
201  *                      MPI2_CONFIG_PAGE_MAN_7.
202  *                      Added EnclosureLevel and ConnectorName fields to
203  *                      MPI2_CONFIG_PAGE_SAS_DEV_0.
204  *                      Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
205  *                      MPI2_CONFIG_PAGE_SAS_DEV_0.
206  *                      Added EnclosureLevel field to
207  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
208  *                      Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
209  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
210  *  01-08-14  02.00.28  Added more defines for the BiosOptions field of
211  *                      MPI2_CONFIG_PAGE_BIOS_1.
212  *  06-13-14  02.00.29  Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and
213  *                      more defines for the BiosOptions field.
214  *  11-18-14  02.00.30  Updated copyright information.
215  *                      Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG.
216  *                      Added AdapterOrderAux fields to BIOS Page 3.
217  *  03-16-15  02.00.31  Updated for MPI v2.6.
218  *                      Added BoardPowerRequirement, PCISlotPowerAllocation, and
219  *                      Flags field to IO Unit Page 7.
220  *                      Added IO Unit Page 11.
221  *                      Added new SAS Phy Event codes
222  *                      Added PCIe configuration pages.
223  *  03-19-15  02.00.32  Fixed PCIe Link Config page structure names to be
224  *                      unique in first 32 characters.
225  *  05-25-15  02.00.33  Added more defines for the BiosOptions field of
226  *                      MPI2_CONFIG_PAGE_BIOS_1.
227  *  08-25-15  02.00.34  Added PCIe Device Page 2 SGL format capability.
228  *  12-18-15  02.00.35  Added SATADeviceWaitTime to SAS IO Unit Page 4.
229  *  01-21-16  02.00.36  Added/modified MPI2_MFGPAGE_DEVID_SAS defines.
230  *                      Added Link field to PCIe Link Pages
231  *                      Added EnclosureLevel and ConnectorName to PCIe
232  *                      Device Page 0.
233  *                      Added define for PCIE IoUnit page 1 max rate shift.
234  *                      Added comment for reserved ExtPageTypes.
235  *                      Added SAS 4 22.5 gbs speed support.
236  *                      Added PCIe 4 16.0 GT/sec speec support.
237  *                      Removed AHCI support.
238  *                      Removed SOP support.
239  *                      Added NegotiatedLinkRate and NegotiatedPortWidth to
240  *                      PCIe device page 0.
241  *  04-10-16  02.00.37  Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines
242  *  07-01-16  02.00.38  Added Manufacturing page 7 Connector types.
243  *                      Changed declaration of ConnectorName in PCIe DevicePage0
244  *                      to match SAS DevicePage 0.
245  *                      Added SATADeviceWaitTime to IO Unit Page 11.
246  *                      Added MPI26_MFGPAGE_DEVID_SAS4008
247  *                      Added x16 PCIe width to IO Unit Page 7
248  *                      Added LINKFLAGS to control SRIS in PCIe IO Unit page 1
249  *                      phy data.
250  *                      Added InitStatus to PCIe IO Unit Page 1 header.
251  *  09-01-16  02.00.39  Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines.
252  *                      Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and
253  *                      MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats.
254  *  --------------------------------------------------------------------------
255  */
256 
257 #ifndef MPI2_CNFG_H
258 #define MPI2_CNFG_H
259 
260 /*****************************************************************************
261 *   Configuration Page Header and defines
262 *****************************************************************************/
263 
264 /* Config Page Header */
265 typedef struct _MPI2_CONFIG_PAGE_HEADER
266 {
267     U8                 PageVersion;                /* 0x00 */
268     U8                 PageLength;                 /* 0x01 */
269     U8                 PageNumber;                 /* 0x02 */
270     U8                 PageType;                   /* 0x03 */
271 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
272   Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
273 
274 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
275 {
276    MPI2_CONFIG_PAGE_HEADER  Struct;
277    U8                       Bytes[4];
278    U16                      Word16[2];
279    U32                      Word32;
280 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
281   Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
282 
283 /* Extended Config Page Header */
284 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
285 {
286     U8                  PageVersion;                /* 0x00 */
287     U8                  Reserved1;                  /* 0x01 */
288     U8                  PageNumber;                 /* 0x02 */
289     U8                  PageType;                   /* 0x03 */
290     U16                 ExtPageLength;              /* 0x04 */
291     U8                  ExtPageType;                /* 0x06 */
292     U8                  Reserved2;                  /* 0x07 */
293 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
294   MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
295   Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
296 
297 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
298 {
299    MPI2_CONFIG_PAGE_HEADER          Struct;
300    MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
301    U8                               Bytes[8];
302    U16                              Word16[4];
303    U32                              Word32[2];
304 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
305   Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
306 
307 
308 /* PageType field values */
309 #define MPI2_CONFIG_PAGEATTR_READ_ONLY              (0x00)
310 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE             (0x10)
311 #define MPI2_CONFIG_PAGEATTR_PERSISTENT             (0x20)
312 #define MPI2_CONFIG_PAGEATTR_MASK                   (0xF0)
313 
314 #define MPI2_CONFIG_PAGETYPE_IO_UNIT                (0x00)
315 #define MPI2_CONFIG_PAGETYPE_IOC                    (0x01)
316 #define MPI2_CONFIG_PAGETYPE_BIOS                   (0x02)
317 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME            (0x08)
318 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING          (0x09)
319 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK          (0x0A)
320 #define MPI2_CONFIG_PAGETYPE_EXTENDED               (0x0F)
321 #define MPI2_CONFIG_PAGETYPE_MASK                   (0x0F)
322 
323 #define MPI2_CONFIG_TYPENUM_MASK                    (0x0FFF)
324 
325 
326 /* ExtPageType field values */
327 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT         (0x10)
328 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER        (0x11)
329 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE          (0x12)
330 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY             (0x13)
331 #define MPI2_CONFIG_EXTPAGETYPE_LOG                 (0x14)
332 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE           (0x15)
333 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG         (0x16)
334 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING      (0x17)
335 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT            (0x18)
336 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET            (0x19)
337 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING   (0x1A)
338 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT        (0x1B) /* MPI v2.6 and later */
339 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH         (0x1C) /* MPI v2.6 and later */
340 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE         (0x1D) /* MPI v2.6 and later */
341 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK           (0x1E) /* MPI v2.6 and later */
342 /*  Product specific reserved values  0xE0 - 0xEF */
343 /*  Vendor specific reserved values   0xF0 - 0xFF */
344 
345 
346 /*****************************************************************************
347 *   PageAddress defines
348 *****************************************************************************/
349 
350 /* RAID Volume PageAddress format */
351 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK             (0xF0000000)
352 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
353 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE           (0x10000000)
354 
355 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK           (0x0000FFFF)
356 
357 
358 /* RAID Physical Disk PageAddress format */
359 #define MPI2_PHYSDISK_PGAD_FORM_MASK                    (0xF0000000)
360 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM    (0x00000000)
361 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM             (0x10000000)
362 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE               (0x20000000)
363 
364 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK             (0x000000FF)
365 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK               (0x0000FFFF)
366 
367 
368 /* SAS Expander PageAddress format */
369 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK              (0xF0000000)
370 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL     (0x00000000)
371 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM      (0x10000000)
372 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL              (0x20000000)
373 
374 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK            (0x0000FFFF)
375 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK            (0x00FF0000)
376 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT           (16)
377 
378 
379 /* SAS Device PageAddress format */
380 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK              (0xF0000000)
381 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
382 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE            (0x20000000)
383 
384 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK            (0x0000FFFF)
385 
386 
387 /* SAS PHY PageAddress format */
388 #define MPI2_SAS_PHY_PGAD_FORM_MASK                 (0xF0000000)
389 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER           (0x00000000)
390 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX        (0x10000000)
391 
392 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK           (0x000000FF)
393 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK        (0x0000FFFF)
394 
395 
396 /* SAS Port PageAddress format */
397 #define MPI2_SASPORT_PGAD_FORM_MASK                 (0xF0000000)
398 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT        (0x00000000)
399 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM             (0x10000000)
400 
401 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK           (0x00000FFF)
402 
403 
404 /* SAS Enclosure PageAddress format */
405 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK              (0xF0000000)
406 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
407 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE            (0x10000000)
408 
409 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK            (0x0000FFFF)
410 
411 /* Enclosure PageAddress format */
412 #define MPI26_ENCLOS_PGAD_FORM_MASK                 (0xF0000000)
413 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE      (0x00000000)
414 #define MPI26_ENCLOS_PGAD_FORM_HANDLE               (0x10000000)
415 
416 #define MPI26_ENCLOS_PGAD_HANDLE_MASK               (0x0000FFFF)
417 
418 /* RAID Configuration PageAddress format */
419 #define MPI2_RAID_PGAD_FORM_MASK                    (0xF0000000)
420 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM      (0x00000000)
421 #define MPI2_RAID_PGAD_FORM_CONFIGNUM               (0x10000000)
422 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG           (0x20000000)
423 
424 #define MPI2_RAID_PGAD_CONFIGNUM_MASK               (0x000000FF)
425 
426 
427 /* Driver Persistent Mapping PageAddress format */
428 #define MPI2_DPM_PGAD_FORM_MASK                     (0xF0000000)
429 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE              (0x00000000)
430 
431 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK              (0x0FFF0000)
432 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT             (16)
433 #define MPI2_DPM_PGAD_START_ENTRY_MASK              (0x0000FFFF)
434 
435 
436 /* Ethernet PageAddress format */
437 #define MPI2_ETHERNET_PGAD_FORM_MASK                (0xF0000000)
438 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM              (0x00000000)
439 
440 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK           (0x000000FF)
441 
442 
443 /* PCIe Switch PageAddress format */
444 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK            (0xF0000000)
445 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL   (0x00000000)
446 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM    (0x10000000)
447 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL     (0x20000000)
448 
449 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK          (0x0000FFFF)
450 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK         (0x00FF0000)
451 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT        (16)
452 
453 
454 /* PCIe Device PageAddress format */
455 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK            (0xF0000000)
456 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
457 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE          (0x20000000)
458 
459 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK          (0x0000FFFF)
460 
461 /* PCIe Link PageAddress format */
462 #define MPI26_PCIE_LINK_PGAD_FORM_MASK            (0xF0000000)
463 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK   (0x00000000)
464 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM        (0x10000000)
465 
466 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK       (0x000000FF)
467 
468 
469 
470 /****************************************************************************
471 *   Configuration messages
472 ****************************************************************************/
473 
474 /* Configuration Request Message */
475 typedef struct _MPI2_CONFIG_REQUEST
476 {
477     U8                      Action;                     /* 0x00 */
478     U8                      SGLFlags;                   /* 0x01 */
479     U8                      ChainOffset;                /* 0x02 */
480     U8                      Function;                   /* 0x03 */
481     U16                     ExtPageLength;              /* 0x04 */
482     U8                      ExtPageType;                /* 0x06 */
483     U8                      MsgFlags;                   /* 0x07 */
484     U8                      VP_ID;                      /* 0x08 */
485     U8                      VF_ID;                      /* 0x09 */
486     U16                     Reserved1;                  /* 0x0A */
487     U8                      Reserved2;                  /* 0x0C */
488     U8                      ProxyVF_ID;                 /* 0x0D */
489     U16                     Reserved4;                  /* 0x0E */
490     U32                     Reserved3;                  /* 0x10 */
491     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
492     U32                     PageAddress;                /* 0x18 */
493     MPI2_SGE_IO_UNION       PageBufferSGE;              /* 0x1C */
494 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
495   Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
496 
497 /* values for the Action field */
498 #define MPI2_CONFIG_ACTION_PAGE_HEADER              (0x00)
499 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT        (0x01)
500 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT       (0x02)
501 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT             (0x03)
502 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM         (0x04)
503 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT        (0x05)
504 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM          (0x06)
505 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE      (0x07)
506 
507 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
508 
509 
510 /* Config Reply Message */
511 typedef struct _MPI2_CONFIG_REPLY
512 {
513     U8                      Action;                     /* 0x00 */
514     U8                      SGLFlags;                   /* 0x01 */
515     U8                      MsgLength;                  /* 0x02 */
516     U8                      Function;                   /* 0x03 */
517     U16                     ExtPageLength;              /* 0x04 */
518     U8                      ExtPageType;                /* 0x06 */
519     U8                      MsgFlags;                   /* 0x07 */
520     U8                      VP_ID;                      /* 0x08 */
521     U8                      VF_ID;                      /* 0x09 */
522     U16                     Reserved1;                  /* 0x0A */
523     U16                     Reserved2;                  /* 0x0C */
524     U16                     IOCStatus;                  /* 0x0E */
525     U32                     IOCLogInfo;                 /* 0x10 */
526     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
527 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
528   Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
529 
530 
531 
532 /*****************************************************************************
533 *
534 *               C o n f i g u r a t i o n    P a g e s
535 *
536 *****************************************************************************/
537 
538 /****************************************************************************
539 *   Manufacturing Config pages
540 ****************************************************************************/
541 
542 #define MPI2_MFGPAGE_VENDORID_LSI                   (0x1000)
543 
544 /* MPI v2.0 SAS products */
545 #define MPI2_MFGPAGE_DEVID_SAS2004                  (0x0070)
546 #define MPI2_MFGPAGE_DEVID_SAS2008                  (0x0072)
547 #define MPI2_MFGPAGE_DEVID_SAS2108_1                (0x0074)
548 #define MPI2_MFGPAGE_DEVID_SAS2108_2                (0x0076)
549 #define MPI2_MFGPAGE_DEVID_SAS2108_3                (0x0077)
550 #define MPI2_MFGPAGE_DEVID_SAS2116_1                (0x0064)
551 #define MPI2_MFGPAGE_DEVID_SAS2116_2                (0x0065)
552 
553 #define MPI2_MFGPAGE_DEVID_SSS6200                  (0x007E)
554 
555 #define MPI2_MFGPAGE_DEVID_SAS2208_1                (0x0080)
556 #define MPI2_MFGPAGE_DEVID_SAS2208_2                (0x0081)
557 #define MPI2_MFGPAGE_DEVID_SAS2208_3                (0x0082)
558 #define MPI2_MFGPAGE_DEVID_SAS2208_4                (0x0083)
559 #define MPI2_MFGPAGE_DEVID_SAS2208_5                (0x0084)
560 #define MPI2_MFGPAGE_DEVID_SAS2208_6                (0x0085)
561 #define MPI2_MFGPAGE_DEVID_SAS2308_1                (0x0086)
562 #define MPI2_MFGPAGE_DEVID_SAS2308_2                (0x0087)
563 #define MPI2_MFGPAGE_DEVID_SAS2308_3                (0x006E)
564 
565 /* MPI v2.5 SAS products */
566 #define MPI25_MFGPAGE_DEVID_SAS3004                 (0x0096)
567 #define MPI25_MFGPAGE_DEVID_SAS3008                 (0x0097)
568 #define MPI25_MFGPAGE_DEVID_SAS3108_1               (0x0090)
569 #define MPI25_MFGPAGE_DEVID_SAS3108_2               (0x0091)
570 #define MPI25_MFGPAGE_DEVID_SAS3108_5               (0x0094)
571 #define MPI25_MFGPAGE_DEVID_SAS3108_6               (0x0095)
572 
573 /* MPI v2.6 SAS Products */
574 #define MPI26_MFGPAGE_DEVID_SAS3216                 (0x00C9)
575 #define MPI26_MFGPAGE_DEVID_SAS3224                 (0x00C4)
576 #define MPI26_MFGPAGE_DEVID_SAS3316_1               (0x00C5)
577 #define MPI26_MFGPAGE_DEVID_SAS3316_2               (0x00C6)
578 #define MPI26_MFGPAGE_DEVID_SAS3316_3               (0x00C7)
579 #define MPI26_MFGPAGE_DEVID_SAS3316_4               (0x00C8)
580 #define MPI26_MFGPAGE_DEVID_SAS3324_1               (0x00C0)
581 #define MPI26_MFGPAGE_DEVID_SAS3324_2               (0x00C1)
582 #define MPI26_MFGPAGE_DEVID_SAS3324_3               (0x00C2)
583 #define MPI26_MFGPAGE_DEVID_SAS3324_4               (0x00C3)
584 
585 #define MPI26_MFGPAGE_DEVID_SAS3516                 (0x00AA)
586 #define MPI26_MFGPAGE_DEVID_SAS3516_1               (0x00AB)
587 #define MPI26_MFGPAGE_DEVID_SAS3416                 (0x00AC)
588 #define MPI26_MFGPAGE_DEVID_SAS3508                 (0x00AD)
589 #define MPI26_MFGPAGE_DEVID_SAS3508_1               (0x00AE)
590 #define MPI26_MFGPAGE_DEVID_SAS3408                 (0x00AF)
591 
592 #define MPI26_MFGPAGE_DEVID_SAS3716                 (0x00D0)
593 #define MPI26_MFGPAGE_DEVID_SAS3616                 (0x00D1)
594 #define MPI26_MFGPAGE_DEVID_SAS3708                 (0x00D2)
595 
596 #define MPI26_MFGPAGE_DEVID_SAS3816                 (0x00E5)
597 #define MPI26_MFGPAGE_DEVID_SAS3816_1               (0x00E6)
598 
599 #define MPI26_MFGPAGE_DEVID_SAS4008                 (0x00A1)
600 
601 
602 /* Manufacturing Page 0 */
603 
604 typedef struct _MPI2_CONFIG_PAGE_MAN_0
605 {
606     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
607     U8                      ChipName[16];               /* 0x04 */
608     U8                      ChipRevision[8];            /* 0x14 */
609     U8                      BoardName[16];              /* 0x1C */
610     U8                      BoardAssembly[16];          /* 0x2C */
611     U8                      BoardTracerNumber[16];      /* 0x3C */
612 } MPI2_CONFIG_PAGE_MAN_0,
613   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
614   Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
615 
616 #define MPI2_MANUFACTURING0_PAGEVERSION                (0x00)
617 
618 
619 /* Manufacturing Page 1 */
620 
621 typedef struct _MPI2_CONFIG_PAGE_MAN_1
622 {
623     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
624     U8                      VPD[256];                   /* 0x04 */
625 } MPI2_CONFIG_PAGE_MAN_1,
626   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
627   Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
628 
629 #define MPI2_MANUFACTURING1_PAGEVERSION                (0x00)
630 
631 
632 typedef struct _MPI2_CHIP_REVISION_ID
633 {
634     U16 DeviceID;                                       /* 0x00 */
635     U8  PCIRevisionID;                                  /* 0x02 */
636     U8  Reserved;                                       /* 0x03 */
637 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
638   Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
639 
640 
641 /* Manufacturing Page 2 */
642 
643 /*
644  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
645  * one and check Header.PageLength at runtime.
646  */
647 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
648 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS   (1)
649 #endif
650 
651 typedef struct _MPI2_CONFIG_PAGE_MAN_2
652 {
653     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
654     MPI2_CHIP_REVISION_ID   ChipId;                     /* 0x04 */
655     U32                     HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
656 } MPI2_CONFIG_PAGE_MAN_2,
657   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
658   Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
659 
660 #define MPI2_MANUFACTURING2_PAGEVERSION                 (0x00)
661 
662 
663 /* Manufacturing Page 3 */
664 
665 /*
666  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
667  * one and check Header.PageLength at runtime.
668  */
669 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
670 #define MPI2_MAN_PAGE_3_INFO_WORDS          (1)
671 #endif
672 
673 typedef struct _MPI2_CONFIG_PAGE_MAN_3
674 {
675     MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
676     MPI2_CHIP_REVISION_ID               ChipId;         /* 0x04 */
677     U32                                 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
678 } MPI2_CONFIG_PAGE_MAN_3,
679   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
680   Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
681 
682 #define MPI2_MANUFACTURING3_PAGEVERSION                 (0x00)
683 
684 
685 /* Manufacturing Page 4 */
686 
687 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
688 {
689     U8                          PowerSaveFlags;                 /* 0x00 */
690     U8                          InternalOperationsSleepTime;    /* 0x01 */
691     U8                          InternalOperationsRunTime;      /* 0x02 */
692     U8                          HostIdleTime;                   /* 0x03 */
693 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
694   MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
695   Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
696 
697 /* defines for the PowerSaveFlags field */
698 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE               (0x03)
699 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED           (0x00)
700 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE             (0x01)
701 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE               (0x02)
702 
703 typedef struct _MPI2_CONFIG_PAGE_MAN_4
704 {
705     MPI2_CONFIG_PAGE_HEADER             Header;                 /* 0x00 */
706     U32                                 Reserved1;              /* 0x04 */
707     U32                                 Flags;                  /* 0x08 */
708     U8                                  InquirySize;            /* 0x0C */
709     U8                                  Reserved2;              /* 0x0D */
710     U16                                 Reserved3;              /* 0x0E */
711     U8                                  InquiryData[56];        /* 0x10 */
712     U32                                 RAID0VolumeSettings;    /* 0x48 */
713     U32                                 RAID1EVolumeSettings;   /* 0x4C */
714     U32                                 RAID1VolumeSettings;    /* 0x50 */
715     U32                                 RAID10VolumeSettings;   /* 0x54 */
716     U32                                 Reserved4;              /* 0x58 */
717     U32                                 Reserved5;              /* 0x5C */
718     MPI2_MANPAGE4_PWR_SAVE_SETTINGS     PowerSaveSettings;      /* 0x60 */
719     U8                                  MaxOCEDisks;            /* 0x64 */
720     U8                                  ResyncRate;             /* 0x65 */
721     U16                                 DataScrubDuration;      /* 0x66 */
722     U8                                  MaxHotSpares;           /* 0x68 */
723     U8                                  MaxPhysDisksPerVol;     /* 0x69 */
724     U8                                  MaxPhysDisks;           /* 0x6A */
725     U8                                  MaxVolumes;             /* 0x6B */
726 } MPI2_CONFIG_PAGE_MAN_4,
727   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
728   Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
729 
730 #define MPI2_MANUFACTURING4_PAGEVERSION                 (0x0A)
731 
732 /* Manufacturing Page 4 Flags field */
733 #define MPI2_MANPAGE4_METADATA_SIZE_MASK                (0x00030000)
734 #define MPI2_MANPAGE4_METADATA_512MB                    (0x00000000)
735 
736 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA                  (0x00008000)
737 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD               (0x00004000)
738 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR              (0x00002000)
739 
740 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION            (0x00001C00)
741 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB             (0x00000000)
742 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION           (0x00000400)
743 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION        (0x00000800)
744 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION            (0x00000C00)
745 
746 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING            (0x00000300)
747 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING         (0x00000000)
748 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING           (0x00000100)
749 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING      (0x00000200)
750 
751 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER            (0x00000080)
752 #define MPI2_MANPAGE4_RAID10_DISABLE                    (0x00000040)
753 #define MPI2_MANPAGE4_RAID1E_DISABLE                    (0x00000020)
754 #define MPI2_MANPAGE4_RAID1_DISABLE                     (0x00000010)
755 #define MPI2_MANPAGE4_RAID0_DISABLE                     (0x00000008)
756 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE              (0x00000004)
757 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE            (0x00000002)
758 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA                (0x00000001)
759 
760 
761 /* Manufacturing Page 5 */
762 
763 /*
764  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
765  * one and check the value returned for NumPhys at runtime.
766  */
767 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
768 #define MPI2_MAN_PAGE_5_PHY_ENTRIES         (1)
769 #endif
770 
771 typedef struct _MPI2_MANUFACTURING5_ENTRY
772 {
773     U64                                 WWID;           /* 0x00 */
774     U64                                 DeviceName;     /* 0x08 */
775 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
776   Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
777 
778 typedef struct _MPI2_CONFIG_PAGE_MAN_5
779 {
780     MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
781     U8                                  NumPhys;        /* 0x04 */
782     U8                                  Reserved1;      /* 0x05 */
783     U16                                 Reserved2;      /* 0x06 */
784     U32                                 Reserved3;      /* 0x08 */
785     U32                                 Reserved4;      /* 0x0C */
786     MPI2_MANUFACTURING5_ENTRY           Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
787 } MPI2_CONFIG_PAGE_MAN_5,
788   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
789   Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
790 
791 #define MPI2_MANUFACTURING5_PAGEVERSION                 (0x03)
792 
793 
794 /* Manufacturing Page 6 */
795 
796 typedef struct _MPI2_CONFIG_PAGE_MAN_6
797 {
798     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
799     U32                             ProductSpecificInfo;/* 0x04 */
800 } MPI2_CONFIG_PAGE_MAN_6,
801   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
802   Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
803 
804 #define MPI2_MANUFACTURING6_PAGEVERSION                 (0x00)
805 
806 
807 /* Manufacturing Page 7 */
808 
809 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
810 {
811     U32                         Pinout;                 /* 0x00 */
812     U8                          Connector[16];          /* 0x04 */
813     U8                          Location;               /* 0x14 */
814     U8                          ReceptacleID;           /* 0x15 */
815     U16                         Slot;                   /* 0x16 */
816     U32                         Reserved2;              /* 0x18 */
817 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
818   Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
819 
820 /* defines for the Pinout field */
821 #define MPI2_MANPAGE7_PINOUT_LANE_MASK                  (0x0000FF00)
822 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT                 (8)
823 
824 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK                  (0x000000FF)
825 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN               (0x00)
826 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE                (0x01)
827 #define MPI2_MANPAGE7_PINOUT_SFF_8482                   (0x02)
828 #define MPI2_MANPAGE7_PINOUT_SFF_8486                   (0x03)
829 #define MPI2_MANPAGE7_PINOUT_SFF_8484                   (0x04)
830 #define MPI2_MANPAGE7_PINOUT_SFF_8087                   (0x05)
831 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I                (0x06)
832 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I                (0x07)
833 #define MPI2_MANPAGE7_PINOUT_SFF_8470                   (0x08)
834 #define MPI2_MANPAGE7_PINOUT_SFF_8088                   (0x09)
835 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X                (0x0A)
836 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X                (0x0B)
837 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X               (0x0C)
838 #define MPI2_MANPAGE7_PINOUT_SFF_8436                   (0x0D)
839 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A                 (0x0E)
840 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i               (0x0F)
841 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i                (0x10)
842 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i                (0x11)
843 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i                (0x12)
844 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i                (0x13)
845 
846 /* defines for the Location field */
847 #define MPI2_MANPAGE7_LOCATION_UNKNOWN                  (0x01)
848 #define MPI2_MANPAGE7_LOCATION_INTERNAL                 (0x02)
849 #define MPI2_MANPAGE7_LOCATION_EXTERNAL                 (0x04)
850 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE               (0x08)
851 #define MPI2_MANPAGE7_LOCATION_AUTO                     (0x10)
852 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT              (0x20)
853 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED            (0x80)
854 
855 /*
856  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
857  * one and check the value returned for NumPhys at runtime.
858  */
859 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
860 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX  (1)
861 #endif
862 
863 typedef struct _MPI2_CONFIG_PAGE_MAN_7
864 {
865     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
866     U32                             Reserved1;          /* 0x04 */
867     U32                             Reserved2;          /* 0x08 */
868     U32                             Flags;              /* 0x0C */
869     U8                              EnclosureName[16];  /* 0x10 */
870     U8                              NumPhys;            /* 0x20 */
871     U8                              Reserved3;          /* 0x21 */
872     U16                             Reserved4;          /* 0x22 */
873     MPI2_MANPAGE7_CONNECTOR_INFO    ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
874 } MPI2_CONFIG_PAGE_MAN_7,
875   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
876   Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
877 
878 #define MPI2_MANUFACTURING7_PAGEVERSION                 (0x01)
879 
880 /* defines for the Flags field */
881 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL         (0x00000008)
882 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER       (0x00000002)
883 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO                (0x00000001)
884 
885 
886 /*
887  * Generic structure to use for product-specific manufacturing pages
888  * (currently Manufacturing Page 8 through Manufacturing Page 31).
889  */
890 
891 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
892 {
893     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
894     U32                             ProductSpecificInfo;/* 0x04 */
895 } MPI2_CONFIG_PAGE_MAN_PS,
896   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
897   Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
898 
899 #define MPI2_MANUFACTURING8_PAGEVERSION                 (0x00)
900 #define MPI2_MANUFACTURING9_PAGEVERSION                 (0x00)
901 #define MPI2_MANUFACTURING10_PAGEVERSION                (0x00)
902 #define MPI2_MANUFACTURING11_PAGEVERSION                (0x00)
903 #define MPI2_MANUFACTURING12_PAGEVERSION                (0x00)
904 #define MPI2_MANUFACTURING13_PAGEVERSION                (0x00)
905 #define MPI2_MANUFACTURING14_PAGEVERSION                (0x00)
906 #define MPI2_MANUFACTURING15_PAGEVERSION                (0x00)
907 #define MPI2_MANUFACTURING16_PAGEVERSION                (0x00)
908 #define MPI2_MANUFACTURING17_PAGEVERSION                (0x00)
909 #define MPI2_MANUFACTURING18_PAGEVERSION                (0x00)
910 #define MPI2_MANUFACTURING19_PAGEVERSION                (0x00)
911 #define MPI2_MANUFACTURING20_PAGEVERSION                (0x00)
912 #define MPI2_MANUFACTURING21_PAGEVERSION                (0x00)
913 #define MPI2_MANUFACTURING22_PAGEVERSION                (0x00)
914 #define MPI2_MANUFACTURING23_PAGEVERSION                (0x00)
915 #define MPI2_MANUFACTURING24_PAGEVERSION                (0x00)
916 #define MPI2_MANUFACTURING25_PAGEVERSION                (0x00)
917 #define MPI2_MANUFACTURING26_PAGEVERSION                (0x00)
918 #define MPI2_MANUFACTURING27_PAGEVERSION                (0x00)
919 #define MPI2_MANUFACTURING28_PAGEVERSION                (0x00)
920 #define MPI2_MANUFACTURING29_PAGEVERSION                (0x00)
921 #define MPI2_MANUFACTURING30_PAGEVERSION                (0x00)
922 #define MPI2_MANUFACTURING31_PAGEVERSION                (0x00)
923 
924 
925 /****************************************************************************
926 *   IO Unit Config Pages
927 ****************************************************************************/
928 
929 /* IO Unit Page 0 */
930 
931 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
932 {
933     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
934     U64                     UniqueValue;                /* 0x04 */
935     MPI2_VERSION_UNION      NvdataVersionDefault;       /* 0x08 */
936     MPI2_VERSION_UNION      NvdataVersionPersistent;    /* 0x0A */
937 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
938   Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
939 
940 #define MPI2_IOUNITPAGE0_PAGEVERSION                    (0x02)
941 
942 
943 /* IO Unit Page 1 */
944 
945 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
946 {
947     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
948     U32                     Flags;                      /* 0x04 */
949 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
950   Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
951 
952 #define MPI2_IOUNITPAGE1_PAGEVERSION                    (0x04)
953 
954 /* IO Unit Page 1 Flags defines */
955 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK       (0x00004000)
956 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE  (0x00002000)
957 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH             (0x00001000)
958 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY    (0x00000800)
959 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE          (0x00000600)
960 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT         (9)
961 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE        (0x00000000)
962 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE       (0x00000200)
963 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE     (0x00000400)
964 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE       (0x00000100)
965 #define MPI2_IOUNITPAGE1_DISABLE_IR                     (0x00000040)
966 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
967 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID        (0x00000004)
968 
969 
970 /* IO Unit Page 3 */
971 
972 /*
973  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
974  * one and check the value returned for GPIOCount at runtime.
975  */
976 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
977 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX    (1)
978 #endif
979 
980 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
981 {
982     MPI2_CONFIG_PAGE_HEADER Header;                                   /* 0x00 */
983     U8                      GPIOCount;                                /* 0x04 */
984     U8                      Reserved1;                                /* 0x05 */
985     U16                     Reserved2;                                /* 0x06 */
986     U16                     GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
987 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
988   Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
989 
990 #define MPI2_IOUNITPAGE3_PAGEVERSION                    (0x01)
991 
992 /* defines for IO Unit Page 3 GPIOVal field */
993 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK             (0xFFFC)
994 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT            (2)
995 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF               (0x0000)
996 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON                (0x0001)
997 
998 
999 /* IO Unit Page 5 */
1000 
1001 /*
1002  * Upper layer code (drivers, utilities, etc.) should leave this define set to
1003  * one and check the value returned for NumDmaEngines at runtime.
1004  */
1005 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
1006 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES      (1)
1007 #endif
1008 
1009 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5
1010 {
1011     MPI2_CONFIG_PAGE_HEADER Header;                                     /* 0x00 */
1012     U64                     RaidAcceleratorBufferBaseAddress;           /* 0x04 */
1013     U64                     RaidAcceleratorBufferSize;                  /* 0x0C */
1014     U64                     RaidAcceleratorControlBaseAddress;          /* 0x14 */
1015     U8                      RAControlSize;                              /* 0x1C */
1016     U8                      NumDmaEngines;                              /* 0x1D */
1017     U8                      RAMinControlSize;                           /* 0x1E */
1018     U8                      RAMaxControlSize;                           /* 0x1F */
1019     U32                     Reserved1;                                  /* 0x20 */
1020     U32                     Reserved2;                                  /* 0x24 */
1021     U32                     Reserved3;                                  /* 0x28 */
1022     U32                     DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
1023 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
1024   Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
1025 
1026 #define MPI2_IOUNITPAGE5_PAGEVERSION                    (0x00)
1027 
1028 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
1029 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS      (0xFFFF0000)
1030 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS     (16)
1031 
1032 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP                   (0x0008)
1033 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION      (0x0004)
1034 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING                (0x0002)
1035 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION             (0x0001)
1036 
1037 
1038 /* IO Unit Page 6 */
1039 
1040 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6
1041 {
1042     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
1043     U16                     Flags;                                  /* 0x04 */
1044     U8                      RAHostControlSize;                      /* 0x06 */
1045     U8                      Reserved0;                              /* 0x07 */
1046     U64                     RaidAcceleratorHostControlBaseAddress;  /* 0x08 */
1047     U32                     Reserved1;                              /* 0x10 */
1048     U32                     Reserved2;                              /* 0x14 */
1049     U32                     Reserved3;                              /* 0x18 */
1050 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
1051   Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
1052 
1053 #define MPI2_IOUNITPAGE6_PAGEVERSION                    (0x00)
1054 
1055 /* defines for IO Unit Page 6 Flags field */
1056 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR  (0x0001)
1057 
1058 
1059 /* IO Unit Page 7 */
1060 
1061 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7
1062 {
1063     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
1064     U8                      CurrentPowerMode;                       /* 0x04 */ /* reserved in MPI 2.0 */
1065     U8                      PreviousPowerMode;                      /* 0x05 */ /* reserved in MPI 2.0 */
1066     U8                      PCIeWidth;                              /* 0x06 */
1067     U8                      PCIeSpeed;                              /* 0x07 */
1068     U32                     ProcessorState;                         /* 0x08 */
1069     U32                     PowerManagementCapabilities;            /* 0x0C */
1070     U16                     IOCTemperature;                         /* 0x10 */
1071     U8                      IOCTemperatureUnits;                    /* 0x12 */
1072     U8                      IOCSpeed;                               /* 0x13 */
1073     U16                     BoardTemperature;                       /* 0x14 */
1074     U8                      BoardTemperatureUnits;                  /* 0x16 */
1075     U8                      Reserved3;                              /* 0x17 */
1076     U32                     BoardPowerRequirement;                              /* 0x18 */ /* reserved prior to MPI v2.6 */
1077     U32                     PCISlotPowerAllocation;                              /* 0x1C */ /* reserved prior to MPI v2.6 */
1078     U8                      Flags;                              /* 0x20 */ /* reserved prior to MPI v2.6 */
1079     U8                      Reserved6;                              /* 0x21 */
1080     U16                     Reserved7;                              /* 0x22 */
1081     U32                     Reserved8;                              /* 0x24 */
1082 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
1083   Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
1084 
1085 #define MPI2_IOUNITPAGE7_PAGEVERSION                    (0x05)
1086 
1087 /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
1088 #define MPI25_IOUNITPAGE7_PM_INIT_MASK              (0xC0)
1089 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE       (0x00)
1090 #define MPI25_IOUNITPAGE7_PM_INIT_HOST              (0x40)
1091 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT           (0x80)
1092 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA          (0xC0)
1093 
1094 #define MPI25_IOUNITPAGE7_PM_MODE_MASK              (0x07)
1095 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE       (0x00)
1096 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN           (0x01)
1097 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER        (0x04)
1098 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER     (0x05)
1099 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY           (0x06)
1100 
1101 
1102 /* defines for IO Unit Page 7 PCIeWidth field */
1103 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1              (0x01)
1104 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2              (0x02)
1105 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4              (0x04)
1106 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8              (0x08)
1107 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16             (0x10)
1108 
1109 /* defines for IO Unit Page 7 PCIeSpeed field */
1110 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS        (0x00)
1111 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS        (0x01)
1112 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS        (0x02)
1113 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS       (0x03)
1114 
1115 /* defines for IO Unit Page 7 ProcessorState field */
1116 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND         (0x0000000F)
1117 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND        (0)
1118 
1119 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT         (0x00)
1120 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED            (0x01)
1121 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED             (0x02)
1122 
1123 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
1124 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE       (0x00400000)
1125 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE    (0x00200000)
1126 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE        (0x00100000)
1127 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE      (0x00040000)
1128 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE   (0x00020000)
1129 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE       (0x00010000)
1130 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE        (0x00004000)
1131 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE     (0x00002000)
1132 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE         (0x00001000)
1133 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED   (0x00000400)
1134 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED   (0x00000200)
1135 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED   (0x00000100)
1136 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED    (0x00000040)
1137 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED    (0x00000020)
1138 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED    (0x00000010)
1139 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE   (0x00000008) /* obsolete */
1140 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE   (0x00000004) /* obsolete */
1141 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE    (0x00000002) /* obsolete */
1142 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE    (0x00000001) /* obsolete */
1143 
1144 /* obsolete names for the PowerManagementCapabilities bits (above) */
1145 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED    (0x00000400)
1146 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED    (0x00000200)
1147 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED    (0x00000100)
1148 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE    (0x00000008) /* obsolete */
1149 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE    (0x00000004) /* obsolete */
1150 
1151 
1152 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
1153 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT       (0x00)
1154 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT        (0x01)
1155 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS           (0x02)
1156 
1157 /* defines for IO Unit Page 7 IOCSpeed field */
1158 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL             (0x01)
1159 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF             (0x02)
1160 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER          (0x04)
1161 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH           (0x08)
1162 
1163 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
1164 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT     (0x00)
1165 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT      (0x01)
1166 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS         (0x02)
1167 
1168 /* defines for IO Unit Page 7 Flags field */
1169 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC       (0x01)
1170 
1171 
1172 /* IO Unit Page 8 */
1173 
1174 #define MPI2_IOUNIT8_NUM_THRESHOLDS     (4)
1175 
1176 typedef struct _MPI2_IOUNIT8_SENSOR
1177 {
1178     U16                     Flags;                                  /* 0x00 */
1179     U16                     Reserved1;                              /* 0x02 */
1180     U16                     Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
1181     U32                     Reserved2;                              /* 0x0C */
1182     U32                     Reserved3;                              /* 0x10 */
1183     U32                     Reserved4;                              /* 0x14 */
1184 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
1185   Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
1186 
1187 /* defines for IO Unit Page 8 Sensor Flags field */
1188 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE         (0x0008)
1189 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE         (0x0004)
1190 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE         (0x0002)
1191 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE         (0x0001)
1192 
1193 /*
1194  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1195  * one and check the value returned for NumSensors at runtime.
1196  */
1197 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1198 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES     (1)
1199 #endif
1200 
1201 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8
1202 {
1203     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
1204     U32                     Reserved1;                              /* 0x04 */
1205     U32                     Reserved2;                              /* 0x08 */
1206     U8                      NumSensors;                             /* 0x0C */
1207     U8                      PollingInterval;                        /* 0x0D */
1208     U16                     Reserved3;                              /* 0x0E */
1209     MPI2_IOUNIT8_SENSOR     Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
1210 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1211   Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
1212 
1213 #define MPI2_IOUNITPAGE8_PAGEVERSION                    (0x00)
1214 
1215 
1216 /* IO Unit Page 9 */
1217 
1218 typedef struct _MPI2_IOUNIT9_SENSOR
1219 {
1220     U16                     CurrentTemperature;                     /* 0x00 */
1221     U16                     Reserved1;                              /* 0x02 */
1222     U8                      Flags;                                  /* 0x04 */
1223     U8                      Reserved2;                              /* 0x05 */
1224     U16                     Reserved3;                              /* 0x06 */
1225     U32                     Reserved4;                              /* 0x08 */
1226     U32                     Reserved5;                              /* 0x0C */
1227 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
1228   Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
1229 
1230 /* defines for IO Unit Page 9 Sensor Flags field */
1231 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID        (0x01)
1232 
1233 /*
1234  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1235  * one and check the value returned for NumSensors at runtime.
1236  */
1237 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1238 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES     (1)
1239 #endif
1240 
1241 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9
1242 {
1243     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
1244     U32                     Reserved1;                              /* 0x04 */
1245     U32                     Reserved2;                              /* 0x08 */
1246     U8                      NumSensors;                             /* 0x0C */
1247     U8                      Reserved4;                              /* 0x0D */
1248     U16                     Reserved3;                              /* 0x0E */
1249     MPI2_IOUNIT9_SENSOR     Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1250 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1251   Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
1252 
1253 #define MPI2_IOUNITPAGE9_PAGEVERSION                    (0x00)
1254 
1255 
1256 /* IO Unit Page 10 */
1257 
1258 typedef struct _MPI2_IOUNIT10_FUNCTION
1259 {
1260     U8                      CreditPercent;      /* 0x00 */
1261     U8                      Reserved1;          /* 0x01 */
1262     U16                     Reserved2;          /* 0x02 */
1263 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
1264   Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
1265 
1266 /*
1267  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1268  * one and check the value returned for NumFunctions at runtime.
1269  */
1270 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1271 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES      (1)
1272 #endif
1273 
1274 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10
1275 {
1276     MPI2_CONFIG_PAGE_HEADER Header;                                         /* 0x00 */
1277     U8                      NumFunctions;                                   /* 0x04 */
1278     U8                      Reserved1;                                      /* 0x05 */
1279     U16                     Reserved2;                                      /* 0x06 */
1280     U32                     Reserved3;                                      /* 0x08 */
1281     U32                     Reserved4;                                      /* 0x0C */
1282     MPI2_IOUNIT10_FUNCTION  Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];   /* 0x10 */
1283 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1284   Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
1285 
1286 #define MPI2_IOUNITPAGE10_PAGEVERSION                   (0x01)
1287 
1288 
1289 /* IO Unit Page 11 (for MPI v2.6 and later) */
1290 
1291 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP
1292 {
1293     U8          MaxTargetSpinup;            /* 0x00 */
1294     U8          SpinupDelay;                /* 0x01 */
1295     U8          SpinupFlags;                /* 0x02 */
1296     U8          Reserved1;                  /* 0x03 */
1297 } MPI26_IOUNIT11_SPINUP_GROUP, MPI2_POINTER PTR_MPI26_IOUNIT11_SPINUP_GROUP,
1298   Mpi26IOUnit11SpinupGroup_t, MPI2_POINTER pMpi26IOUnit11SpinupGroup_t;
1299 
1300 /* defines for IO Unit Page 11 SpinupFlags */
1301 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG          (0x01)
1302 
1303 
1304 /*
1305  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1306  * four and check the value returned for NumPhys at runtime.
1307  */
1308 #ifndef MPI26_IOUNITPAGE11_PHY_MAX
1309 #define MPI26_IOUNITPAGE11_PHY_MAX        (4)
1310 #endif
1311 
1312 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11
1313 {
1314     MPI2_CONFIG_PAGE_HEADER         Header;                         /* 0x00 */
1315     U32                             Reserved1;                      /* 0x04 */
1316     MPI26_IOUNIT11_SPINUP_GROUP     SpinupGroupParameters[4];       /* 0x08 */
1317     U32                             Reserved2;                      /* 0x18 */
1318     U32                             Reserved3;                      /* 0x1C */
1319     U32                             Reserved4;                      /* 0x20 */
1320     U8                              BootDeviceWaitTime;             /* 0x24 */
1321     U8                              SATADeviceWaitTime;             /* 0x25 */
1322     U16                             Reserved6;                      /* 0x26 */
1323     U8                              NumPhys;                        /* 0x28 */
1324     U8                              PEInitialSpinupDelay;           /* 0x29 */
1325     U8                              PEReplyDelay;                   /* 0x2A */
1326     U8                              Flags;                          /* 0x2B */
1327     U8                              PHY[MPI26_IOUNITPAGE11_PHY_MAX];/* 0x2C */
1328 } MPI26_CONFIG_PAGE_IO_UNIT_11,
1329   MPI2_POINTER PTR_MPI26_CONFIG_PAGE_IO_UNIT_11,
1330   Mpi26IOUnitPage11_t, MPI2_POINTER pMpi26IOUnitPage11_t;
1331 
1332 #define MPI26_IOUNITPAGE11_PAGEVERSION                  (0x00)
1333 
1334 /* defines for Flags field */
1335 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE        (0x01)
1336 
1337 /* defines for PHY field */
1338 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK        (0x03)
1339 
1340 
1341 
1342 /****************************************************************************
1343 *   IOC Config Pages
1344 ****************************************************************************/
1345 
1346 /* IOC Page 0 */
1347 
1348 typedef struct _MPI2_CONFIG_PAGE_IOC_0
1349 {
1350     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1351     U32                     Reserved1;                  /* 0x04 */
1352     U32                     Reserved2;                  /* 0x08 */
1353     U16                     VendorID;                   /* 0x0C */
1354     U16                     DeviceID;                   /* 0x0E */
1355     U8                      RevisionID;                 /* 0x10 */
1356     U8                      Reserved3;                  /* 0x11 */
1357     U16                     Reserved4;                  /* 0x12 */
1358     U32                     ClassCode;                  /* 0x14 */
1359     U16                     SubsystemVendorID;          /* 0x18 */
1360     U16                     SubsystemID;                /* 0x1A */
1361 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
1362   Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
1363 
1364 #define MPI2_IOCPAGE0_PAGEVERSION                       (0x02)
1365 
1366 
1367 /* IOC Page 1 */
1368 
1369 typedef struct _MPI2_CONFIG_PAGE_IOC_1
1370 {
1371     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1372     U32                     Flags;                      /* 0x04 */
1373     U32                     CoalescingTimeout;          /* 0x08 */
1374     U8                      CoalescingDepth;            /* 0x0C */
1375     U8                      PCISlotNum;                 /* 0x0D */
1376     U8                      PCIBusNum;                  /* 0x0E */
1377     U8                      PCIDomainSegment;           /* 0x0F */
1378     U32                     Reserved1;                  /* 0x10 */
1379     U32                     Reserved2;                  /* 0x14 */
1380 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1381   Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1382 
1383 #define MPI2_IOCPAGE1_PAGEVERSION                       (0x05)
1384 
1385 /* defines for IOC Page 1 Flags field */
1386 #define MPI2_IOCPAGE1_REPLY_COALESCING                  (0x00000001)
1387 
1388 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN                (0xFF)
1389 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN                 (0xFF)
1390 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN                 (0xFF)
1391 
1392 /* IOC Page 6 */
1393 
1394 typedef struct _MPI2_CONFIG_PAGE_IOC_6
1395 {
1396     MPI2_CONFIG_PAGE_HEADER Header;                         /* 0x00 */
1397     U32                     CapabilitiesFlags;              /* 0x04 */
1398     U8                      MaxDrivesRAID0;                 /* 0x08 */
1399     U8                      MaxDrivesRAID1;                 /* 0x09 */
1400     U8                      MaxDrivesRAID1E;                /* 0x0A */
1401     U8                      MaxDrivesRAID10;                /* 0x0B */
1402     U8                      MinDrivesRAID0;                 /* 0x0C */
1403     U8                      MinDrivesRAID1;                 /* 0x0D */
1404     U8                      MinDrivesRAID1E;                /* 0x0E */
1405     U8                      MinDrivesRAID10;                /* 0x0F */
1406     U32                     Reserved1;                      /* 0x10 */
1407     U8                      MaxGlobalHotSpares;             /* 0x14 */
1408     U8                      MaxPhysDisks;                   /* 0x15 */
1409     U8                      MaxVolumes;                     /* 0x16 */
1410     U8                      MaxConfigs;                     /* 0x17 */
1411     U8                      MaxOCEDisks;                    /* 0x18 */
1412     U8                      Reserved2;                      /* 0x19 */
1413     U16                     Reserved3;                      /* 0x1A */
1414     U32                     SupportedStripeSizeMapRAID0;    /* 0x1C */
1415     U32                     SupportedStripeSizeMapRAID1E;   /* 0x20 */
1416     U32                     SupportedStripeSizeMapRAID10;   /* 0x24 */
1417     U32                     Reserved4;                      /* 0x28 */
1418     U32                     Reserved5;                      /* 0x2C */
1419     U16                     DefaultMetadataSize;            /* 0x30 */
1420     U16                     Reserved6;                      /* 0x32 */
1421     U16                     MaxBadBlockTableEntries;        /* 0x34 */
1422     U16                     Reserved7;                      /* 0x36 */
1423     U32                     IRNvsramVersion;                /* 0x38 */
1424 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1425   Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1426 
1427 #define MPI2_IOCPAGE6_PAGEVERSION                       (0x05)
1428 
1429 /* defines for IOC Page 6 CapabilitiesFlags */
1430 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT      (0x00000020)
1431 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT          (0x00000010)
1432 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT           (0x00000008)
1433 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT          (0x00000004)
1434 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT           (0x00000002)
1435 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE        (0x00000001)
1436 
1437 
1438 /* IOC Page 7 */
1439 
1440 #define MPI2_IOCPAGE7_EVENTMASK_WORDS       (4)
1441 
1442 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1443 {
1444     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1445     U32                     Reserved1;                  /* 0x04 */
1446     U32                     EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1447     U16                     SASBroadcastPrimitiveMasks; /* 0x18 */
1448     U16                     SASNotifyPrimitiveMasks;    /* 0x1A */
1449     U32                     Reserved3;                  /* 0x1C */
1450 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1451   Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1452 
1453 #define MPI2_IOCPAGE7_PAGEVERSION                       (0x02)
1454 
1455 
1456 /* IOC Page 8 */
1457 
1458 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1459 {
1460     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1461     U8                      NumDevsPerEnclosure;        /* 0x04 */
1462     U8                      Reserved1;                  /* 0x05 */
1463     U16                     Reserved2;                  /* 0x06 */
1464     U16                     MaxPersistentEntries;       /* 0x08 */
1465     U16                     MaxNumPhysicalMappedIDs;    /* 0x0A */
1466     U16                     Flags;                      /* 0x0C */
1467     U16                     Reserved3;                  /* 0x0E */
1468     U16                     IRVolumeMappingFlags;       /* 0x10 */
1469     U16                     Reserved4;                  /* 0x12 */
1470     U32                     Reserved5;                  /* 0x14 */
1471 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1472   Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1473 
1474 #define MPI2_IOCPAGE8_PAGEVERSION                       (0x00)
1475 
1476 /* defines for IOC Page 8 Flags field */
1477 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1             (0x00000020)
1478 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0         (0x00000010)
1479 
1480 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE           (0x0000000E)
1481 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING  (0x00000000)
1482 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING      (0x00000002)
1483 
1484 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING  (0x00000001)
1485 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING   (0x00000000)
1486 
1487 /* defines for IOC Page 8 IRVolumeMappingFlags */
1488 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE  (0x00000003)
1489 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING        (0x00000000)
1490 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING       (0x00000001)
1491 
1492 
1493 /****************************************************************************
1494 *   BIOS Config Pages
1495 ****************************************************************************/
1496 
1497 /* BIOS Page 1 */
1498 
1499 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1500 {
1501     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1502     U32                     BiosOptions;                /* 0x04 */
1503     U32                     IOCSettings;                /* 0x08 */
1504     U8                      SSUTimeout;                 /* 0x0C */
1505     U8                      Reserved1;                  /* 0x0D */
1506     U16                     Reserved2;                  /* 0x0E */
1507     U32                     DeviceSettings;             /* 0x10 */
1508     U16                     NumberOfDevices;            /* 0x14 */
1509     U16                     UEFIVersion;                /* 0x16 */
1510     U16                     IOTimeoutBlockDevicesNonRM; /* 0x18 */
1511     U16                     IOTimeoutSequential;        /* 0x1A */
1512     U16                     IOTimeoutOther;             /* 0x1C */
1513     U16                     IOTimeoutBlockDevicesRM;    /* 0x1E */
1514 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1515   Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1516 
1517 #define MPI2_BIOSPAGE1_PAGEVERSION                      (0x07)
1518 
1519 /* values for BIOS Page 1 BiosOptions field */
1520 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE    (0x00008000)
1521 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG                  (0x00004000)
1522 
1523 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK                         (0x00003800)
1524 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL                        (0x00000000)
1525 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE                   (0x00000800)
1526 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID                        (0x00001000)
1527 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS                        (0x00001800)
1528 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY                        (0x00002000)
1529 
1530 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS                 (0x00000400)
1531 
1532 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD       (0x00000300)
1533 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD   (0x00000000)
1534 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD       (0x00000100)
1535 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD    (0x00000200)
1536 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD    (0x00000300)
1537 
1538 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID                      (0x000000F0)
1539 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID                       (0x00000000)
1540 
1541 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION       (0x00000006)
1542 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII                  (0x00000000)
1543 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII                 (0x00000002)
1544 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII           (0x00000004)
1545 
1546 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS                     (0x00000001)
1547 
1548 /* values for BIOS Page 1 IOCSettings field */
1549 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE      (0x00030000)
1550 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT       (0x00000000)
1551 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT          (0x00010000)
1552 
1553 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING           (0x000000C0)
1554 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING           (0x00000000)
1555 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING           (0x00000040)
1556 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING          (0x00000080)
1557 
1558 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT      (0x00000030)
1559 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT                (0x00000000)
1560 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT              (0x00000010)
1561 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT                (0x00000020)
1562 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT               (0x00000030)
1563 
1564 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS             (0x00000008)
1565 
1566 /* values for BIOS Page 1 DeviceSettings field */
1567 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING     (0x00000010)
1568 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN           (0x00000008)
1569 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN            (0x00000004)
1570 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN        (0x00000002)
1571 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN         (0x00000001)
1572 
1573 /* defines for BIOS Page 1 UEFIVersion field */
1574 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK              (0xFF00)
1575 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT             (8)
1576 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK              (0x00FF)
1577 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT             (0)
1578 
1579 
1580 
1581 /* BIOS Page 2 */
1582 
1583 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1584 {
1585     U32         Reserved1;                              /* 0x00 */
1586     U32         Reserved2;                              /* 0x04 */
1587     U32         Reserved3;                              /* 0x08 */
1588     U32         Reserved4;                              /* 0x0C */
1589     U32         Reserved5;                              /* 0x10 */
1590     U32         Reserved6;                              /* 0x14 */
1591 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1592   MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1593   Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1594 
1595 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1596 {
1597     U64         SASAddress;                             /* 0x00 */
1598     U8          LUN[8];                                 /* 0x08 */
1599     U32         Reserved1;                              /* 0x10 */
1600     U32         Reserved2;                              /* 0x14 */
1601 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1602   Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1603 
1604 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1605 {
1606     U64         EnclosureLogicalID;                     /* 0x00 */
1607     U32         Reserved1;                              /* 0x08 */
1608     U32         Reserved2;                              /* 0x0C */
1609     U16         SlotNumber;                             /* 0x10 */
1610     U16         Reserved3;                              /* 0x12 */
1611     U32         Reserved4;                              /* 0x14 */
1612 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1613   MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1614   Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1615 
1616 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1617 {
1618     U64         DeviceName;                             /* 0x00 */
1619     U8          LUN[8];                                 /* 0x08 */
1620     U32         Reserved1;                              /* 0x10 */
1621     U32         Reserved2;                              /* 0x14 */
1622 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1623   Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1624 
1625 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1626 {
1627     MPI2_BOOT_DEVICE_ADAPTER_ORDER  AdapterOrder;
1628     MPI2_BOOT_DEVICE_SAS_WWID       SasWwid;
1629     MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1630     MPI2_BOOT_DEVICE_DEVICE_NAME    DeviceName;
1631 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1632   Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1633 
1634 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1635 {
1636     MPI2_CONFIG_PAGE_HEADER     Header;                 /* 0x00 */
1637     U32                         Reserved1;              /* 0x04 */
1638     U32                         Reserved2;              /* 0x08 */
1639     U32                         Reserved3;              /* 0x0C */
1640     U32                         Reserved4;              /* 0x10 */
1641     U32                         Reserved5;              /* 0x14 */
1642     U32                         Reserved6;              /* 0x18 */
1643     U8                          ReqBootDeviceForm;      /* 0x1C */
1644     U8                          Reserved7;              /* 0x1D */
1645     U16                         Reserved8;              /* 0x1E */
1646     MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedBootDevice;    /* 0x20 */
1647     U8                          ReqAltBootDeviceForm;   /* 0x38 */
1648     U8                          Reserved9;              /* 0x39 */
1649     U16                         Reserved10;             /* 0x3A */
1650     MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedAltBootDevice; /* 0x3C */
1651     U8                          CurrentBootDeviceForm;  /* 0x58 */
1652     U8                          Reserved11;             /* 0x59 */
1653     U16                         Reserved12;             /* 0x5A */
1654     MPI2_BIOSPAGE2_BOOT_DEVICE  CurrentBootDevice;      /* 0x58 */
1655 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1656   Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1657 
1658 #define MPI2_BIOSPAGE2_PAGEVERSION                      (0x04)
1659 
1660 /* values for BIOS Page 2 BootDeviceForm fields */
1661 #define MPI2_BIOSPAGE2_FORM_MASK                        (0x0F)
1662 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED         (0x00)
1663 #define MPI2_BIOSPAGE2_FORM_SAS_WWID                    (0x05)
1664 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT              (0x06)
1665 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME                 (0x07)
1666 
1667 
1668 /* BIOS Page 3 */
1669 
1670 #define MPI2_BIOSPAGE3_NUM_ADAPTER      (4)
1671 
1672 typedef struct _MPI2_ADAPTER_INFO
1673 {
1674     U8      PciBusNumber;                               /* 0x00 */
1675     U8      PciDeviceAndFunctionNumber;                 /* 0x01 */
1676     U16     AdapterFlags;                               /* 0x02 */
1677 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1678   Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1679 
1680 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED                (0x0001)
1681 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS             (0x0002)
1682 
1683 typedef struct _MPI2_ADAPTER_ORDER_AUX
1684 {
1685     U64     WWID;                                       /* 0x00 */
1686     U32     Reserved1;                                  /* 0x08 */
1687     U32     Reserved2;                                  /* 0x0C */
1688 } MPI2_ADAPTER_ORDER_AUX, MPI2_POINTER PTR_MPI2_ADAPTER_ORDER_AUX,
1689   Mpi2AdapterOrderAux_t, MPI2_POINTER pMpi2AdapterOrderAux_t;
1690 
1691 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1692 {
1693     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1694     U32                     GlobalFlags;                /* 0x04 */
1695     U32                     BiosVersion;                /* 0x08 */
1696     MPI2_ADAPTER_INFO       AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x0C */
1697     U32                     Reserved1;                  /* 0x1C */
1698     MPI2_ADAPTER_ORDER_AUX  AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x20 */ /* MPI v2.5 and newer */
1699 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1700   Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1701 
1702 #define MPI2_BIOSPAGE3_PAGEVERSION                      (0x01)
1703 
1704 /* values for BIOS Page 3 GlobalFlags */
1705 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR             (0x00000002)
1706 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE             (0x00000004)
1707 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE        (0x00000010)
1708 
1709 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK      (0x000000E0)
1710 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY      (0x00000000)
1711 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY            (0x00000020)
1712 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY        (0x00000040)
1713 
1714 
1715 /* BIOS Page 4 */
1716 
1717 /*
1718  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1719  * one and check the value returned for NumPhys at runtime.
1720  */
1721 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1722 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES        (1)
1723 #endif
1724 
1725 typedef struct _MPI2_BIOS4_ENTRY
1726 {
1727     U64                     ReassignmentWWID;       /* 0x00 */
1728     U64                     ReassignmentDeviceName; /* 0x08 */
1729 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1730   Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1731 
1732 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1733 {
1734     MPI2_CONFIG_PAGE_HEADER Header;                             /* 0x00 */
1735     U8                      NumPhys;                            /* 0x04 */
1736     U8                      Reserved1;                          /* 0x05 */
1737     U16                     Reserved2;                          /* 0x06 */
1738     MPI2_BIOS4_ENTRY        Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES];  /* 0x08 */
1739 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1740   Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1741 
1742 #define MPI2_BIOSPAGE4_PAGEVERSION                      (0x01)
1743 
1744 
1745 /****************************************************************************
1746 *   RAID Volume Config Pages
1747 ****************************************************************************/
1748 
1749 /* RAID Volume Page 0 */
1750 
1751 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1752 {
1753     U8                      RAIDSetNum;                 /* 0x00 */
1754     U8                      PhysDiskMap;                /* 0x01 */
1755     U8                      PhysDiskNum;                /* 0x02 */
1756     U8                      Reserved;                   /* 0x03 */
1757 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1758   Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1759 
1760 /* defines for the PhysDiskMap field */
1761 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY                  (0x01)
1762 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY                (0x02)
1763 
1764 typedef struct _MPI2_RAIDVOL0_SETTINGS
1765 {
1766     U16                     Settings;                   /* 0x00 */
1767     U8                      HotSparePool;               /* 0x01 */
1768     U8                      Reserved;                   /* 0x02 */
1769 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1770   Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1771 
1772 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1773 #define MPI2_RAID_HOT_SPARE_POOL_0                      (0x01)
1774 #define MPI2_RAID_HOT_SPARE_POOL_1                      (0x02)
1775 #define MPI2_RAID_HOT_SPARE_POOL_2                      (0x04)
1776 #define MPI2_RAID_HOT_SPARE_POOL_3                      (0x08)
1777 #define MPI2_RAID_HOT_SPARE_POOL_4                      (0x10)
1778 #define MPI2_RAID_HOT_SPARE_POOL_5                      (0x20)
1779 #define MPI2_RAID_HOT_SPARE_POOL_6                      (0x40)
1780 #define MPI2_RAID_HOT_SPARE_POOL_7                      (0x80)
1781 
1782 /* RAID Volume Page 0 VolumeSettings defines */
1783 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX     (0x0008)
1784 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1785 
1786 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING        (0x0003)
1787 #define MPI2_RAIDVOL0_SETTING_UNCHANGED                 (0x0000)
1788 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING     (0x0001)
1789 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING      (0x0002)
1790 
1791 /*
1792  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1793  * one and check the value returned for NumPhysDisks at runtime.
1794  */
1795 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1796 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX       (1)
1797 #endif
1798 
1799 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1800 {
1801     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1802     U16                     DevHandle;                  /* 0x04 */
1803     U8                      VolumeState;                /* 0x06 */
1804     U8                      VolumeType;                 /* 0x07 */
1805     U32                     VolumeStatusFlags;          /* 0x08 */
1806     MPI2_RAIDVOL0_SETTINGS  VolumeSettings;             /* 0x0C */
1807     U64                     MaxLBA;                     /* 0x10 */
1808     U32                     StripeSize;                 /* 0x18 */
1809     U16                     BlockSize;                  /* 0x1C */
1810     U16                     Reserved1;                  /* 0x1E */
1811     U8                      SupportedPhysDisks;         /* 0x20 */
1812     U8                      ResyncRate;                 /* 0x21 */
1813     U16                     DataScrubDuration;          /* 0x22 */
1814     U8                      NumPhysDisks;               /* 0x24 */
1815     U8                      Reserved2;                  /* 0x25 */
1816     U8                      Reserved3;                  /* 0x26 */
1817     U8                      InactiveStatus;             /* 0x27 */
1818     MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1819 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1820   Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1821 
1822 #define MPI2_RAIDVOLPAGE0_PAGEVERSION           (0x0A)
1823 
1824 /* values for RAID VolumeState */
1825 #define MPI2_RAID_VOL_STATE_MISSING                         (0x00)
1826 #define MPI2_RAID_VOL_STATE_FAILED                          (0x01)
1827 #define MPI2_RAID_VOL_STATE_INITIALIZING                    (0x02)
1828 #define MPI2_RAID_VOL_STATE_ONLINE                          (0x03)
1829 #define MPI2_RAID_VOL_STATE_DEGRADED                        (0x04)
1830 #define MPI2_RAID_VOL_STATE_OPTIMAL                         (0x05)
1831 
1832 /* values for RAID VolumeType */
1833 #define MPI2_RAID_VOL_TYPE_RAID0                            (0x00)
1834 #define MPI2_RAID_VOL_TYPE_RAID1E                           (0x01)
1835 #define MPI2_RAID_VOL_TYPE_RAID1                            (0x02)
1836 #define MPI2_RAID_VOL_TYPE_RAID10                           (0x05)
1837 #define MPI2_RAID_VOL_TYPE_UNKNOWN                          (0xFF)
1838 
1839 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1840 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC            (0x02000000)
1841 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING        (0x01000000)
1842 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING               (0x00800000)
1843 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING      (0x00400000)
1844 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT      (0x00200000)
1845 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB                (0x00100000)
1846 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK         (0x00080000)
1847 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION        (0x00040000)
1848 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT           (0x00020000)
1849 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS        (0x00010000)
1850 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT        (0x00000080)
1851 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED               (0x00000040)
1852 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE              (0x00000020)
1853 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR          (0x00000000)
1854 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR        (0x00000010)
1855 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL      (0x00000008)
1856 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE           (0x00000004)
1857 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED                  (0x00000002)
1858 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED                   (0x00000001)
1859 
1860 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1861 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS             (0x08)
1862 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS                    (0x04)
1863 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL                  (0x02)
1864 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL                 (0x01)
1865 
1866 /* values for RAID Volume Page 0 InactiveStatus field */
1867 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE                  (0x00)
1868 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE           (0x01)
1869 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE           (0x02)
1870 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE    (0x03)
1871 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE             (0x04)
1872 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE    (0x05)
1873 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED                (0x06)
1874 
1875 
1876 /* RAID Volume Page 1 */
1877 
1878 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1879 {
1880     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1881     U16                     DevHandle;                  /* 0x04 */
1882     U16                     Reserved0;                  /* 0x06 */
1883     U8                      GUID[24];                   /* 0x08 */
1884     U8                      Name[16];                   /* 0x20 */
1885     U64                     WWID;                       /* 0x30 */
1886     U32                     Reserved1;                  /* 0x38 */
1887     U32                     Reserved2;                  /* 0x3C */
1888 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1889   Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1890 
1891 #define MPI2_RAIDVOLPAGE1_PAGEVERSION           (0x03)
1892 
1893 
1894 /****************************************************************************
1895 *   RAID Physical Disk Config Pages
1896 ****************************************************************************/
1897 
1898 /* RAID Physical Disk Page 0 */
1899 
1900 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1901 {
1902     U16                     Reserved1;                  /* 0x00 */
1903     U8                      HotSparePool;               /* 0x02 */
1904     U8                      Reserved2;                  /* 0x03 */
1905 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1906   Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1907 
1908 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1909 
1910 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1911 {
1912     U8                      VendorID[8];                /* 0x00 */
1913     U8                      ProductID[16];              /* 0x08 */
1914     U8                      ProductRevLevel[4];         /* 0x18 */
1915     U8                      SerialNum[32];              /* 0x1C */
1916 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1917   MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1918   Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1919 
1920 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1921 {
1922     MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
1923     U16                             DevHandle;                  /* 0x04 */
1924     U8                              Reserved1;                  /* 0x06 */
1925     U8                              PhysDiskNum;                /* 0x07 */
1926     MPI2_RAIDPHYSDISK0_SETTINGS     PhysDiskSettings;           /* 0x08 */
1927     U32                             Reserved2;                  /* 0x0C */
1928     MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData;                /* 0x10 */
1929     U32                             Reserved3;                  /* 0x4C */
1930     U8                              PhysDiskState;              /* 0x50 */
1931     U8                              OfflineReason;              /* 0x51 */
1932     U8                              IncompatibleReason;         /* 0x52 */
1933     U8                              PhysDiskAttributes;         /* 0x53 */
1934     U32                             PhysDiskStatusFlags;        /* 0x54 */
1935     U64                             DeviceMaxLBA;               /* 0x58 */
1936     U64                             HostMaxLBA;                 /* 0x60 */
1937     U64                             CoercedMaxLBA;              /* 0x68 */
1938     U16                             BlockSize;                  /* 0x70 */
1939     U16                             Reserved5;                  /* 0x72 */
1940     U32                             Reserved6;                  /* 0x74 */
1941 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1942   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1943   Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1944 
1945 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION          (0x05)
1946 
1947 /* PhysDiskState defines */
1948 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED               (0x00)
1949 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE               (0x01)
1950 #define MPI2_RAID_PD_STATE_OFFLINE                      (0x02)
1951 #define MPI2_RAID_PD_STATE_ONLINE                       (0x03)
1952 #define MPI2_RAID_PD_STATE_HOT_SPARE                    (0x04)
1953 #define MPI2_RAID_PD_STATE_DEGRADED                     (0x05)
1954 #define MPI2_RAID_PD_STATE_REBUILDING                   (0x06)
1955 #define MPI2_RAID_PD_STATE_OPTIMAL                      (0x07)
1956 
1957 /* OfflineReason defines */
1958 #define MPI2_PHYSDISK0_ONLINE                           (0x00)
1959 #define MPI2_PHYSDISK0_OFFLINE_MISSING                  (0x01)
1960 #define MPI2_PHYSDISK0_OFFLINE_FAILED                   (0x03)
1961 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING             (0x04)
1962 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED                (0x05)
1963 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED         (0x06)
1964 #define MPI2_PHYSDISK0_OFFLINE_OTHER                    (0xFF)
1965 
1966 /* IncompatibleReason defines */
1967 #define MPI2_PHYSDISK0_COMPATIBLE                       (0x00)
1968 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL            (0x01)
1969 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE           (0x02)
1970 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA             (0x03)
1971 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD   (0x04)
1972 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA    (0x05)
1973 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE          (0x06)
1974 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN             (0xFF)
1975 
1976 /* PhysDiskAttributes defines */
1977 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK                (0x0C)
1978 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE         (0x08)
1979 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE           (0x04)
1980 
1981 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK             (0x03)
1982 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL              (0x02)
1983 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL             (0x01)
1984 
1985 /* PhysDiskStatusFlags defines */
1986 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED        (0x00000040)
1987 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET           (0x00000020)
1988 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED  (0x00000010)
1989 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS     (0x00000000)
1990 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1991 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME      (0x00000004)
1992 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED             (0x00000002)
1993 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC          (0x00000001)
1994 
1995 
1996 /* RAID Physical Disk Page 1 */
1997 
1998 /*
1999  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2000  * one and check the value returned for NumPhysDiskPaths at runtime.
2001  */
2002 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
2003 #define MPI2_RAID_PHYS_DISK1_PATH_MAX   (1)
2004 #endif
2005 
2006 typedef struct _MPI2_RAIDPHYSDISK1_PATH
2007 {
2008     U16             DevHandle;          /* 0x00 */
2009     U16             Reserved1;          /* 0x02 */
2010     U64             WWID;               /* 0x04 */
2011     U64             OwnerWWID;          /* 0x0C */
2012     U8              OwnerIdentifier;    /* 0x14 */
2013     U8              Reserved2;          /* 0x15 */
2014     U16             Flags;              /* 0x16 */
2015 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
2016   Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
2017 
2018 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
2019 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY        (0x0004)
2020 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN         (0x0002)
2021 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID        (0x0001)
2022 
2023 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
2024 {
2025     MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
2026     U8                              NumPhysDiskPaths;           /* 0x04 */
2027     U8                              PhysDiskNum;                /* 0x05 */
2028     U16                             Reserved1;                  /* 0x06 */
2029     U32                             Reserved2;                  /* 0x08 */
2030     MPI2_RAIDPHYSDISK1_PATH         PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
2031 } MPI2_CONFIG_PAGE_RD_PDISK_1,
2032   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
2033   Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
2034 
2035 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION          (0x02)
2036 
2037 
2038 /****************************************************************************
2039 *   values for fields used by several types of SAS Config Pages
2040 ****************************************************************************/
2041 
2042 /* values for NegotiatedLinkRates fields */
2043 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL             (0xF0)
2044 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL            (4)
2045 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL            (0x0F)
2046 /* link rates used for Negotiated Physical and Logical Link Rate */
2047 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
2048 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
2049 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
2050 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
2051 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
2052 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
2053 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
2054 #define MPI2_SAS_NEG_LINK_RATE_1_5                      (0x08)
2055 #define MPI2_SAS_NEG_LINK_RATE_3_0                      (0x09)
2056 #define MPI2_SAS_NEG_LINK_RATE_6_0                      (0x0A)
2057 #define MPI25_SAS_NEG_LINK_RATE_12_0                    (0x0B)
2058 #define MPI26_SAS_NEG_LINK_RATE_22_5                    (0x0C)
2059 
2060 
2061 /* values for AttachedPhyInfo fields */
2062 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
2063 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
2064 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
2065 
2066 #define MPI2_SAS_APHYINFO_REASON_MASK                   (0x0000000F)
2067 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
2068 #define MPI2_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
2069 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
2070 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
2071 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
2072 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
2073 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
2074 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
2075 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
2076 
2077 
2078 /* values for PhyInfo fields */
2079 #define MPI2_SAS_PHYINFO_PHY_VACANT                     (0x80000000)
2080 
2081 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
2082 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION      (27)
2083 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE               (0x00000000)
2084 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL              (0x08000000)
2085 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER              (0x10000000)
2086 
2087 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS       (0x04000000)
2088 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT        (0x02000000)
2089 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS               (0x01000000)
2090 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT          (0x00400000)
2091 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS                   (0x00200000)
2092 #define MPI2_SAS_PHYINFO_ZONING_ENABLED                 (0x00100000)
2093 
2094 #define MPI2_SAS_PHYINFO_REASON_MASK                    (0x000F0000)
2095 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
2096 #define MPI2_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
2097 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
2098 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
2099 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
2100 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
2101 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
2102 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
2103 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
2104 
2105 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED         (0x00008000)
2106 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
2107 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
2108 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
2109 
2110 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME      (0x00000F00)
2111 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME     (8)
2112 
2113 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE         (0x000000F0)
2114 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING                 (0x00000000)
2115 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING            (0x00000010)
2116 #define MPI2_SAS_PHYINFO_TABLE_ROUTING                  (0x00000020)
2117 
2118 
2119 /* values for SAS ProgrammedLinkRate fields */
2120 #define MPI2_SAS_PRATE_MAX_RATE_MASK                    (0xF0)
2121 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
2122 #define MPI2_SAS_PRATE_MAX_RATE_1_5                     (0x80)
2123 #define MPI2_SAS_PRATE_MAX_RATE_3_0                     (0x90)
2124 #define MPI2_SAS_PRATE_MAX_RATE_6_0                     (0xA0)
2125 #define MPI25_SAS_PRATE_MAX_RATE_12_0                   (0xB0)
2126 #define MPI26_SAS_PRATE_MAX_RATE_22_5                   (0xC0)
2127 #define MPI2_SAS_PRATE_MIN_RATE_MASK                    (0x0F)
2128 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
2129 #define MPI2_SAS_PRATE_MIN_RATE_1_5                     (0x08)
2130 #define MPI2_SAS_PRATE_MIN_RATE_3_0                     (0x09)
2131 #define MPI2_SAS_PRATE_MIN_RATE_6_0                     (0x0A)
2132 #define MPI25_SAS_PRATE_MIN_RATE_12_0                   (0x0B)
2133 #define MPI26_SAS_PRATE_MIN_RATE_22_5                   (0x0C)
2134 
2135 
2136 /* values for SAS HwLinkRate fields */
2137 #define MPI2_SAS_HWRATE_MAX_RATE_MASK                   (0xF0)
2138 #define MPI2_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
2139 #define MPI2_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
2140 #define MPI2_SAS_HWRATE_MAX_RATE_6_0                    (0xA0)
2141 #define MPI25_SAS_HWRATE_MAX_RATE_12_0                  (0xB0)
2142 #define MPI26_SAS_HWRATE_MAX_RATE_22_5                  (0xC0)
2143 #define MPI2_SAS_HWRATE_MIN_RATE_MASK                   (0x0F)
2144 #define MPI2_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
2145 #define MPI2_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
2146 #define MPI2_SAS_HWRATE_MIN_RATE_6_0                    (0x0A)
2147 #define MPI25_SAS_HWRATE_MIN_RATE_12_0                  (0x0B)
2148 #define MPI26_SAS_HWRATE_MIN_RATE_22_5                  (0x0C)
2149 
2150 
2151 
2152 /****************************************************************************
2153 *   SAS IO Unit Config Pages
2154 ****************************************************************************/
2155 
2156 /* SAS IO Unit Page 0 */
2157 
2158 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
2159 {
2160     U8          Port;                   /* 0x00 */
2161     U8          PortFlags;              /* 0x01 */
2162     U8          PhyFlags;               /* 0x02 */
2163     U8          NegotiatedLinkRate;     /* 0x03 */
2164     U32         ControllerPhyDeviceInfo;/* 0x04 */
2165     U16         AttachedDevHandle;      /* 0x08 */
2166     U16         ControllerDevHandle;    /* 0x0A */
2167     U32         DiscoveryStatus;        /* 0x0C */
2168     U32         Reserved;               /* 0x10 */
2169 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
2170   Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
2171 
2172 /*
2173  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2174  * one and check the value returned for NumPhys at runtime.
2175  */
2176 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
2177 #define MPI2_SAS_IOUNIT0_PHY_MAX        (1)
2178 #endif
2179 
2180 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
2181 {
2182     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
2183     U32                                 Reserved1;                          /* 0x08 */
2184     U8                                  NumPhys;                            /* 0x0C */
2185     U8                                  Reserved2;                          /* 0x0D */
2186     U16                                 Reserved3;                          /* 0x0E */
2187     MPI2_SAS_IO_UNIT0_PHY_DATA          PhyData[MPI2_SAS_IOUNIT0_PHY_MAX];  /* 0x10 */
2188 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
2189   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
2190   Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
2191 
2192 #define MPI2_SASIOUNITPAGE0_PAGEVERSION                     (0x05)
2193 
2194 /* values for SAS IO Unit Page 0 PortFlags */
2195 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS     (0x08)
2196 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG          (0x01)
2197 
2198 /* values for SAS IO Unit Page 0 PhyFlags */
2199 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT       (0x40)
2200 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT       (0x20)
2201 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED             (0x10)
2202 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED               (0x08)
2203 
2204 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2205 
2206 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2207 
2208 /* values for SAS IO Unit Page 0 DiscoveryStatus */
2209 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
2210 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
2211 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED               (0x20000000)
2212 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
2213 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR             (0x08000000)
2214 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
2215 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
2216 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN                (0x00002000)
2217 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
2218 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
2219 #define MPI2_SASIOUNIT0_DS_TABLE_LINK                       (0x00000400)
2220 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
2221 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
2222 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
2223 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
2224 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
2225 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
2226 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
2227 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
2228 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
2229 
2230 
2231 /* SAS IO Unit Page 1 */
2232 
2233 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
2234 {
2235     U8          Port;                       /* 0x00 */
2236     U8          PortFlags;                  /* 0x01 */
2237     U8          PhyFlags;                   /* 0x02 */
2238     U8          MaxMinLinkRate;             /* 0x03 */
2239     U32         ControllerPhyDeviceInfo;    /* 0x04 */
2240     U16         MaxTargetPortConnectTime;   /* 0x08 */
2241     U16         Reserved1;                  /* 0x0A */
2242 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2243   Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
2244 
2245 /*
2246  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2247  * one and check the value returned for NumPhys at runtime.
2248  */
2249 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2250 #define MPI2_SAS_IOUNIT1_PHY_MAX        (1)
2251 #endif
2252 
2253 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
2254 {
2255     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
2256     U16                                 ControlFlags;                       /* 0x08 */
2257     U16                                 SASNarrowMaxQueueDepth;             /* 0x0A */
2258     U16                                 AdditionalControlFlags;             /* 0x0C */
2259     U16                                 SASWideMaxQueueDepth;               /* 0x0E */
2260     U8                                  NumPhys;                            /* 0x10 */
2261     U8                                  SATAMaxQDepth;                      /* 0x11 */
2262     U8                                  ReportDeviceMissingDelay;           /* 0x12 */
2263     U8                                  IODeviceMissingDelay;               /* 0x13 */
2264     MPI2_SAS_IO_UNIT1_PHY_DATA          PhyData[MPI2_SAS_IOUNIT1_PHY_MAX];  /* 0x14 */
2265 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
2266   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2267   Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
2268 
2269 #define MPI2_SASIOUNITPAGE1_PAGEVERSION     (0x09)
2270 
2271 /* values for SAS IO Unit Page 1 ControlFlags */
2272 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST                    (0x8000)
2273 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX                        (0x4000)
2274 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX                        (0x2000) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */
2275 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
2276 
2277 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT                    (0x0600)
2278 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT                   (9)
2279 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH                    (0x0)
2280 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT                     (0x1)
2281 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT                    (0x2)
2282 
2283 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
2284 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
2285 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
2286 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
2287 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
2288 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
2289 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
2290 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION                   (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */
2291 
2292 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
2293 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT                 (0x0100)
2294 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
2295 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
2296 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
2297 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
2298 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
2299 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
2300 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
2301 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
2302 
2303 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2304 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK                 (0x7F)
2305 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16                      (0x80)
2306 
2307 /* values for SAS IO Unit Page 1 PortFlags */
2308 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
2309 
2310 /* values for SAS IO Unit Page 1 PhyFlags */
2311 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT               (0x40)
2312 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT               (0x20)
2313 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE                      (0x10)
2314 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
2315 
2316 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
2317 #define MPI2_SASIOUNIT1_MAX_RATE_MASK                               (0xF0)
2318 #define MPI2_SASIOUNIT1_MAX_RATE_1_5                                (0x80)
2319 #define MPI2_SASIOUNIT1_MAX_RATE_3_0                                (0x90)
2320 #define MPI2_SASIOUNIT1_MAX_RATE_6_0                                (0xA0)
2321 #define MPI25_SASIOUNIT1_MAX_RATE_12_0                              (0xB0)
2322 #define MPI26_SASIOUNIT1_MAX_RATE_22_5                              (0xC0)
2323 #define MPI2_SASIOUNIT1_MIN_RATE_MASK                               (0x0F)
2324 #define MPI2_SASIOUNIT1_MIN_RATE_1_5                                (0x08)
2325 #define MPI2_SASIOUNIT1_MIN_RATE_3_0                                (0x09)
2326 #define MPI2_SASIOUNIT1_MIN_RATE_6_0                                (0x0A)
2327 #define MPI25_SASIOUNIT1_MIN_RATE_12_0                              (0x0B)
2328 #define MPI26_SASIOUNIT1_MIN_RATE_22_5                              (0x0C)
2329 
2330 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2331 
2332 
2333 /* SAS IO Unit Page 4 (for MPI v2.5 and earlier) */
2334 
2335 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
2336 {
2337     U8          MaxTargetSpinup;            /* 0x00 */
2338     U8          SpinupDelay;                /* 0x01 */
2339     U8          SpinupFlags;                /* 0x02 */
2340     U8          Reserved1;                  /* 0x03 */
2341 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2342   Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
2343 
2344 /* defines for SAS IO Unit Page 4 SpinupFlags */
2345 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG         (0x01)
2346 
2347 
2348 /*
2349  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2350  * one and check the value returned for NumPhys at runtime.
2351  */
2352 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2353 #define MPI2_SAS_IOUNIT4_PHY_MAX        (4)
2354 #endif
2355 
2356 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
2357 {
2358     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                         /* 0x00 */
2359     MPI2_SAS_IOUNIT4_SPINUP_GROUP       SpinupGroupParameters[4];       /* 0x08 */
2360     U32                                 Reserved1;                      /* 0x18 */
2361     U32                                 Reserved2;                      /* 0x1C */
2362     U32                                 Reserved3;                      /* 0x20 */
2363     U8                                  BootDeviceWaitTime;             /* 0x24 */
2364     U8                                  SATADeviceWaitTime;             /* 0x25 */
2365     U16                                 Reserved5;                      /* 0x26 */
2366     U8                                  NumPhys;                        /* 0x28 */
2367     U8                                  PEInitialSpinupDelay;           /* 0x29 */
2368     U8                                  PEReplyDelay;                   /* 0x2A */
2369     U8                                  Flags;                          /* 0x2B */
2370     U8                                  PHY[MPI2_SAS_IOUNIT4_PHY_MAX];  /* 0x2C */
2371 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2372   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2373   Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
2374 
2375 #define MPI2_SASIOUNITPAGE4_PAGEVERSION     (0x02)
2376 
2377 /* defines for Flags field */
2378 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE               (0x01)
2379 
2380 /* defines for PHY field */
2381 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK               (0x03)
2382 
2383 
2384 /* SAS IO Unit Page 5 */
2385 
2386 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2387 {
2388     U8          ControlFlags;               /* 0x00 */
2389     U8          PortWidthModGroup;          /* 0x01 */
2390     U16         InactivityTimerExponent;    /* 0x02 */
2391     U8          SATAPartialTimeout;         /* 0x04 */
2392     U8          Reserved2;                  /* 0x05 */
2393     U8          SATASlumberTimeout;         /* 0x06 */
2394     U8          Reserved3;                  /* 0x07 */
2395     U8          SASPartialTimeout;          /* 0x08 */
2396     U8          Reserved4;                  /* 0x09 */
2397     U8          SASSlumberTimeout;          /* 0x0A */
2398     U8          Reserved5;                  /* 0x0B */
2399 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2400   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2401   Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
2402 
2403 /* defines for ControlFlags field */
2404 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
2405 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
2406 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
2407 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
2408 
2409 /* defines for PortWidthModeGroup field */
2410 #define MPI2_SASIOUNIT5_PWMG_DISABLE                    (0xFF)
2411 
2412 /* defines for InactivityTimerExponent field */
2413 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER            (0x7000)
2414 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER           (12)
2415 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL            (0x0700)
2416 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL           (8)
2417 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER           (0x0070)
2418 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER          (4)
2419 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL           (0x0007)
2420 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL          (0)
2421 
2422 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS                 (7)
2423 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND                  (6)
2424 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS        (5)
2425 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS            (4)
2426 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND             (3)
2427 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS        (2)
2428 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS            (1)
2429 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND             (0)
2430 
2431 /*
2432  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2433  * one and check the value returned for NumPhys at runtime.
2434  */
2435 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2436 #define MPI2_SAS_IOUNIT5_PHY_MAX        (1)
2437 #endif
2438 
2439 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5
2440 {
2441     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
2442     U8                                  NumPhys;                            /* 0x08 */
2443     U8                                  Reserved1;                          /* 0x09 */
2444     U16                                 Reserved2;                          /* 0x0A */
2445     U32                                 Reserved3;                          /* 0x0C */
2446     MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS   SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];  /* 0x10 */
2447 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2448   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2449   Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2450 
2451 #define MPI2_SASIOUNITPAGE5_PAGEVERSION     (0x01)
2452 
2453 
2454 /* SAS IO Unit Page 6 */
2455 
2456 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2457 {
2458     U8          CurrentStatus;              /* 0x00 */
2459     U8          CurrentModulation;          /* 0x01 */
2460     U8          CurrentUtilization;         /* 0x02 */
2461     U8          Reserved1;                  /* 0x03 */
2462     U32         Reserved2;                  /* 0x04 */
2463 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2464   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2465   Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2466   MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2467 
2468 /* defines for CurrentStatus field */
2469 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE                      (0x00)
2470 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED                     (0x01)
2471 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG                   (0x02)
2472 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN                        (0x03)
2473 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY                 (0x04)
2474 #define MPI2_SASIOUNIT6_STATUS_INACTIVE                         (0x05)
2475 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT                    (0x06)
2476 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST                      (0x07)
2477 
2478 /* defines for CurrentModulation field */
2479 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT                   (0x00)
2480 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT                   (0x01)
2481 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT                   (0x02)
2482 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT                  (0x03)
2483 
2484 /*
2485  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2486  * one and check the value returned for NumGroups at runtime.
2487  */
2488 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2489 #define MPI2_SAS_IOUNIT6_GROUP_MAX      (1)
2490 #endif
2491 
2492 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6
2493 {
2494     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2495     U32                                 Reserved1;                  /* 0x08 */
2496     U32                                 Reserved2;                  /* 0x0C */
2497     U8                                  NumGroups;                  /* 0x10 */
2498     U8                                  Reserved3;                  /* 0x11 */
2499     U16                                 Reserved4;                  /* 0x12 */
2500     MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2501         PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2502 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2503   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2504   Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2505 
2506 #define MPI2_SASIOUNITPAGE6_PAGEVERSION     (0x00)
2507 
2508 
2509 /* SAS IO Unit Page 7 */
2510 
2511 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2512 {
2513     U8          Flags;                      /* 0x00 */
2514     U8          Reserved1;                  /* 0x01 */
2515     U16         Reserved2;                  /* 0x02 */
2516     U8          Threshold75Pct;             /* 0x04 */
2517     U8          Threshold50Pct;             /* 0x05 */
2518     U8          Threshold25Pct;             /* 0x06 */
2519     U8          Reserved3;                  /* 0x07 */
2520 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2521   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2522   Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2523   MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2524 
2525 /* defines for Flags field */
2526 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION  (0x01)
2527 
2528 
2529 /*
2530  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2531  * one and check the value returned for NumGroups at runtime.
2532  */
2533 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2534 #define MPI2_SAS_IOUNIT7_GROUP_MAX      (1)
2535 #endif
2536 
2537 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7
2538 {
2539     MPI2_CONFIG_EXTENDED_PAGE_HEADER            Header;             /* 0x00 */
2540     U8                                          SamplingInterval;   /* 0x08 */
2541     U8                                          WindowLength;       /* 0x09 */
2542     U16                                         Reserved1;          /* 0x0A */
2543     U32                                         Reserved2;          /* 0x0C */
2544     U32                                         Reserved3;          /* 0x10 */
2545     U8                                          NumGroups;          /* 0x14 */
2546     U8                                          Reserved4;          /* 0x15 */
2547     U16                                         Reserved5;          /* 0x16 */
2548     MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2549         PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2550 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2551   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2552   Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2553 
2554 #define MPI2_SASIOUNITPAGE7_PAGEVERSION     (0x00)
2555 
2556 
2557 /* SAS IO Unit Page 8 */
2558 
2559 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8
2560 {
2561     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                         /* 0x00 */
2562     U32                                 Reserved1;                      /* 0x08 */
2563     U32                                 PowerManagementCapabilities;    /* 0x0C */
2564     U8                                  TxRxSleepStatus;                /* 0x10 */ /* reserved in MPI 2.0 */
2565     U8                                  Reserved2;                      /* 0x11 */
2566     U16                                 Reserved3;                      /* 0x12 */
2567 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2568   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2569   Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2570 
2571 #define MPI2_SASIOUNITPAGE8_PAGEVERSION     (0x00)
2572 
2573 /* defines for PowerManagementCapabilities field */
2574 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD          (0x00001000)
2575 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
2576 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
2577 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
2578 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
2579 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD        (0x00000010)
2580 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
2581 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
2582 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
2583 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
2584 
2585 /* defines for TxRxSleepStatus field */
2586 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED          (0x00)
2587 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED           (0x01)
2588 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE               (0x02)
2589 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN             (0x03)
2590 
2591 
2592 
2593 /* SAS IO Unit Page 16 */
2594 
2595 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16
2596 {
2597     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
2598     U64                                 TimeStamp;                          /* 0x08 */
2599     U32                                 Reserved1;                          /* 0x10 */
2600     U32                                 Reserved2;                          /* 0x14 */
2601     U32                                 FastPathPendedRequests;             /* 0x18 */
2602     U32                                 FastPathUnPendedRequests;           /* 0x1C */
2603     U32                                 FastPathHostRequestStarts;          /* 0x20 */
2604     U32                                 FastPathFirmwareRequestStarts;      /* 0x24 */
2605     U32                                 FastPathHostCompletions;            /* 0x28 */
2606     U32                                 FastPathFirmwareCompletions;        /* 0x2C */
2607     U32                                 NonFastPathRequestStarts;           /* 0x30 */
2608     U32                                 NonFastPathHostCompletions;         /* 0x30 */
2609 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2610   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2611   Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t;
2612 
2613 #define MPI2_SASIOUNITPAGE16_PAGEVERSION    (0x00)
2614 
2615 
2616 /****************************************************************************
2617 *   SAS Expander Config Pages
2618 ****************************************************************************/
2619 
2620 /* SAS Expander Page 0 */
2621 
2622 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2623 {
2624     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2625     U8                                  PhysicalPort;               /* 0x08 */
2626     U8                                  ReportGenLength;            /* 0x09 */
2627     U16                                 EnclosureHandle;            /* 0x0A */
2628     U64                                 SASAddress;                 /* 0x0C */
2629     U32                                 DiscoveryStatus;            /* 0x14 */
2630     U16                                 DevHandle;                  /* 0x18 */
2631     U16                                 ParentDevHandle;            /* 0x1A */
2632     U16                                 ExpanderChangeCount;        /* 0x1C */
2633     U16                                 ExpanderRouteIndexes;       /* 0x1E */
2634     U8                                  NumPhys;                    /* 0x20 */
2635     U8                                  SASLevel;                   /* 0x21 */
2636     U16                                 Flags;                      /* 0x22 */
2637     U16                                 STPBusInactivityTimeLimit;  /* 0x24 */
2638     U16                                 STPMaxConnectTimeLimit;     /* 0x26 */
2639     U16                                 STP_SMP_NexusLossTime;      /* 0x28 */
2640     U16                                 MaxNumRoutedSasAddresses;   /* 0x2A */
2641     U64                                 ActiveZoneManagerSASAddress;/* 0x2C */
2642     U16                                 ZoneLockInactivityLimit;    /* 0x34 */
2643     U16                                 Reserved1;                  /* 0x36 */
2644     U8                                  TimeToReducedFunc;          /* 0x38 */
2645     U8                                  InitialTimeToReducedFunc;   /* 0x39 */
2646     U8                                  MaxReducedFuncTime;         /* 0x3A */
2647     U8                                  Reserved2;                  /* 0x3B */
2648 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2649   Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2650 
2651 #define MPI2_SASEXPANDER0_PAGEVERSION       (0x06)
2652 
2653 /* values for SAS Expander Page 0 DiscoveryStatus field */
2654 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED         (0x80000000)
2655 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED          (0x40000000)
2656 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED            (0x20000000)
2657 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED          (0x10000000)
2658 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR          (0x08000000)
2659 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2660 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE         (0x00004000)
2661 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN             (0x00002000)
2662 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK     (0x00001000)
2663 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE            (0x00000800)
2664 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK                    (0x00000400)
2665 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK              (0x00000200)
2666 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR                 (0x00000100)
2667 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED           (0x00000080)
2668 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST               (0x00000040)
2669 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES             (0x00000020)
2670 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT                   (0x00000010)
2671 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS                (0x00000004)
2672 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE          (0x00000002)
2673 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED                 (0x00000001)
2674 
2675 /* values for SAS Expander Page 0 Flags field */
2676 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY      (0x2000)
2677 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED                (0x1000)
2678 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES    (0x0800)
2679 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES     (0x0400)
2680 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT             (0x0200)
2681 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING             (0x0100)
2682 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT     (0x0080)
2683 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE       (0x0010)
2684 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG              (0x0004)
2685 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS         (0x0002)
2686 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG         (0x0001)
2687 
2688 
2689 /* SAS Expander Page 1 */
2690 
2691 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2692 {
2693     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2694     U8                                  PhysicalPort;               /* 0x08 */
2695     U8                                  Reserved1;                  /* 0x09 */
2696     U16                                 Reserved2;                  /* 0x0A */
2697     U8                                  NumPhys;                    /* 0x0C */
2698     U8                                  Phy;                        /* 0x0D */
2699     U16                                 NumTableEntriesProgrammed;  /* 0x0E */
2700     U8                                  ProgrammedLinkRate;         /* 0x10 */
2701     U8                                  HwLinkRate;                 /* 0x11 */
2702     U16                                 AttachedDevHandle;          /* 0x12 */
2703     U32                                 PhyInfo;                    /* 0x14 */
2704     U32                                 AttachedDeviceInfo;         /* 0x18 */
2705     U16                                 ExpanderDevHandle;          /* 0x1C */
2706     U8                                  ChangeCount;                /* 0x1E */
2707     U8                                  NegotiatedLinkRate;         /* 0x1F */
2708     U8                                  PhyIdentifier;              /* 0x20 */
2709     U8                                  AttachedPhyIdentifier;      /* 0x21 */
2710     U8                                  Reserved3;                  /* 0x22 */
2711     U8                                  DiscoveryInfo;              /* 0x23 */
2712     U32                                 AttachedPhyInfo;            /* 0x24 */
2713     U8                                  ZoneGroup;                  /* 0x28 */
2714     U8                                  SelfConfigStatus;           /* 0x29 */
2715     U16                                 Reserved4;                  /* 0x2A */
2716 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2717   Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2718 
2719 #define MPI2_SASEXPANDER1_PAGEVERSION       (0x02)
2720 
2721 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2722 
2723 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2724 
2725 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2726 
2727 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2728 
2729 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2730 
2731 /* values for SAS Expander Page 1 DiscoveryInfo field */
2732 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED    (0x04)
2733 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE  (0x02)
2734 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES  (0x01)
2735 
2736 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2737 
2738 
2739 /****************************************************************************
2740 *   SAS Device Config Pages
2741 ****************************************************************************/
2742 
2743 /* SAS Device Page 0 */
2744 
2745 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2746 {
2747     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2748     U16                                 Slot;                   /* 0x08 */
2749     U16                                 EnclosureHandle;        /* 0x0A */
2750     U64                                 SASAddress;             /* 0x0C */
2751     U16                                 ParentDevHandle;        /* 0x14 */
2752     U8                                  PhyNum;                 /* 0x16 */
2753     U8                                  AccessStatus;           /* 0x17 */
2754     U16                                 DevHandle;              /* 0x18 */
2755     U8                                  AttachedPhyIdentifier;  /* 0x1A */
2756     U8                                  ZoneGroup;              /* 0x1B */
2757     U32                                 DeviceInfo;             /* 0x1C */
2758     U16                                 Flags;                  /* 0x20 */
2759     U8                                  PhysicalPort;           /* 0x22 */
2760     U8                                  MaxPortConnections;     /* 0x23 */
2761     U64                                 DeviceName;             /* 0x24 */
2762     U8                                  PortGroups;             /* 0x2C */
2763     U8                                  DmaGroup;               /* 0x2D */
2764     U8                                  ControlGroup;           /* 0x2E */
2765     U8                                  EnclosureLevel;         /* 0x2F */
2766     U8                                  ConnectorName[4];       /* 0x30 */
2767     U32                                 Reserved3;              /* 0x34 */
2768 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2769   Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2770 
2771 #define MPI2_SASDEVICE0_PAGEVERSION         (0x09)
2772 
2773 /* values for SAS Device Page 0 AccessStatus field */
2774 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS                  (0x00)
2775 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED           (0x01)
2776 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED     (0x02)
2777 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT  (0x03)
2778 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION  (0x04)
2779 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE      (0x05)
2780 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE  (0x06)
2781 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED             (0x07)
2782 /* specific values for SATA Init failures */
2783 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN                (0x10)
2784 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT   (0x11)
2785 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG                   (0x12)
2786 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION         (0x13)
2787 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER            (0x14)
2788 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN                 (0x15)
2789 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN                (0x16)
2790 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN                (0x17)
2791 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION       (0x18)
2792 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE        (0x19)
2793 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX                    (0x1F)
2794 
2795 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2796 
2797 /* values for SAS Device Page 0 Flags field */
2798 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE          (0x8000)
2799 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH           (0x4000)
2800 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE           (0x2000)
2801 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE           (0x1000)
2802 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE           (0x0800)
2803 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY     (0x0400)
2804 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE             (0x0200)
2805 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE           (0x0100)
2806 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED     (0x0080)
2807 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED         (0x0040)
2808 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED           (0x0020)
2809 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED           (0x0010)
2810 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH         (0x0008)
2811 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE              (0x0004)
2812 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID             (0x0002)
2813 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2814 
2815 /* SAS Device Page 1 */
2816 
2817 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2818 {
2819     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2820     U32                                 Reserved1;              /* 0x08 */
2821     U64                                 SASAddress;             /* 0x0C */
2822     U32                                 Reserved2;              /* 0x14 */
2823     U16                                 DevHandle;              /* 0x18 */
2824     U16                                 Reserved3;              /* 0x1A */
2825     U8                                  InitialRegDeviceFIS[20];/* 0x1C */
2826 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2827   Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2828 
2829 #define MPI2_SASDEVICE1_PAGEVERSION         (0x01)
2830 
2831 
2832 /****************************************************************************
2833 *   SAS PHY Config Pages
2834 ****************************************************************************/
2835 
2836 /* SAS PHY Page 0 */
2837 
2838 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2839 {
2840     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2841     U16                                 OwnerDevHandle;         /* 0x08 */
2842     U16                                 Reserved1;              /* 0x0A */
2843     U16                                 AttachedDevHandle;      /* 0x0C */
2844     U8                                  AttachedPhyIdentifier;  /* 0x0E */
2845     U8                                  Reserved2;              /* 0x0F */
2846     U32                                 AttachedPhyInfo;        /* 0x10 */
2847     U8                                  ProgrammedLinkRate;     /* 0x14 */
2848     U8                                  HwLinkRate;             /* 0x15 */
2849     U8                                  ChangeCount;            /* 0x16 */
2850     U8                                  Flags;                  /* 0x17 */
2851     U32                                 PhyInfo;                /* 0x18 */
2852     U8                                  NegotiatedLinkRate;     /* 0x1C */
2853     U8                                  Reserved3;              /* 0x1D */
2854     U16                                 Reserved4;              /* 0x1E */
2855 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2856   Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2857 
2858 #define MPI2_SASPHY0_PAGEVERSION            (0x03)
2859 
2860 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2861 
2862 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2863 
2864 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2865 
2866 /* values for SAS PHY Page 0 Flags field */
2867 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC             (0x01)
2868 
2869 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2870 
2871 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2872 
2873 
2874 /* SAS PHY Page 1 */
2875 
2876 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2877 {
2878     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2879     U32                                 Reserved1;                  /* 0x08 */
2880     U32                                 InvalidDwordCount;          /* 0x0C */
2881     U32                                 RunningDisparityErrorCount; /* 0x10 */
2882     U32                                 LossDwordSynchCount;        /* 0x14 */
2883     U32                                 PhyResetProblemCount;       /* 0x18 */
2884 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2885   Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2886 
2887 #define MPI2_SASPHY1_PAGEVERSION            (0x01)
2888 
2889 
2890 /* SAS PHY Page 2 */
2891 
2892 typedef struct _MPI2_SASPHY2_PHY_EVENT
2893 {
2894     U8          PhyEventCode;       /* 0x00 */
2895     U8          Reserved1;          /* 0x01 */
2896     U16         Reserved2;          /* 0x02 */
2897     U32         PhyEventInfo;       /* 0x04 */
2898 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2899   Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2900 
2901 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2902 
2903 
2904 /*
2905  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2906  * one and check the value returned for NumPhyEvents at runtime.
2907  */
2908 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2909 #define MPI2_SASPHY2_PHY_EVENT_MAX      (1)
2910 #endif
2911 
2912 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2
2913 {
2914     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2915     U32                                 Reserved1;                  /* 0x08 */
2916     U8                                  NumPhyEvents;               /* 0x0C */
2917     U8                                  Reserved2;                  /* 0x0D */
2918     U16                                 Reserved3;                  /* 0x0E */
2919     MPI2_SASPHY2_PHY_EVENT              PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */
2920 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2921   Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2922 
2923 #define MPI2_SASPHY2_PAGEVERSION            (0x00)
2924 
2925 
2926 /* SAS PHY Page 3 */
2927 
2928 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG
2929 {
2930     U8          PhyEventCode;       /* 0x00 */
2931     U8          Reserved1;          /* 0x01 */
2932     U16         Reserved2;          /* 0x02 */
2933     U8          CounterType;        /* 0x04 */
2934     U8          ThresholdWindow;    /* 0x05 */
2935     U8          TimeUnits;          /* 0x06 */
2936     U8          Reserved3;          /* 0x07 */
2937     U32         EventThreshold;     /* 0x08 */
2938     U16         ThresholdFlags;     /* 0x0C */
2939     U16         Reserved4;          /* 0x0E */
2940 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2941   Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2942 
2943 /* values for PhyEventCode field */
2944 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
2945 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
2946 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
2947 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
2948 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
2949 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
2950 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
2951 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
2952 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
2953 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
2954 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
2955 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
2956 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
2957 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
2958 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
2959 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
2960 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
2961 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION                  (0x2A)
2962 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2B)
2963 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2C)
2964 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2D)
2965 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2E)
2966 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
2967 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
2968 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
2969 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
2970 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
2971 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
2972 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
2973 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
2974 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
2975 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
2976 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
2977 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
2978 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xD0)
2979 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xD1)
2980 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP                      (0xD2)
2981 /* Following codes are product specific and in MPI v2.6 and later */
2982 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME             (0xD3)
2983 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME    (0xD4)
2984 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME                 (0xD5)
2985 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT       (0xD6)
2986 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START               (0xD7)
2987 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT        (0xD8)
2988 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN           (0xD9)
2989 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE        (0xDA)
2990 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE       (0xDB)
2991 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE        (0xDC)
2992 
2993 /* values for the CounterType field */
2994 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
2995 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
2996 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
2997 
2998 /* values for the TimeUnits field */
2999 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
3000 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
3001 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
3002 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
3003 
3004 /* values for the ThresholdFlags field */
3005 #define MPI2_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
3006 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
3007 
3008 /*
3009  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3010  * one and check the value returned for NumPhyEvents at runtime.
3011  */
3012 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
3013 #define MPI2_SASPHY3_PHY_EVENT_MAX      (1)
3014 #endif
3015 
3016 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3
3017 {
3018     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3019     U32                                 Reserved1;                  /* 0x08 */
3020     U8                                  NumPhyEvents;               /* 0x0C */
3021     U8                                  Reserved2;                  /* 0x0D */
3022     U16                                 Reserved3;                  /* 0x0E */
3023     MPI2_SASPHY3_PHY_EVENT_CONFIG       PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
3024 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
3025   Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
3026 
3027 #define MPI2_SASPHY3_PAGEVERSION            (0x00)
3028 
3029 
3030 /* SAS PHY Page 4 */
3031 
3032 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4
3033 {
3034     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3035     U16                                 Reserved1;                  /* 0x08 */
3036     U8                                  Reserved2;                  /* 0x0A */
3037     U8                                  Flags;                      /* 0x0B */
3038     U8                                  InitialFrame[28];           /* 0x0C */
3039 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
3040   Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
3041 
3042 #define MPI2_SASPHY4_PAGEVERSION            (0x00)
3043 
3044 /* values for the Flags field */
3045 #define MPI2_SASPHY4_FLAGS_FRAME_VALID        (0x02)
3046 #define MPI2_SASPHY4_FLAGS_SATA_FRAME         (0x01)
3047 
3048 
3049 
3050 
3051 /****************************************************************************
3052 *   SAS Port Config Pages
3053 ****************************************************************************/
3054 
3055 /* SAS Port Page 0 */
3056 
3057 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
3058 {
3059     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3060     U8                                  PortNumber;                 /* 0x08 */
3061     U8                                  PhysicalPort;               /* 0x09 */
3062     U8                                  PortWidth;                  /* 0x0A */
3063     U8                                  PhysicalPortWidth;          /* 0x0B */
3064     U8                                  ZoneGroup;                  /* 0x0C */
3065     U8                                  Reserved1;                  /* 0x0D */
3066     U16                                 Reserved2;                  /* 0x0E */
3067     U64                                 SASAddress;                 /* 0x10 */
3068     U32                                 DeviceInfo;                 /* 0x18 */
3069     U32                                 Reserved3;                  /* 0x1C */
3070     U32                                 Reserved4;                  /* 0x20 */
3071 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
3072   Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
3073 
3074 #define MPI2_SASPORT0_PAGEVERSION           (0x00)
3075 
3076 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
3077 
3078 
3079 /****************************************************************************
3080 *   SAS Enclosure Config Pages
3081 ****************************************************************************/
3082 
3083 /* SAS Enclosure Page 0, Enclosure Page 0 */
3084 
3085 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
3086 {
3087     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3088     U32                                 Reserved1;                  /* 0x08 */
3089     U64                                 EnclosureLogicalID;         /* 0x0C */
3090     U16                                 Flags;                      /* 0x14 */
3091     U16                                 EnclosureHandle;            /* 0x16 */
3092     U16                                 NumSlots;                   /* 0x18 */
3093     U16                                 StartSlot;                  /* 0x1A */
3094     U8                                  Reserved2;                  /* 0x1C */
3095     U8                                  EnclosureLevel;             /* 0x1D */
3096     U16                                 SEPDevHandle;               /* 0x1E */
3097     U32                                 Reserved3;                  /* 0x20 */
3098     U32                                 Reserved4;                  /* 0x24 */
3099 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3100   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3101   Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t,
3102   MPI26_CONFIG_PAGE_ENCLOSURE_0,
3103   MPI2_POINTER PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0,
3104   Mpi26EnclosurePage0_t, MPI2_POINTER pMpi26EnclosurePage0_t;
3105 
3106 #define MPI2_SASENCLOSURE0_PAGEVERSION      (0x04)
3107 
3108 /* values for SAS Enclosure Page 0 Flags field */
3109 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID      (0x0010)
3110 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK              (0x000F)
3111 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN           (0x0000)
3112 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES           (0x0001)
3113 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO         (0x0002)
3114 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO         (0x0003)
3115 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE     (0x0004)
3116 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO          (0x0005)
3117 
3118 #define MPI26_ENCLOSURE0_PAGEVERSION        (0x04)
3119 
3120 /* Values for Enclosure Page 0 Flags field */
3121 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID         (0x0010)
3122 #define MPI26_ENCLS0_FLAGS_MNG_MASK                 (0x000F)
3123 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN              (0x0000)
3124 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES              (0x0001)
3125 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO            (0x0002)
3126 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO            (0x0003)
3127 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE        (0x0004)
3128 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO             (0x0005)
3129 
3130 /****************************************************************************
3131 *   Log Config Page
3132 ****************************************************************************/
3133 
3134 /* Log Page 0 */
3135 
3136 /*
3137  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3138  * one and check the value returned for NumLogEntries at runtime.
3139  */
3140 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
3141 #define MPI2_LOG_0_NUM_LOG_ENTRIES          (1)
3142 #endif
3143 
3144 #define MPI2_LOG_0_LOG_DATA_LENGTH          (0x1C)
3145 
3146 typedef struct _MPI2_LOG_0_ENTRY
3147 {
3148     U64         TimeStamp;                          /* 0x00 */
3149     U32         Reserved1;                          /* 0x08 */
3150     U16         LogSequence;                        /* 0x0C */
3151     U16         LogEntryQualifier;                  /* 0x0E */
3152     U8          VP_ID;                              /* 0x10 */
3153     U8          VF_ID;                              /* 0x11 */
3154     U16         Reserved2;                          /* 0x12 */
3155     U8          LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
3156 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
3157   Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
3158 
3159 /* values for Log Page 0 LogEntry LogEntryQualifier field */
3160 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED          (0x0000)
3161 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET        (0x0001)
3162 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE      (0x0002)
3163 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC    (0x8000)
3164 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC    (0xFFFF)
3165 
3166 typedef struct _MPI2_CONFIG_PAGE_LOG_0
3167 {
3168     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3169     U32                                 Reserved1;                  /* 0x08 */
3170     U32                                 Reserved2;                  /* 0x0C */
3171     U16                                 NumLogEntries;              /* 0x10 */
3172     U16                                 Reserved3;                  /* 0x12 */
3173     MPI2_LOG_0_ENTRY                    LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
3174 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
3175   Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
3176 
3177 #define MPI2_LOG_0_PAGEVERSION              (0x02)
3178 
3179 
3180 /****************************************************************************
3181 *   RAID Config Page
3182 ****************************************************************************/
3183 
3184 /* RAID Page 0 */
3185 
3186 /*
3187  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3188  * one and check the value returned for NumElements at runtime.
3189  */
3190 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
3191 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS       (1)
3192 #endif
3193 
3194 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
3195 {
3196     U16                     ElementFlags;               /* 0x00 */
3197     U16                     VolDevHandle;               /* 0x02 */
3198     U8                      HotSparePool;               /* 0x04 */
3199     U8                      PhysDiskNum;                /* 0x05 */
3200     U16                     PhysDiskDevHandle;          /* 0x06 */
3201 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3202   MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3203   Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
3204 
3205 /* values for the ElementFlags field */
3206 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE       (0x000F)
3207 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT          (0x0000)
3208 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT   (0x0001)
3209 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT       (0x0002)
3210 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT             (0x0003)
3211 
3212 
3213 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
3214 {
3215     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3216     U8                                  NumHotSpares;               /* 0x08 */
3217     U8                                  NumPhysDisks;               /* 0x09 */
3218     U8                                  NumVolumes;                 /* 0x0A */
3219     U8                                  ConfigNum;                  /* 0x0B */
3220     U32                                 Flags;                      /* 0x0C */
3221     U8                                  ConfigGUID[24];             /* 0x10 */
3222     U32                                 Reserved1;                  /* 0x28 */
3223     U8                                  NumElements;                /* 0x2C */
3224     U8                                  Reserved2;                  /* 0x2D */
3225     U16                                 Reserved3;                  /* 0x2E */
3226     MPI2_RAIDCONFIG0_CONFIG_ELEMENT     ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
3227 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3228   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3229   Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
3230 
3231 #define MPI2_RAIDCONFIG0_PAGEVERSION            (0x00)
3232 
3233 /* values for RAID Configuration Page 0 Flags field */
3234 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG        (0x00000001)
3235 
3236 
3237 /****************************************************************************
3238 *   Driver Persistent Mapping Config Pages
3239 ****************************************************************************/
3240 
3241 /* Driver Persistent Mapping Page 0 */
3242 
3243 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
3244 {
3245     U64                                 PhysicalIdentifier;         /* 0x00 */
3246     U16                                 MappingInformation;         /* 0x08 */
3247     U16                                 DeviceIndex;                /* 0x0A */
3248     U32                                 PhysicalBitsMapping;        /* 0x0C */
3249     U32                                 Reserved1;                  /* 0x10 */
3250 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3251   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3252   Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
3253 
3254 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
3255 {
3256     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3257     MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY  Entry;                      /* 0x08 */
3258 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3259   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3260   Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
3261 
3262 #define MPI2_DRIVERMAPPING0_PAGEVERSION         (0x00)
3263 
3264 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
3265 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK              (0x07F0)
3266 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT             (4)
3267 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK           (0x000F)
3268 
3269 
3270 /****************************************************************************
3271 *   Ethernet Config Pages
3272 ****************************************************************************/
3273 
3274 /* Ethernet Page 0 */
3275 
3276 /* IP address (union of IPv4 and IPv6) */
3277 typedef union _MPI2_ETHERNET_IP_ADDR
3278 {
3279     U32     IPv4Addr;
3280     U32     IPv6Addr[4];
3281 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
3282   Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
3283 
3284 #define MPI2_ETHERNET_HOST_NAME_LENGTH          (32)
3285 
3286 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0
3287 {
3288     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
3289     U8                                  NumInterfaces;          /* 0x08 */
3290     U8                                  Reserved0;              /* 0x09 */
3291     U16                                 Reserved1;              /* 0x0A */
3292     U32                                 Status;                 /* 0x0C */
3293     U8                                  MediaState;             /* 0x10 */
3294     U8                                  Reserved2;              /* 0x11 */
3295     U16                                 Reserved3;              /* 0x12 */
3296     U8                                  MacAddress[6];          /* 0x14 */
3297     U8                                  Reserved4;              /* 0x1A */
3298     U8                                  Reserved5;              /* 0x1B */
3299     MPI2_ETHERNET_IP_ADDR               IpAddress;              /* 0x1C */
3300     MPI2_ETHERNET_IP_ADDR               SubnetMask;             /* 0x2C */
3301     MPI2_ETHERNET_IP_ADDR               GatewayIpAddress;       /* 0x3C */
3302     MPI2_ETHERNET_IP_ADDR               DNS1IpAddress;          /* 0x4C */
3303     MPI2_ETHERNET_IP_ADDR               DNS2IpAddress;          /* 0x5C */
3304     MPI2_ETHERNET_IP_ADDR               DhcpIpAddress;          /* 0x6C */
3305     U8                                  HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3306 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3307   Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
3308 
3309 #define MPI2_ETHERNETPAGE0_PAGEVERSION   (0x00)
3310 
3311 /* values for Ethernet Page 0 Status field */
3312 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE             (0x80000000)
3313 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE             (0x40000000)
3314 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED        (0x20000000)
3315 #define MPI2_ETHPG0_STATUS_DEFAULT_IF               (0x00000100)
3316 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED         (0x00000080)
3317 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED           (0x00000040)
3318 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED             (0x00000020)
3319 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED      (0x00000010)
3320 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED             (0x00000008)
3321 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED             (0x00000004)
3322 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES           (0x00000002)
3323 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED           (0x00000001)
3324 
3325 /* values for Ethernet Page 0 MediaState field */
3326 #define MPI2_ETHPG0_MS_DUPLEX_MASK                  (0x80)
3327 #define MPI2_ETHPG0_MS_HALF_DUPLEX                  (0x00)
3328 #define MPI2_ETHPG0_MS_FULL_DUPLEX                  (0x80)
3329 
3330 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK           (0x07)
3331 #define MPI2_ETHPG0_MS_NOT_CONNECTED                (0x00)
3332 #define MPI2_ETHPG0_MS_10MBIT                       (0x01)
3333 #define MPI2_ETHPG0_MS_100MBIT                      (0x02)
3334 #define MPI2_ETHPG0_MS_1GBIT                        (0x03)
3335 
3336 
3337 /* Ethernet Page 1 */
3338 
3339 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1
3340 {
3341     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
3342     U32                                 Reserved0;              /* 0x08 */
3343     U32                                 Flags;                  /* 0x0C */
3344     U8                                  MediaState;             /* 0x10 */
3345     U8                                  Reserved1;              /* 0x11 */
3346     U16                                 Reserved2;              /* 0x12 */
3347     U8                                  MacAddress[6];          /* 0x14 */
3348     U8                                  Reserved3;              /* 0x1A */
3349     U8                                  Reserved4;              /* 0x1B */
3350     MPI2_ETHERNET_IP_ADDR               StaticIpAddress;        /* 0x1C */
3351     MPI2_ETHERNET_IP_ADDR               StaticSubnetMask;       /* 0x2C */
3352     MPI2_ETHERNET_IP_ADDR               StaticGatewayIpAddress; /* 0x3C */
3353     MPI2_ETHERNET_IP_ADDR               StaticDNS1IpAddress;    /* 0x4C */
3354     MPI2_ETHERNET_IP_ADDR               StaticDNS2IpAddress;    /* 0x5C */
3355     U32                                 Reserved5;              /* 0x6C */
3356     U32                                 Reserved6;              /* 0x70 */
3357     U32                                 Reserved7;              /* 0x74 */
3358     U32                                 Reserved8;              /* 0x78 */
3359     U8                                  HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
3360 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3361   Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
3362 
3363 #define MPI2_ETHERNETPAGE1_PAGEVERSION   (0x00)
3364 
3365 /* values for Ethernet Page 1 Flags field */
3366 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF             (0x00000100)
3367 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD         (0x00000080)
3368 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET              (0x00000040)
3369 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2                (0x00000020)
3370 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT         (0x00000010)
3371 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6                (0x00000008)
3372 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4                (0x00000004)
3373 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES         (0x00000002)
3374 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF              (0x00000001)
3375 
3376 /* values for Ethernet Page 1 MediaState field */
3377 #define MPI2_ETHPG1_MS_DUPLEX_MASK                  (0x80)
3378 #define MPI2_ETHPG1_MS_HALF_DUPLEX                  (0x00)
3379 #define MPI2_ETHPG1_MS_FULL_DUPLEX                  (0x80)
3380 
3381 #define MPI2_ETHPG1_MS_DATA_RATE_MASK               (0x07)
3382 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO               (0x00)
3383 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT             (0x01)
3384 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT            (0x02)
3385 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT              (0x03)
3386 
3387 
3388 /****************************************************************************
3389 *   Extended Manufacturing Config Pages
3390 ****************************************************************************/
3391 
3392 /*
3393  * Generic structure to use for product-specific extended manufacturing pages
3394  * (currently Extended Manufacturing Page 40 through Extended Manufacturing
3395  * Page 60).
3396  */
3397 
3398 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS
3399 {
3400     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
3401     U32                                 ProductSpecificInfo;    /* 0x08 */
3402 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3403   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3404   Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
3405 
3406 /* PageVersion should be provided by product-specific code */
3407 
3408 
3409 /****************************************************************************
3410 *   values for fields used by several types of PCIe Config Pages
3411 ****************************************************************************/
3412 
3413 /* values for NegotiatedLinkRates fields */
3414 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL          (0x0F)
3415 /* link rates used for Negotiated Physical Link Rate */
3416 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN                (0x00)
3417 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED           (0x01)
3418 #define MPI26_PCIE_NEG_LINK_RATE_2_5                    (0x02)
3419 #define MPI26_PCIE_NEG_LINK_RATE_5_0                    (0x03)
3420 #define MPI26_PCIE_NEG_LINK_RATE_8_0                    (0x04)
3421 #define MPI26_PCIE_NEG_LINK_RATE_16_0                   (0x05)
3422 
3423 
3424 /****************************************************************************
3425 *   PCIe IO Unit Config Pages (MPI v2.6 and later)
3426 ****************************************************************************/
3427 
3428 /* PCIe IO Unit Page 0 */
3429 
3430 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA
3431 {
3432     U8          Link;                   /* 0x00 */
3433     U8          LinkFlags;              /* 0x01 */
3434     U8          PhyFlags;               /* 0x02 */
3435     U8          NegotiatedLinkRate;     /* 0x03 */
3436     U32         ControllerPhyDeviceInfo;/* 0x04 */
3437     U16         AttachedDevHandle;      /* 0x08 */
3438     U16         ControllerDevHandle;    /* 0x0A */
3439     U32         EnumerationStatus;      /* 0x0C */
3440     U32         Reserved1;              /* 0x10 */
3441 } MPI26_PCIE_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA,
3442   Mpi26PCIeIOUnit0PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit0PhyData_t;
3443 
3444 /*
3445  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3446  * one and check the value returned for NumPhys at runtime.
3447  */
3448 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX
3449 #define MPI26_PCIE_IOUNIT0_PHY_MAX      (1)
3450 #endif
3451 
3452 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0
3453 {
3454     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                                 /* 0x00 */
3455     U32                                 Reserved1;                              /* 0x08 */
3456     U8                                  NumPhys;                                /* 0x0C */
3457     U8                                  InitStatus;                             /* 0x0D */
3458     U16                                 Reserved3;                              /* 0x0E */
3459     MPI26_PCIE_IO_UNIT0_PHY_DATA        PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX];    /* 0x10 */
3460 } MPI26_CONFIG_PAGE_PIOUNIT_0,
3461   MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_0,
3462   Mpi26PCIeIOUnitPage0_t, MPI2_POINTER pMpi26PCIeIOUnitPage0_t;
3463 
3464 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION                   (0x00)
3465 
3466 /* values for PCIe IO Unit Page 0 LinkFlags */
3467 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08)
3468 
3469 /* values for PCIe IO Unit Page 0 PhyFlags */
3470 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED             (0x08)
3471 
3472 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3473 
3474 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */
3475 
3476 /* values for PCIe IO Unit Page 0 EnumerationStatus */
3477 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED          (0x40000000)
3478 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED           (0x20000000)
3479 
3480 
3481 /* PCIe IO Unit Page 1 */
3482 
3483 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA
3484 {
3485     U8          Link;                       /* 0x00 */
3486     U8          LinkFlags;                  /* 0x01 */
3487     U8          PhyFlags;                   /* 0x02 */
3488     U8          MaxMinLinkRate;             /* 0x03 */
3489     U32         ControllerPhyDeviceInfo;    /* 0x04 */
3490     U32         Reserved1;                  /* 0x08 */
3491 } MPI26_PCIE_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA,
3492   Mpi26PCIeIOUnit1PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit1PhyData_t;
3493 
3494 /* values for LinkFlags */
3495 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS    (0x00)
3496 #define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS     (0x01)
3497 
3498 /*
3499  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3500  * one and check the value returned for NumPhys at runtime.
3501  */
3502 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX
3503 #define MPI26_PCIE_IOUNIT1_PHY_MAX      (1)
3504 #endif
3505 
3506 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1
3507 {
3508     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
3509     U16                                 ControlFlags;                       /* 0x08 */
3510     U16                                 Reserved;                           /* 0x0A */
3511     U16                                 AdditionalControlFlags;             /* 0x0C */
3512     U16                                 NVMeMaxQueueDepth;                  /* 0x0E */
3513     U8                                  NumPhys;                            /* 0x10 */
3514     U8                                  Reserved1;                          /* 0x11 */
3515     U16                                 Reserved2;                          /* 0x12 */
3516     MPI26_PCIE_IO_UNIT1_PHY_DATA        PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/* 0x14 */
3517 } MPI26_CONFIG_PAGE_PIOUNIT_1,
3518   MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_1,
3519   Mpi26PCIeIOUnitPage1_t, MPI2_POINTER pMpi26PCIeIOUnitPage1_t;
3520 
3521 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION   (0x00)
3522 
3523 /* values for PCIe IO Unit Page 1 PhyFlags */
3524 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE                      (0x08)
3525 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY                    (0x01)
3526 
3527 /* values for PCIe IO Unit Page 1 MaxMinLinkRate */
3528 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK                             (0xF0)
3529 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT                            (4)
3530 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5                              (0x20)
3531 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0                              (0x30)
3532 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0                              (0x40)
3533 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0                             (0x50)
3534 
3535 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */
3536 
3537 
3538 /****************************************************************************
3539 *   PCIe Switch Config Pages (MPI v2.6 and later)
3540 ****************************************************************************/
3541 
3542 /* PCIe Switch Page 0 */
3543 
3544 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0
3545 {
3546     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3547     U8                                  PhysicalPort;               /* 0x08 */
3548     U8                                  Reserved1;                  /* 0x09 */
3549     U16                                 Reserved2;                  /* 0x0A */
3550     U16                                 DevHandle;                  /* 0x0C */
3551     U16                                 ParentDevHandle;            /* 0x0E */
3552     U8                                  NumPorts;                   /* 0x10 */
3553     U8                                  PCIeLevel;                  /* 0x11 */
3554     U16                                 Reserved3;                  /* 0x12 */
3555     U32                                 Reserved4;                  /* 0x14 */
3556     U32                                 Reserved5;                  /* 0x18 */
3557     U32                                 Reserved6;                  /* 0x1C */
3558 } MPI26_CONFIG_PAGE_PSWITCH_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_0,
3559   Mpi26PCIeSwitchPage0_t, MPI2_POINTER pMpi26PCIeSwitchPage0_t;
3560 
3561 #define MPI26_PCIESWITCH0_PAGEVERSION       (0x00)
3562 
3563 
3564 /* PCIe Switch Page 1 */
3565 
3566 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1
3567 {
3568     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3569     U8                                  PhysicalPort;               /* 0x08 */
3570     U8                                  Reserved1;                  /* 0x09 */
3571     U16                                 Reserved2;                  /* 0x0A */
3572     U8                                  NumPorts;                   /* 0x0C */
3573     U8                                  PortNum;                    /* 0x0D */
3574     U16                                 AttachedDevHandle;          /* 0x0E */
3575     U16                                 SwitchDevHandle;            /* 0x10 */
3576     U8                                  NegotiatedPortWidth;        /* 0x12 */
3577     U8                                  NegotiatedLinkRate;         /* 0x13 */
3578     U32                                 Reserved4;                  /* 0x14 */
3579     U32                                 Reserved5;                  /* 0x18 */
3580 } MPI26_CONFIG_PAGE_PSWITCH_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_1,
3581   Mpi26PCIeSwitchPage1_t, MPI2_POINTER pMpi26PCIeSwitchPage1_t;
3582 
3583 #define MPI26_PCIESWITCH1_PAGEVERSION       (0x00)
3584 
3585 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3586 
3587 
3588 /****************************************************************************
3589 *   PCIe Device Config Pages (MPI v2.6 and later)
3590 ****************************************************************************/
3591 
3592 /* PCIe Device Page 0 */
3593 
3594 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0
3595 {
3596     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
3597     U16                                 Slot;                   /* 0x08 */
3598     U16                                 EnclosureHandle;        /* 0x0A */
3599     U64                                 WWID;                   /* 0x0C */
3600     U16                                 ParentDevHandle;        /* 0x14 */
3601     U8                                  PortNum;                /* 0x16 */
3602     U8                                  AccessStatus;           /* 0x17 */
3603     U16                                 DevHandle;              /* 0x18 */
3604     U8                                  PhysicalPort;           /* 0x1A */
3605     U8                                  Reserved1;              /* 0x1B */
3606     U32                                 DeviceInfo;             /* 0x1C */
3607     U32                                 Flags;                  /* 0x20 */
3608     U8                                  SupportedLinkRates;     /* 0x24 */
3609     U8                                  MaxPortWidth;           /* 0x25 */
3610     U8                                  NegotiatedPortWidth;    /* 0x26 */
3611     U8                                  NegotiatedLinkRate;     /* 0x27 */
3612     U8                                  EnclosureLevel;         /* 0x28 */
3613     U8                                  Reserved2;              /* 0x29 */
3614     U16                                 Reserved3;              /* 0x2A */
3615     U8                                  ConnectorName[4];       /* 0x2C */
3616     U32                                 Reserved4;              /* 0x30 */
3617     U32                                 Reserved5;              /* 0x34 */
3618 } MPI26_CONFIG_PAGE_PCIEDEV_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_0,
3619   Mpi26PCIeDevicePage0_t, MPI2_POINTER pMpi26PCIeDevicePage0_t;
3620 
3621 #define MPI26_PCIEDEVICE0_PAGEVERSION       (0x01)
3622 
3623 /* values for PCIe Device Page 0 AccessStatus field */
3624 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS                    (0x00)
3625 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION         (0x04)
3626 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED            (0x02)
3627 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED               (0x07)
3628 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED   (0x08)
3629 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE           (0x09)
3630 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED                (0x0A)
3631 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN                      (0x10)
3632 
3633 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT           (0x30)
3634 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED      (0x31)
3635 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED         (0x32)
3636 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED          (0x33)
3637 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED        (0x34)
3638 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED         (0x35)
3639 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36)
3640 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT            (0x37)
3641 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS          (0x38)
3642 
3643 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX                (0x3F)
3644 
3645 /* see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo field */
3646 
3647 /* values for PCIe Device Page 0 Flags field */
3648 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE            (0x8000)
3649 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH              (0x4000)
3650 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE              (0x2000)
3651 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION      (0x0400)
3652 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION            (0x0200)
3653 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE             (0x0100)
3654 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED        (0x0080)
3655 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED            (0x0040)
3656 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED              (0x0020)
3657 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED              (0x0010)
3658 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID               (0x0002)
3659 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT                 (0x0001)
3660 
3661 /* values for PCIe Device Page 0 SupportedLinkRates field */
3662 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED             (0x08)
3663 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED              (0x04)
3664 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED              (0x02)
3665 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED              (0x01)
3666 
3667 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3668 
3669 
3670 /* PCIe Device Page 2 */
3671 
3672 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2
3673 {
3674     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
3675     U16                                 DevHandle;              /* 0x08 */
3676     U16                                 Reserved1;              /* 0x0A */
3677     U32                                 MaximumDataTransferSize;/* 0x0C */
3678     U32                                 Capabilities;           /* 0x10 */
3679     U32                                 Reserved2;              /* 0x14 */
3680 } MPI26_CONFIG_PAGE_PCIEDEV_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_2,
3681   Mpi26PCIeDevicePage2_t, MPI2_POINTER pMpi26PCIeDevicePage2_t;
3682 
3683 #define MPI26_PCIEDEVICE2_PAGEVERSION       (0x00)
3684 
3685 /* defines for PCIe Device Page 2 Capabilities field */
3686 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT                  (0x00000004)
3687 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT          (0x00000002)
3688 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT                 (0x00000001)
3689 
3690 
3691 /****************************************************************************
3692 *   PCIe Link Config Pages (MPI v2.6 and later)
3693 ****************************************************************************/
3694 
3695 /* PCIe Link Page 1 */
3696 
3697 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1
3698 {
3699     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3700     U8                                  Link;                       /* 0x08 */
3701     U8                                  Reserved1;                  /* 0x09 */
3702     U16                                 Reserved2;                  /* 0x0A */
3703     U32                                 CorrectableErrorCount;      /* 0x0C */
3704     U16                                 NonFatalErrorCount;         /* 0x10 */
3705     U16                                 Reserved3;                  /* 0x12 */
3706     U16                                 FatalErrorCount;            /* 0x14 */
3707     U16                                 Reserved4;                  /* 0x16 */
3708 } MPI26_CONFIG_PAGE_PCIELINK_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_1,
3709   Mpi26PcieLinkPage1_t, MPI2_POINTER pMpi26PcieLinkPage1_t;
3710 
3711 #define MPI26_PCIELINK1_PAGEVERSION            (0x00)
3712 
3713 /* PCIe Link Page 2 */
3714 
3715 typedef struct _MPI26_PCIELINK2_LINK_EVENT
3716 {
3717     U8          LinkEventCode;      /* 0x00 */
3718     U8          Reserved1;          /* 0x01 */
3719     U16         Reserved2;          /* 0x02 */
3720     U32         LinkEventInfo;      /* 0x04 */
3721 } MPI26_PCIELINK2_LINK_EVENT, MPI2_POINTER PTR_MPI26_PCIELINK2_LINK_EVENT,
3722   Mpi26PcieLink2LinkEvent_t, MPI2_POINTER pMpi26PcieLink2LinkEvent_t;
3723 
3724 /* use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */
3725 
3726 
3727 /*
3728  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3729  * one and check the value returned for NumLinkEvents at runtime.
3730  */
3731 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX
3732 #define MPI26_PCIELINK2_LINK_EVENT_MAX      (1)
3733 #endif
3734 
3735 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2
3736 {
3737     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3738     U8                                  Link;                       /* 0x08 */
3739     U8                                  Reserved1;                  /* 0x09 */
3740     U16                                 Reserved2;                  /* 0x0A */
3741     U8                                  NumLinkEvents;              /* 0x0C */
3742     U8                                  Reserved3;                  /* 0x0D */
3743     U16                                 Reserved4;                  /* 0x0E */
3744     MPI26_PCIELINK2_LINK_EVENT          LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /* 0x10 */
3745 } MPI26_CONFIG_PAGE_PCIELINK_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_2,
3746   Mpi26PcieLinkPage2_t, MPI2_POINTER pMpi26PcieLinkPage2_t;
3747 
3748 #define MPI26_PCIELINK2_PAGEVERSION            (0x00)
3749 
3750 
3751 /* PCIe Link Page 3 */
3752 
3753 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG
3754 {
3755     U8          LinkEventCode;      /* 0x00 */
3756     U8          Reserved1;          /* 0x01 */
3757     U16         Reserved2;          /* 0x02 */
3758     U8          CounterType;        /* 0x04 */
3759     U8          ThresholdWindow;    /* 0x05 */
3760     U8          TimeUnits;          /* 0x06 */
3761     U8          Reserved3;          /* 0x07 */
3762     U32         EventThreshold;     /* 0x08 */
3763     U16         ThresholdFlags;     /* 0x0C */
3764     U16         Reserved4;          /* 0x0E */
3765 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, MPI2_POINTER PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG,
3766   Mpi26PcieLink3LinkEventConfig_t, MPI2_POINTER pMpi26PcieLink3LinkEventConfig_t;
3767 
3768 /* values for LinkEventCode field */
3769 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT                              (0x00)
3770 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED            (0x01)
3771 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED              (0x02)
3772 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED                  (0x03)
3773 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED              (0x04)
3774 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED      (0x05)
3775 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED               (0x06)
3776 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP                          (0x07)
3777 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP                     (0x08)
3778 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP                         (0x09)
3779 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE                  (0x0A)
3780 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE                     (0x0B)
3781 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE                     (0x0C)
3782 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE                        (0x0D)
3783 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE                  (0x0E)
3784 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE                 (0x0F)
3785 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR                          (0x10)
3786 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR                          (0x11)
3787 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR                       (0x12)
3788 
3789 /* values for the CounterType field */
3790 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING               (0x00)
3791 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING             (0x01)
3792 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE             (0x02)
3793 
3794 /* values for the TimeUnits field */
3795 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS            (0x00)
3796 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS           (0x01)
3797 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND              (0x02)
3798 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS            (0x03)
3799 
3800 /* values for the ThresholdFlags field */
3801 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY                 (0x0001)
3802 
3803 /*
3804  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3805  * one and check the value returned for NumLinkEvents at runtime.
3806  */
3807 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX
3808 #define MPI26_PCIELINK3_LINK_EVENT_MAX      (1)
3809 #endif
3810 
3811 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3
3812 {
3813     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
3814     U8                                  Link;                       /* 0x08 */
3815     U8                                  Reserved1;                  /* 0x09 */
3816     U16                                 Reserved2;                  /* 0x0A */
3817     U8                                  NumLinkEvents;              /* 0x0C */
3818     U8                                  Reserved3;                  /* 0x0D */
3819     U16                                 Reserved4;                  /* 0x0E */
3820     MPI26_PCIELINK3_LINK_EVENT_CONFIG   LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /* 0x10 */
3821 } MPI26_CONFIG_PAGE_PCIELINK_3, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_3,
3822   Mpi26PcieLinkPage3_t, MPI2_POINTER pMpi26PcieLinkPage3_t;
3823 
3824 #define MPI26_PCIELINK3_PAGEVERSION            (0x00)
3825 
3826 
3827 #endif
3828 
3829