xref: /illumos-gate/usr/src/uts/common/sys/fibre-channel/fca/qlc/ql_api.h (revision 4c3888b8f38c903370e022661d08aba393db3911)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /* Copyright 2015 QLogic Corporation */
23 
24 /*
25  * Copyright (c) 2008, 2011, Oracle and/or its affiliates. All rights reserved.
26  */
27 
28 #ifndef	_QL_API_H
29 #define	_QL_API_H
30 
31 /*
32  * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
33  *
34  * ***********************************************************************
35  * *									**
36  * *				NOTICE					**
37  * *		COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION		**
38  * *			ALL RIGHTS RESERVED				**
39  * *									**
40  * ***********************************************************************
41  *
42  */
43 
44 #ifdef	__cplusplus
45 extern "C" {
46 #endif
47 
48 /* OS include files. */
49 #include <sys/scsi/scsi_types.h>
50 #include <sys/byteorder.h>
51 #include <sys/pci.h>
52 #include <sys/utsname.h>
53 #include <sys/file.h>
54 #include <sys/param.h>
55 #include <sys/time.h>
56 #include <sys/ddifm.h>
57 #include <sys/sunddi.h>
58 #include <sys/fm/protocol.h>
59 #include <sys/fm/io/ddi.h>
60 #include <ql_open.h>
61 
62 #include <sys/fibre-channel/fc.h>
63 #include <sys/fibre-channel/impl/fc_fcaif.h>
64 
65 #ifndef	DDI_INTR_TYPE_FIXED
66 #define	DDI_INTR_TYPE_FIXED	0x1
67 #endif
68 #ifndef	DDI_INTR_TYPE_MSI
69 #define	DDI_INTR_TYPE_MSI	0x2
70 #endif
71 #ifndef	DDI_INTR_TYPE_MSIX
72 #define	DDI_INTR_TYPE_MSIX	0x4
73 #endif
74 #ifndef	DDI_INTR_FLAG_BLOCK
75 #define	DDI_INTR_FLAG_BLOCK	0x100
76 #endif
77 #ifndef	DDI_INTR_ALLOC_NORMAL
78 #define	DDI_INTR_ALLOC_NORMAL	0
79 #endif
80 #ifndef	DDI_INTR_ALLOC_STRICT
81 #define	DDI_INTR_ALLOC_STRICT	1
82 #endif
83 
84 #define	PCI_PCIE_DEVICE_CONTROL		0x8	/* Device control reg offset */
85 #define	PCI_MSI_CONTROL			0x2	/* MSI Control reg offset */
86 #define	PCI_MSI_MSG_ADDR		0x4	/* MSI Msg Addr reg offset */
87 #define	PCI_MSI_MSG_UPPER_ADDR		0x8	/* MSI MSI Msg Upper Addr reg */
88 /* offset */
89 #define	PCI_MSI_MSG_DATA		0xc	/* MSI Msg Data reg offset */
90 #define	PCI_MSI_X_CONTROL		0x2	/* MSI-X Control reg offset */
91 #define	MSI_X_TABLE_SIZE_MASK		0x7ff	/* MSI-X Table Size mask */
92 
93 #define	PCIE_EXT_CAP_PTR		0x100
94 #define	PCIE_EXT_CAP_NEXT_SHIFT		20
95 #define	PCIE_EXT_CAP_ID_SRIOV		0x0010	/* SRIOV capabilities offset */
96 #define	PCIE_EXT_CAP_SRIOV_TOTAL_VFS	0xe
97 #define	PCIE_SRIOV_PAGE_SIZE_MULTIPLIER	4096
98 
99 /*
100  * NPIV defines
101  */
102 #ifndef	FC_NPIV_FDISC_FAILED
103 #define	FC_NPIV_FDISC_FAILED	0x45
104 #endif
105 #ifndef	FC_NPIV_FDISC_WWN_INUSE
106 #define	FC_NPIV_FDISC_WWN_INUSE	0x46
107 #endif
108 #ifndef	FC_NPIV_NOT_SUPPORTED
109 #define	FC_NPIV_NOT_SUPPORTED	0x47
110 #endif
111 #ifndef	FC_NPIV_WRONG_TOPOLOGY
112 #define	FC_NPIV_WRONG_TOPOLOGY	0x48
113 #endif
114 #ifndef	FC_NPIV_NPIV_BOUND
115 #define	FC_NPIV_NPIV_BOUND	0x49
116 #endif
117 #ifndef	FC_HBA_PORTSPEED_32GBIT
118 #define	FC_HBA_PORTSPEED_32GBIT	64
119 #endif
120 
121 #pragma weak ddi_intr_get_supported_types
122 #pragma weak ddi_intr_get_nintrs
123 #pragma weak ddi_intr_alloc
124 #pragma weak ddi_intr_free
125 #pragma weak ddi_intr_get_pri
126 #pragma weak ddi_intr_add_handler
127 #pragma weak ddi_intr_dup_handler
128 #pragma weak ddi_intr_get_navail
129 #pragma weak ddi_intr_block_disable
130 #pragma weak ddi_intr_block_enable
131 #pragma weak ddi_intr_disable
132 #pragma weak ddi_intr_enable
133 #pragma weak ddi_intr_get_cap
134 #pragma weak ddi_intr_remove_handler
135 extern int ddi_intr_get_supported_types();
136 extern int ddi_intr_get_nintrs();
137 extern int ddi_intr_alloc();
138 extern int ddi_intr_free();
139 extern int ddi_intr_get_pri();
140 extern int ddi_intr_add_handler();
141 extern int ddi_intr_dup_handler();
142 extern int ddi_intr_get_navail();
143 extern int ddi_intr_block_disable();
144 extern int ddi_intr_block_enable();
145 extern int ddi_intr_disable();
146 extern int ddi_intr_enable();
147 extern int ddi_intr_get_cap();
148 extern int ddi_intr_remove_handler();
149 
150 #define	QL_CLEAR_DMA_HANDLE(x)	((ddi_dma_impl_t *)x)->dmai_fault_notify = 0; \
151 				((ddi_dma_impl_t *)x)->dmai_fault_check = 0; \
152 				((ddi_dma_impl_t *)x)->dmai_fault	= 0
153 
154 #ifndef	FC_STATE_1GBIT_SPEED
155 #define	FC_STATE_1GBIT_SPEED	0x0100	/* 1 Gbit/sec */
156 #endif
157 #ifndef	FC_STATE_2GBIT_SPEED
158 #define	FC_STATE_2GBIT_SPEED	0x0400	/* 2 Gbit/sec */
159 #endif
160 #ifndef	FC_STATE_4GBIT_SPEED
161 #define	FC_STATE_4GBIT_SPEED	0x0500	/* 4 Gbit/sec */
162 #endif
163 #ifndef FC_STATE_8GBIT_SPEED
164 #define	FC_STATE_8GBIT_SPEED	0x0700	/* 8 Gbit/sec */
165 #endif
166 #ifndef FC_STATE_10GBIT_SPEED
167 #define	FC_STATE_10GBIT_SPEED	0x0600	/* 10 Gbit/sec */
168 #endif
169 #ifndef FC_STATE_16GBIT_SPEED
170 #define	FC_STATE_16GBIT_SPEED	0x0800	/* 16 Gbit/sec */
171 #endif
172 #ifndef FC_STATE_32GBIT_SPEED
173 #define	FC_STATE_32GBIT_SPEED	0x1000	/* 32 Gbit/sec */
174 #endif
175 
176 /*
177  * Data bit definitions.
178  */
179 #define	BIT_0	0x1
180 #define	BIT_1	0x2
181 #define	BIT_2	0x4
182 #define	BIT_3	0x8
183 #define	BIT_4	0x10
184 #define	BIT_5	0x20
185 #define	BIT_6	0x40
186 #define	BIT_7	0x80
187 #define	BIT_8	0x100
188 #define	BIT_9	0x200
189 #define	BIT_10	0x400
190 #define	BIT_11	0x800
191 #define	BIT_12	0x1000
192 #define	BIT_13	0x2000
193 #define	BIT_14	0x4000
194 #define	BIT_15	0x8000
195 #define	BIT_16	0x10000
196 #define	BIT_17	0x20000
197 #define	BIT_18	0x40000
198 #define	BIT_19	0x80000
199 #define	BIT_20	0x100000
200 #define	BIT_21	0x200000
201 #define	BIT_22	0x400000
202 #define	BIT_23	0x800000
203 #define	BIT_24	0x1000000
204 #define	BIT_25	0x2000000
205 #define	BIT_26	0x4000000
206 #define	BIT_27	0x8000000
207 #define	BIT_28	0x10000000
208 #define	BIT_29	0x20000000
209 #define	BIT_30	0x40000000
210 #define	BIT_31	0x80000000
211 #define	BIT_32	0x100000000
212 #define	BIT_33	0x200000000
213 #define	BIT_34	0x400000000
214 #define	BIT_35	0x800000000
215 #define	BIT_36	0x1000000000
216 #define	BIT_37	0x2000000000
217 #define	BIT_38	0x4000000000
218 #define	BIT_39	0x8000000000
219 #define	BIT_40	0x10000000000
220 #define	BIT_41	0x20000000000
221 #define	BIT_42	0x40000000000
222 #define	BIT_43	0x80000000000
223 #define	BIT_44	0x100000000000
224 #define	BIT_45	0x200000000000
225 #define	BIT_46	0x400000000000
226 #define	BIT_47	0x800000000000
227 #define	BIT_48	0x1000000000000
228 #define	BIT_49	0x2000000000000
229 #define	BIT_50	0x4000000000000
230 #define	BIT_51	0x8000000000000
231 #define	BIT_52	0x10000000000000
232 #define	BIT_53	0x20000000000000
233 #define	BIT_54	0x40000000000000
234 #define	BIT_55	0x80000000000000
235 #define	BIT_56	0x100000000000000
236 #define	BIT_57	0x200000000000000
237 #define	BIT_58	0x400000000000000
238 #define	BIT_59	0x800000000000000
239 #define	BIT_60	0x1000000000000000
240 #define	BIT_61	0x2000000000000000
241 #define	BIT_62	0x4000000000000000
242 #define	BIT_63	0x8000000000000000
243 
244 /*
245  *  Local Macro Definitions.
246  */
247 #ifndef TRUE
248 #define	TRUE	B_TRUE
249 #endif
250 
251 #ifndef FALSE
252 #define	FALSE	B_FALSE
253 #endif
254 
255 /*
256  * I/O register
257  */
258 #define	RD_REG_BYTE(ha, addr) \
259 	(uint8_t)ddi_get8(ha->dev_handle, (uint8_t *)(addr))
260 #define	RD_REG_WORD(ha, addr) \
261 	(uint16_t)ddi_get16(ha->dev_handle, (uint16_t *)(addr))
262 #define	RD_REG_DWORD(ha, addr) \
263 	(uint32_t)ddi_get32(ha->dev_handle, (uint32_t *)(addr))
264 #define	RD_REG_DDWORD(ha, addr) \
265 	(uint64_t)ddi_get64(ha->dev_handle, (uint64_t *)(addr))
266 
267 #define	WRT_REG_BYTE(ha, addr, data) \
268 	ddi_put8(ha->dev_handle, (uint8_t *)(addr), (uint8_t)(data))
269 #define	WRT_REG_WORD(ha, addr, data) \
270 	ddi_put16(ha->dev_handle, (uint16_t *)(addr), (uint16_t)(data))
271 #define	WRT_REG_DWORD(ha, addr, data) \
272 	ddi_put32(ha->dev_handle, (uint32_t *)(addr), (uint32_t)(data))
273 #define	WRT_REG_DDWORD(ha, addr, data) \
274 	ddi_put64(ha->dev_handle, (uint64_t *)(addr), (uint64_t)(data))
275 
276 #define	RD8_IO_REG(ha, regname) \
277 	RD_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname))
278 #define	RD16_IO_REG(ha, regname) \
279 	RD_REG_WORD(ha, (ha->iobase + ha->reg_off->regname))
280 #define	RD32_IO_REG(ha, regname) \
281 	RD_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname))
282 
283 #define	WRT8_IO_REG(ha, regname, data) \
284 	WRT_REG_BYTE(ha, (ha->iobase + ha->reg_off->regname), (data))
285 #define	WRT16_IO_REG(ha, regname, data) \
286 	WRT_REG_WORD(ha, (ha->iobase + ha->reg_off->regname), (data))
287 #define	WRT32_IO_REG(ha, regname, data) \
288 	WRT_REG_DWORD(ha, (ha->iobase + ha->reg_off->regname), (data))
289 
290 #define	RD_IOREG_BYTE(ha, addr) \
291 	(uint8_t)ddi_get8(ha->iomap_dev_handle, (uint8_t *)(addr))
292 #define	RD_IOREG_WORD(ha, addr) \
293 	(uint16_t)ddi_get16(ha->iomap_dev_handle, (uint16_t *)(addr))
294 #define	RD_IOREG_DWORD(ha, addr) \
295 	(uint32_t)ddi_get32(ha->iomap_dev_handle, (uint32_t *)(addr))
296 
297 #define	WRT_IOREG_BYTE(ha, addr, data) \
298 	ddi_put8(ha->iomap_dev_handle, (uint8_t *)addr, (uint8_t)(data))
299 #define	WRT_IOREG_WORD(ha, addr, data) \
300 	ddi_put16(ha->iomap_dev_handle, (uint16_t *)addr, (uint16_t)(data))
301 #define	WRT_IOREG_DWORD(ha, addr, data) \
302 	ddi_put32(ha->iomap_dev_handle, (uint32_t *)addr, (uint32_t)(data))
303 
304 #define	RD8_IOMAP_REG(ha, regname) \
305 	RD_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname))
306 #define	RD16_IOMAP_REG(ha, regname) \
307 	RD_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname))
308 #define	RD32_IOMAP_REG(ha, regname) \
309 	RD_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname))
310 
311 #define	WRT8_IOMAP_REG(ha, regname, data) \
312 	WRT_IOREG_BYTE(ha, (ha->iomap_iobase + ha->reg_off->regname), (data))
313 #define	WRT16_IOMAP_REG(ha, regname, data) \
314 	WRT_IOREG_WORD(ha, (ha->iomap_iobase + ha->reg_off->regname), (data))
315 #define	WRT32_IOMAP_REG(ha, regname, data) \
316 	WRT_IOREG_DWORD(ha, (ha->iomap_iobase + ha->reg_off->regname), (data))
317 
318 #define	RD8_MBAR_REG(ha, ofst) \
319 	(uint8_t)ddi_get8(ha->mbar_dev_handle, \
320 	(uint8_t *)(ha->mbar + (ofst)))
321 #define	RD16_MBAR_REG(ha, ofst) \
322 	(uint16_t)ddi_get16(ha->mbar_dev_handle, \
323 	(uint16_t *)(ha->mbar + (ofst)))
324 #define	RD32_MBAR_REG(ha, ofst) \
325 	(uint32_t)ddi_get32(ha->mbar_dev_handle, \
326 	(uint32_t *)(ha->mbar + (ofst)))
327 #define	RD64_MBAR_REG(ha, ofst) \
328 	(uint64_t)ddi_get64(ha->mbar_dev_handle, \
329 	(uint64_t *)(ha->mbar + (ofst)))
330 
331 #define	WR8_MBAR_REG(ha, ofst, data) \
332 	ddi_put8(ha->mbar_dev_handle, \
333 	(uint8_t *)(ha->mbar + (ofst)), \
334 	(uint8_t)(data))
335 #define	WR16_MBAR_REG(ha, ofst, data) \
336 	ddi_put16(ha->mbar_dev_handle, \
337 	(uint16_t *)(ha->mbar + (ofst)), \
338 	(uint16_t)(data))
339 #define	WR32_MBAR_REG(ha, ofst, data) \
340 	ddi_put32(ha->mbar_dev_handle, \
341 	(uint32_t *)(ha->mbar + (ofst)), \
342 	(uint32_t)(data))
343 #define	WR64_MBAR_REG(ha, ofst, data) \
344 	ddi_put64(ha->mbar_dev_handle, \
345 	(uint64_t *)(ha->mbar + (ofst)), \
346 	(uint64_t)(data))
347 
348 /*
349  * FCA definitions
350  */
351 #define	MAX_LUNS	16384
352 #define	QL_FCA_BRAND	0x0fca2200
353 
354 /* Following to be removed when defined by OS. */
355 /* ************************************************************************ */
356 #define	LA_ELS_FARP_REQ		0x54
357 #define	LA_ELS_FARP_REPLY	0x55
358 #define	LA_ELS_LPC		0x71
359 #define	LA_ELS_LSTS		0x72
360 
361 typedef struct {
362 	ls_code_t ls_code;
363 	uint8_t rsvd[3];
364 	uint8_t port_control;
365 	uint8_t lpb[16];
366 	uint8_t lpe[16];
367 } ql_lpc_t;
368 
369 typedef struct {
370 	ls_code_t ls_code;
371 } ql_acc_rjt_t;
372 
373 typedef	fc_linit_resp_t ql_lpc_resp_t;
374 typedef	fc_scr_resp_t ql_rscn_resp_t;
375 
376 typedef struct {
377 	uint16_t    class_valid_svc_opt;
378 	uint16_t    initiator_ctl;
379 	uint16_t    recipient_ctl;
380 	uint16_t    rcv_data_size;
381 	uint16_t    conc_sequences;
382 	uint16_t    n_port_end_to_end_credit;
383 	uint16_t    open_sequences_per_exch;
384 	uint16_t    unused;
385 } class_svc_param_t;
386 
387 typedef struct {
388 	uint8_t    type;
389 	uint8_t    rsvd;
390 	uint16_t    process_assoc_flags;
391 	uint32_t    originator_process;
392 	uint32_t    responder_process;
393 	uint32_t    process_flags;
394 } prli_svc_param_t;
395 /* *********************************************************************** */
396 
397 /*
398  * Fibre Channel device definitions.
399  */
400 #define	MAX_22_FIBRE_DEVICES	256
401 #define	MAX_24_FIBRE_DEVICES	2048
402 #define	MAX_24_VIRTUAL_PORTS	127
403 #define	MAX_25_VIRTUAL_PORTS	254
404 #define	MAX_27_VIRTUAL_PORTS	252
405 #define	MAX_8021_VIRTUAL_PORTS	63
406 #define	MAX_81XX_VIRTUAL_PORTS	254
407 #define	MAX_83_VIRTUAL_PORTS	254
408 
409 #define	LAST_LOCAL_LOOP_ID		 0x7d
410 #define	FL_PORT_LOOP_ID			 0x7e /* FFFFFE Fabric F_Port */
411 #define	SWITCH_FABRIC_CONTROLLER_LOOP_ID 0x7f /* FFFFFD Fabric Controller */
412 #define	SIMPLE_NAME_SERVER_LOOP_ID	 0x80 /* FFFFFC Directory Server */
413 #define	SNS_FIRST_LOOP_ID		 0x81
414 #define	SNS_LAST_LOOP_ID		 0xfe
415 #define	IP_BROADCAST_LOOP_ID		 0xff /* FFFFFF Broadcast */
416 #define	BROADCAST_ADDR			 0xffffff /* FFFFFF Broadcast */
417 
418 /*
419  * Fibre Channel 24xx device definitions.
420  */
421 #define	LAST_N_PORT_HDL		0x7ef
422 #define	SNS_24XX_HDL		0x7FC	/* SNS FFFFFCh */
423 #define	SFC_24XX_HDL		0x7FD	/* fabric controller FFFFFDh */
424 #define	FL_PORT_24XX_HDL	0x7FE	/* F_Port FFFFFEh */
425 #define	BROADCAST_24XX_HDL	0x7FF	/* IP broadcast FFFFFFh */
426 
427 /* Loop ID's used as flags, must be higher than any valid Loop ID */
428 #define	PORT_NO_LOOP_ID		0x8000	/* Device does not have loop ID. */
429 #define	PORT_LOST_ID		0x4000	/* Device has been lost. */
430 
431 /* Fibre Channel Topoploy. */
432 #define	QL_N_PORT		BIT_0
433 #define	QL_NL_PORT		BIT_1
434 #define	QL_F_PORT		BIT_2
435 #define	QL_FL_PORT		BIT_3
436 #define	QL_LOOP_CONNECTION	(QL_NL_PORT | QL_FL_PORT)
437 #define	QL_P2P_CONNECTION	(QL_F_PORT | QL_N_PORT)
438 #define	QL_FABRIC_CONNECTION	(QL_F_PORT | QL_FL_PORT)
439 
440 /* Timeout timer counts in seconds (must greater than 1 second). */
441 #define	WATCHDOG_TIME		5			/* 0 - 255 */
442 #define	PORT_RETRY_TIME		2			/* 0 - 255 */
443 #define	LOOP_DOWN_TIMER_OFF	0
444 #define	LOOP_DOWN_TIMER_START	240			/* 0 - 255 */
445 #define	LOOP_DOWN_TIMER_END	1
446 #define	LOOP_DOWN_RESET		(LOOP_DOWN_TIMER_START - 45)	/* 0 - 255 */
447 #define	R_A_TOV_DEFAULT		20			/* 0 - 65535 */
448 #define	IDLE_CHECK_TIMER	300			/* 0 - 65535 */
449 #define	MAX_DEVICE_LOST_RETRY	16			/* 0 - 255 */
450 #define	TIMEOUT_THRESHOLD	16			/* 0 - 255 */
451 
452 /* Maximum outstanding commands in ISP queues (1-4095) */
453 #define	OSC_INDEX_MASK		0xfff
454 #define	OSC_INDEX_SHIFT		12
455 
456 /* Maximum unsolicited buffers (1-65535) */
457 #define	QL_UB_LIMIT	256
458 
459 /* ISP request, response and receive buffer entry counts */
460 #define	REQUEST_ENTRY_CNT	512	/* Request entries (205-65535) */
461 #define	RESPONSE_ENTRY_CNT	256	/* Response entries (1-65535) */
462 #define	RCVBUF_CONTAINER_CNT	64	/* Rcv buffer containers (8-1024) */
463 
464 /*
465  * ISP request, response, mailbox and receive buffer queue sizes
466  */
467 #define	SHADOW_ENTRY_SIZE	4
468 #define	REQUEST_ENTRY_SIZE	64
469 #define	REQUEST_QUEUE_SIZE	(REQUEST_ENTRY_SIZE * REQUEST_ENTRY_CNT)
470 
471 #define	RESPONSE_ENTRY_SIZE	64
472 #define	RESPONSE_QUEUE_SIZE	(RESPONSE_ENTRY_SIZE * RESPONSE_ENTRY_CNT)
473 
474 #define	RCVBUF_CONTAINER_SIZE	12
475 #define	RCVBUF_QUEUE_SIZE	(RCVBUF_CONTAINER_SIZE * RCVBUF_CONTAINER_CNT)
476 
477 /*
478  * DMA attributes definitions.
479  */
480 #define	QL_DMA_LOW_ADDRESS		(uint64_t)0
481 #define	QL_DMA_HIGH_64BIT_ADDRESS	(uint64_t)0xffffffffffffffff
482 #define	QL_DMA_HIGH_32BIT_ADDRESS	(uint64_t)0xffffffff
483 #define	QL_DMA_XFER_COUNTER		(uint64_t)0xffffffff
484 #define	QL_DMA_ADDRESS_ALIGNMENT	(uint64_t)8
485 #define	QL_DMA_ALIGN_8_BYTE_BOUNDARY	(uint64_t)BIT_3
486 #define	QL_DMA_RING_ADDRESS_ALIGNMENT	(uint64_t)64
487 #define	QL_DMA_ALIGN_64_BYTE_BOUNDARY	(uint64_t)BIT_6
488 #define	QL_DMA_BURSTSIZES		0xff
489 #define	QL_DMA_MIN_XFER_SIZE		1
490 #define	QL_DMA_MAX_XFER_SIZE		(uint64_t)0xffffffff
491 #define	QL_DMA_SEGMENT_BOUNDARY		(uint64_t)0xffffffff
492 
493 #ifdef __sparc
494 #define	QL_DMA_SG_LIST_LENGTH	1
495 #define	QL_FCSM_CMD_SGLLEN	1
496 #define	QL_FCSM_RSP_SGLLEN	1
497 #define	QL_FCIP_CMD_SGLLEN	1
498 #define	QL_FCIP_RSP_SGLLEN	1
499 #define	QL_FCP_CMD_SGLLEN	1
500 #define	QL_FCP_RSP_SGLLEN	1
501 #else
502 #define	QL_DMA_SG_LIST_LENGTH	1024
503 #define	QL_FCSM_CMD_SGLLEN	1
504 #define	QL_FCSM_RSP_SGLLEN	6
505 /*
506  * QL_FCIP_CMD_SGLLEN needs to be increased as we changed the max fcip packet
507  * size to about 64K. With this, we need to increase the maximum number of
508  * scatter-gather elements allowable from the existing 7. We want it to be more
509  * like 17 (max fragments for an fcip packet that is unaligned). (64K / 4K) + 1
510  * or whatever. Otherwise the DMA breakup routines will give bad results.
511  */
512 #define	QL_FCIP_CMD_SGLLEN	17
513 #define	QL_FCIP_RSP_SGLLEN	1
514 #define	QL_FCP_CMD_SGLLEN	1
515 #define	QL_FCP_RSP_SGLLEN	1
516 #endif
517 
518 #ifndef	DDI_DMA_RELAXED_ORDERING
519 #define	DDI_DMA_RELAXED_ORDERING	0x400
520 #endif
521 
522 #define	QL_DMA_GRANULARITY	1
523 #define	QL_DMA_XFER_FLAGS	0
524 
525 typedef union {
526 	uint64_t size64;	/* 1 X 64 bit number */
527 	uint32_t size32[2];	/* 2 x 32 bit number */
528 	uint16_t size16[4];	/* 4 x 16 bit number */
529 	uint8_t	 size8[8];	/* 8 x  8 bit number */
530 } conv_num_t;
531 
532 /*
533  *  Device register offsets.
534  */
535 #define	MAX_MBOX_COUNT		32
536 typedef struct {
537 	uint16_t flash_address;	/* Flash BIOS address */
538 	uint16_t flash_data;	/* Flash BIOS data */
539 	uint16_t ctrl_status;	/* Control/Status */
540 	uint16_t ictrl;		/* Interrupt control */
541 	uint16_t istatus;	/* Interrupt status */
542 	uint16_t semaphore;	/* Semaphore */
543 	uint16_t nvram;		/* NVRAM register. */
544 	uint16_t req_in;		/* for 2200 MBX 4 Write */
545 	uint16_t req_out;	/* for 2200 MBX 4 read */
546 	uint16_t resp_in;	/* for 2200 MBX 5 Read */
547 	uint16_t resp_out;	/* for 2200 MBX 5 Write */
548 	uint16_t risc2host;
549 	uint16_t mbox_cnt;	/* Number of mailboxes */
550 	uint16_t mailbox_in[MAX_MBOX_COUNT]; /* Mailbox registers */
551 	uint16_t mailbox_out[MAX_MBOX_COUNT]; /* Mailbox registers */
552 	uint16_t fpm_diag_config;
553 	uint16_t pcr;		/* Processor Control Register. */
554 	uint16_t mctr;		/* Memory Configuration and Timing. */
555 	uint16_t fb_cmd;
556 	uint16_t hccr;		/* Host command & control register. */
557 	uint16_t gpiod;		/* GPIO Data register. */
558 	uint16_t gpioe;		/* GPIO Enable register. */
559 	uint16_t host_to_host_sema;	/* 2312 resource lock register */
560 	uint16_t pri_req_in;	/* 2400 */
561 	uint16_t pri_req_out;	/* 2400 */
562 	uint16_t atio_req_in;	/* 2400 */
563 	uint16_t atio_req_out;	/* 2400 */
564 	uint16_t io_base_addr;	/* 2400 */
565 	uint16_t nx_host_int;	/* NetXen */
566 	uint16_t nx_risc_int;	/* NetXen */
567 } reg_off_t;
568 
569 /*
570  * Multi-Queue, Mem BAR 2 definition.
571  */
572 #define	MBAR2_REQ_IN		0x0
573 #define	MBAR2_REQ_OUT		0x4
574 #define	MBAR2_RESP_IN		0x8
575 #define	MBAR2_RESP_OUT		0xc
576 #define	MBAR2_MULTI_Q_MAX	256
577 #define	MBAR2_REG_OFFSET	4096
578 
579 /*
580  * Mbox-8 read maximum debounce count.
581  * Reading Mbox-8 could be debouncing, before getting stable value.
582  * This is the recommended driver fix from Qlogic along with firmware fix.
583  * During testing, maximum count did not cross 3.
584  */
585 #define	QL_MAX_DEBOUNCE	10
586 
587 /*
588  * Control Status register definitions
589  */
590 #define	ISP_FUNC_NUM_MASK	(BIT_15 | BIT_14)
591 #define	ISP_FLASH_64K_BANK	BIT_3	/* Flash BIOS 64K Bank Select */
592 #define	ISP_FLASH_ENABLE	BIT_1	/* Flash BIOS Read/Write enable */
593 #define	ISP_RESET		BIT_0	/* ISP soft reset */
594 
595 /*
596  * Control Status 24xx register definitions
597  */
598 #define	FLASH_NVRAM_ACCESS_ERROR	BIT_18
599 #define	DMA_ACTIVE			BIT_17
600 #define	DMA_SHUTDOWN			BIT_16
601 #define	FUNCTION_NUMBER			BIT_15
602 
603 #define	MWB_4096_BYTES			(BIT_5 | BIT_4)
604 #define	MWB_2048_BYTES			BIT_5
605 #define	MWB_1024_BYTES			BIT_4
606 #define	MWB_512_BYTES			0
607 
608 /*
609  * Interrupt Control register definitions
610  */
611 #define	ISP_EN_INT		BIT_15	/* ISP enable interrupts. */
612 #define	ISP_EN_RISC		BIT_3	/* ISP enable RISC interrupts. */
613 
614 /*
615  * Interrupt Status register definitions
616  */
617 #define	RISC_INT		BIT_3	/* RISC interrupt */
618 
619 /*
620  * NetXen Host/Risc Interrupt register definitions
621  */
622 #define	NX_MBX_CMD		BIT_0	/* Mailbox command present */
623 #define	NX_RISC_INT		BIT_0	/* RISC interrupt present */
624 
625 /*
626  * NVRAM register definitions.
627  */
628 #define	NV_DESELECT		0
629 #define	NV_CLOCK		BIT_0
630 #define	NV_SELECT		BIT_1
631 #define	NV_DATA_OUT		BIT_2
632 #define	NV_DATA_IN		BIT_3
633 #define	NV_PR_ENABLE		BIT_13	/* protection register enable */
634 #define	NV_WR_ENABLE		BIT_14	/* write enable */
635 #define	NV_BUSY			BIT_15
636 
637 /*
638  * Flash/NVRAM 24xx definitions
639  */
640 #define	FLASH_DATA_FLAG		BIT_31
641 #define	FLASH_CONF_ADDR		0x7FFD0000
642 #define	FLASH_24_25_DATA_ADDR	0x7FF00000
643 #define	FLASH_8100_DATA_ADDR	0x7F800000
644 #define	FLASH_8300_DATA_ADDR	0x7F800000
645 #define	FLASH_2700_DATA_ADDR	0x7F800000
646 #define	FLASH_ADDR_MASK		0x7FFF0000
647 
648 #define	NVRAM_CONF_ADDR		0x7FFF0000
649 #define	NVRAM_DATA_ADDR		0x7FFE0000
650 
651 #define	NVRAM_2200_FUNC0_ADDR		0x0
652 #define	NVRAM_2300_FUNC0_ADDR		0x0
653 #define	NVRAM_2300_FUNC1_ADDR		0x80
654 #define	NVRAM_2400_FUNC0_ADDR		0x80
655 #define	NVRAM_2400_FUNC1_ADDR		0x180
656 #define	NVRAM_2500_FUNC0_ADDR		0x48080
657 #define	NVRAM_2500_FUNC1_ADDR		0x48180
658 #define	NVRAM_8100_FUNC0_ADDR		0xD0080
659 #define	NVRAM_8100_FUNC1_ADDR		0xD0180
660 #define	NVRAM_8021_FUNC0_ADDR		0xF0080
661 #define	NVRAM_8021_FUNC1_ADDR		0xF0180
662 #define	NVRAM_8300_FC_FUNC0_ADDR	0x270080
663 #define	NVRAM_8300_FC_FUNC1_ADDR	0x270180
664 #define	NVRAM_8300_FCOE_FUNC0_ADDR	0x274080
665 #define	NVRAM_8300_FCOE_FUNC1_ADDR	0x274180
666 #define	NVRAM_2700_FUNC0_ADDR		0x270080
667 #define	NVRAM_2700_FUNC1_ADDR		0x270180
668 #define	NVRAM_2700_FUNC2_ADDR		0x270280
669 #define	NVRAM_2700_FUNC3_ADDR		0x270380
670 
671 #define	VPD_2400_FUNC0_ADDR		0
672 #define	VPD_2400_FUNC1_ADDR		0x100
673 #define	VPD_2500_FUNC0_ADDR		0x48000
674 #define	VPD_2500_FUNC1_ADDR		0x48100
675 #define	VPD_8100_FUNC0_ADDR		0xD0000
676 #define	VPD_8100_FUNC1_ADDR		0xD0400
677 #define	VPD_8021_FUNC0_ADDR		0xFA300
678 #define	VPD_8021_FUNC1_ADDR		0xFA300
679 #define	VPD_8300_FC_FUNC0_ADDR		0x270000
680 #define	VPD_8300_FC_FUNC1_ADDR		0x270100
681 #define	VPD_8300_FCOE_FUNC0_ADDR	0xFA300
682 #define	VPD_8300_FCOE_FUNC1_ADDR	0xFA300
683 #define	VPD_2700_FUNC0_ADDR		0x270000
684 #define	VPD_2700_FUNC1_ADDR		0x270100
685 #define	VPD_2700_FUNC2_ADDR		0x270200
686 #define	VPD_2700_FUNC3_ADDR		0x270300
687 #define	VPD_SIZE			0x80
688 
689 #define	FLASH_2200_FIRMWARE_ADDR	0x20000
690 #define	FLASH_2300_FIRMWARE_ADDR	0x20000
691 #define	FLASH_2400_FIRMWARE_ADDR	0x20000
692 #define	FLASH_2500_FIRMWARE_ADDR	0x20000
693 #define	FLASH_8100_FIRMWARE_ADDR	0xA0000
694 #define	FLASH_8021_FIRMWARE_ADDR	0x40000
695 #define	FLASH_8021_FIRMWARE_SIZE	0x80000
696 #define	FLASH_8300_FC_FIRMWARE_ADDR	0x240000
697 #define	FLASH_8300_FCOE_FIRMWARE_ADDR	0x220000
698 #define	FLASH_8300_FIRMWARE_SIZE	0x20000
699 #define	FLASH_2700_FIRMWARE_ADDR	0x240000
700 #define	FLASH_2700_FIRMWARE_SIZE	0x20000
701 
702 #define	FLASH_8021_BOOTLOADER_ADDR	0x4000
703 #define	FLASH_8021_BOOTLOADER_SIZE	0x8000
704 #define	FLASH_8300_BOOTLOADER_ADDR	0x4000
705 #define	FLASH_8300_BOOTLOADER_SIZE	0x8000
706 
707 #define	FLASH_2200_BOOT_CODE_ADDR	0
708 #define	FLASH_2300_BOOT_CODE_ADDR	0
709 #define	FLASH_2400_BOOT_CODE_ADDR	0
710 #define	FLASH_2500_BOOT_CODE_ADDR	0
711 #define	FLASH_2700_BOOT_CODE_ADDR	0x200000
712 #define	FLASH_8100_BOOT_CODE_ADDR	0x80000
713 #define	FLASH_8021_BOOT_CODE_ADDR	0x20000
714 #define	FLASH_8300_BOOT_CODE_ADDR	0x200000
715 
716 #define	BEACON_8300_FC_FUNC0_ADDR	0x00201320
717 #define	BEACON_8300_FC_FUNC1_ADDR	0x00201328
718 #define	BEACON_8300_FCOE_FUNC0_ADDR	0x00201324
719 #define	BEACON_8300_FCOE_FUNC1_ADDR	0x0020132c
720 #define	BEACON_2700_FUNC0_ADDR		0x00201320
721 #define	BEACON_2700_FUNC1_ADDR		0x00201328
722 #define	BEACON_2700_FUNC2_ADDR		0x00201330
723 #define	BEACON_2700_FUNC3_ADDR		0x00201338
724 
725 #define	FLASH_2400_ERRLOG_START_ADDR_0	0
726 #define	FLASH_2400_ERRLOG_START_ADDR_1	0
727 #define	FLASH_2500_ERRLOG_START_ADDR_0	0x54000
728 #define	FLASH_2500_ERRLOG_START_ADDR_1	0x54400
729 #define	FLASH_8100_ERRLOG_START_ADDR_0	0xDC000
730 #define	FLASH_8100_ERRLOG_START_ADDR_1	0xDC400
731 #define	FLASH_8300_ERRLOG_START_ADDR_0	0x280000
732 #define	FLASH_8300_ERRLOG_START_ADDR_1	0x280400
733 #define	FLASH_ERRLOG_SIZE		0x200
734 #define	FLASH_ERRLOG_ENTRY_SIZE		4
735 
736 #define	FLASH_2400_DESCRIPTOR_TABLE	0
737 #define	FLASH_2500_DESCRIPTOR_TABLE	0x50000
738 #define	FLASH_8100_DESCRIPTOR_TABLE	0xD8000
739 #define	FLASH_8021_DESCRIPTOR_TABLE	0
740 #define	FLASH_8300_DESCRIPTOR_TABLE	0xFC000
741 #define	FLASH_2700_DESCRIPTOR_TABLE	0xFC000
742 
743 #define	FLASH_2400_LAYOUT_TABLE		0x11400
744 #define	FLASH_2500_LAYOUT_TABLE		0x50400
745 #define	FLASH_8100_LAYOUT_TABLE		0xD8400
746 #define	FLASH_8021_LAYOUT_TABLE		0xFC400
747 #define	FLASH_8300_LAYOUT_TABLE		0xFC400
748 #define	FLASH_2700_LAYOUT_TABLE		0xFC400
749 
750 /*
751  * Flash Error Log Event Codes.
752  */
753 #define	FLASH_ERRLOG_AEN_8002		0x8002
754 #define	FLASH_ERRLOG_AEN_8003		0x8003
755 #define	FLASH_ERRLOG_AEN_8004		0x8004
756 #define	FLASH_ERRLOG_RESET_ERR		0xF00B
757 #define	FLASH_ERRLOG_ISP_ERR		0xF020
758 #define	FLASH_ERRLOG_PARITY_ERR		0xF022
759 #define	FLASH_ERRLOG_NVRAM_CHKSUM_ERR	0xF023
760 #define	FLASH_ERRLOG_FLASH_FW_ERR	0xF024
761 
762 #define	VPD_TAG_END		0x78
763 #define	VPD_TAG_CHKSUM		"RV"
764 #define	VPD_TAG_SN		"SN"
765 #define	VPD_TAG_PN		"PN"
766 #define	VPD_TAG_PRODID		"\x82"
767 #define	VPD_TAG_LRT		0x90
768 #define	VPD_TAG_LRTC		0x91
769 
770 /*
771  * RISC to Host Status register definitions.
772  */
773 #define	RH_RISC_INT		BIT_15		/* RISC to Host Intrpt Req */
774 #define	RH_RISC_PAUSED		BIT_8		/* RISC Paused bit. */
775 
776 /*
777  * RISC to Host Status register status field definitions.
778  */
779 #define	ROM_MBX_SUCCESS		0x01
780 #define	ROM_MBX_ERR		0x02
781 #define	MBX_SUCCESS		0x10
782 #define	MBX_ERR			0x11
783 #define	ASYNC_EVENT		0x12
784 #define	RESP_UPDATE		0x13
785 #define	MULTI_Q_RSP_UPDATE	0x14
786 #define	SCSI_FAST_POST_16	0x15
787 #define	SCSI_FAST_POST_32	0x16
788 #define	CTIO_FAST_POST		0x17
789 #define	IP_FAST_POST_XMT	0x18
790 #define	IP_FAST_POST_RCV	0x19
791 #define	IP_FAST_POST_BRD	0x1a
792 #define	IP_FAST_POST_RCV_ALN	0x1b
793 #define	ATIO_UPDATE		0x1c
794 #define	ATIO_RESP_UPDATE	0x1d
795 
796 /*
797  * HCCR commands.
798  */
799 #define	HC_RESET_RISC		0x1000	/* Reset RISC */
800 #define	HC_PAUSE_RISC		0x2000	/* Pause RISC */
801 #define	HC_RELEASE_RISC		0x3000	/* Release RISC from reset. */
802 #define	HC_DISABLE_PARITY_PAUSE	0x4001	/* qla2200/2300 - disable parity err */
803 					/* RISC pause. */
804 #define	HC_SET_HOST_INT		0x5000	/* Set host interrupt */
805 #define	HC_CLR_HOST_INT		0x6000	/* Clear HOST interrupt */
806 #define	HC_CLR_RISC_INT		0x7000	/* Clear RISC interrupt */
807 #define	HC_HOST_INT		BIT_7	/* Host interrupt bit */
808 #define	HC_RISC_PAUSE		BIT_5	/* Pause mode bit */
809 
810 /*
811  * HCCR commands for 24xx and 25xx.
812  */
813 #define	HC24_RESET_RISC		0x10000000	/* Reset RISC */
814 #define	HC24_CLEAR_RISC_RESET	0x20000000	/* Release RISC from reset. */
815 #define	HC24_PAUSE_RISC		0x30000000	/* Pause RISC */
816 #define	HC24_RELEASE_PAUSE	0x40000000	/* Release RISC from pause */
817 #define	HC24_SET_HOST_INT	0x50000000	/* Set host interrupt */
818 #define	HC24_CLR_HOST_INT	0x60000000	/* Clear HOST interrupt */
819 #define	HC24_CLR_RISC_INT	0xA0000000	/* Clear RISC interrupt */
820 #define	HC24_HOST_INT		BIT_6		/* Host to RISC intrpt bit */
821 #define	HC24_RISC_RESET		BIT_5		/* RISC Reset mode bit. */
822 
823 /*
824  * ISP Initialization Control Blocks.
825  * Little endian except where noted.
826  */
827 #define	ICB_VERSION		1
828 typedef struct ql_init_cb {
829 	uint8_t version;
830 	uint8_t reserved;
831 
832 	/*
833 	 * LSB BIT 0  = enable_hard_loop_id
834 	 * LSB BIT 1  = enable_fairness
835 	 * LSB BIT 2  = enable_full_duplex
836 	 * LSB BIT 3  = enable_fast_posting
837 	 * LSB BIT 4  = enable_target_mode
838 	 * LSB BIT 5  = disable_initiator_mode
839 	 * LSB BIT 6  = enable_adisc
840 	 * LSB BIT 7  = enable_target_inquiry_data
841 	 *
842 	 * MSB BIT 0  = enable_port_update_ae
843 	 * MSB BIT 1  = disable_initial_lip
844 	 * MSB BIT 2  = enable_decending_soft_assign
845 	 * MSB BIT 3  = previous_assigned_addressing
846 	 * MSB BIT 4  = enable_stop_q_on_full
847 	 * MSB BIT 5  = enable_full_login_on_lip
848 	 * MSB BIT 6  = enable_node_name
849 	 * MSB BIT 7  = extended_control_block
850 	 */
851 	uint8_t firmware_options[2];
852 
853 	uint8_t max_frame_length[2];
854 	uint8_t max_iocb_allocation[2];
855 	uint8_t execution_throttle[2];
856 	uint8_t login_retry_count;
857 	uint8_t retry_delay;			/* unused */
858 	uint8_t port_name[8];			/* Big endian. */
859 	uint8_t hard_address[2];		/* option bit 0 */
860 	uint8_t inquiry;			/* option bit 7 */
861 	uint8_t login_timeout;
862 	uint8_t node_name[8];			/* Big endian */
863 	uint8_t request_q_outpointer[2];
864 	uint8_t response_q_inpointer[2];
865 	uint8_t request_q_length[2];
866 	uint8_t response_q_length[2];
867 	uint8_t request_q_address[8];
868 	uint8_t response_q_address[8];
869 	uint8_t lun_enables[2];
870 	uint8_t command_resouce_count;
871 	uint8_t immediate_notify_resouce_count;
872 	uint8_t timeout[2];
873 	uint8_t reserved_2[2];
874 
875 	/*
876 	 * LSB BIT 0 = Timer operation mode bit 0
877 	 * LSB BIT 1 = Timer operation mode bit 1
878 	 * LSB BIT 2 = Timer operation mode bit 2
879 	 * LSB BIT 3 = Timer operation mode bit 3
880 	 * LSB BIT 4 = P2P Connection option bit 0
881 	 * LSB BIT 5 = P2P Connection option bit 1
882 	 * LSB BIT 6 = P2P Connection option bit 2
883 	 * LSB BIT 7 = Enable Non part on LIHA failure
884 	 *
885 	 * MSB BIT 0 = Enable class 2
886 	 * MSB BIT 1 = Enable ACK0
887 	 * MSB BIT 2 =
888 	 * MSB BIT 3 =
889 	 * MSB BIT 4 = FC Tape Enable
890 	 * MSB BIT 5 = Enable FC Confirm
891 	 * MSB BIT 6 = Enable CRN
892 	 * MSB BIT 7 =
893 	 */
894 	uint8_t	add_fw_opt[2];
895 
896 	uint8_t	response_accumulation_timer;
897 	uint8_t	interrupt_delay_timer;
898 
899 	/*
900 	 * LSB BIT 0 = Enable Read xfr_rdy
901 	 * LSB BIT 1 = Soft ID only
902 	 * LSB BIT 2 =
903 	 * LSB BIT 3 =
904 	 * LSB BIT 4 = FCP RSP Payload [0]
905 	 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
906 	 * LSB BIT 6 =
907 	 * LSB BIT 7 =
908 	 *
909 	 * MSB BIT 0 = Sbus enable - 2300
910 	 * MSB BIT 1 =
911 	 * MSB BIT 2 =
912 	 * MSB BIT 3 =
913 	 * MSB BIT 4 =
914 	 * MSB BIT 5 = enable 50 ohm termination
915 	 * MSB BIT 6 = Data Rate (2300 only)
916 	 * MSB BIT 7 = Data Rate (2300 only)
917 	 */
918 	uint8_t	special_options[2];
919 
920 	uint8_t	reserved_3[26];
921 } ql_init_cb_t;
922 
923 /*
924  * Virtual port definition.
925  */
926 typedef struct ql_vp_cfg {
927 	uint8_t	reserved[2];
928 	uint8_t	options;
929 	uint8_t	hard_prev_addr;
930 	uint8_t	port_name[8];
931 	uint8_t	node_name[8];
932 } ql_vp_cfg_t;
933 
934 /*
935  * VP options.
936  */
937 #define	VPO_ENABLE_SNS_LOGIN_SCR	BIT_6
938 #define	VPO_TARGET_MODE_DISABLED	BIT_5
939 #define	VPO_INITIATOR_MODE_ENABLED	BIT_4
940 #define	VPO_ENABLED			BIT_3
941 #define	VPO_ID_NOT_ACQUIRED		BIT_2
942 #define	VPO_PREVIOUSLY_ASSIGNED_ID	BIT_1
943 #define	VPO_HARD_ASSIGNED_ID		BIT_0
944 
945 #define	ICB_24XX_VERSION	1
946 typedef struct ql_init_24xx_cb {
947 	uint8_t version[2];
948 	uint8_t reserved_1[2];
949 	uint8_t max_frame_length[2];
950 	uint8_t execution_throttle[2];
951 	uint8_t exchange_count[2];
952 	uint8_t hard_address[2];
953 	uint8_t port_name[8];	/* Big endian. */
954 	uint8_t node_name[8];	/* Big endian. */
955 
956 	uint8_t response_q_inpointer[2];
957 	uint8_t request_q_outpointer[2];
958 
959 	uint8_t login_retry_count[2];
960 
961 	uint8_t prio_request_q_outpointer[2];
962 
963 	uint8_t response_q_length[2];
964 	uint8_t request_q_length[2];
965 
966 	uint8_t link_down_on_nos[2];
967 
968 	uint8_t prio_request_q_length[2];
969 	uint8_t request_q_address[8];
970 	uint8_t response_q_address[8];
971 	uint8_t prio_request_q_address[8];
972 	uint8_t msi_x_vector[2];
973 	uint8_t reserved_2[6];
974 	uint8_t atio_q_inpointer[2];
975 	uint8_t atio_q_length[2];
976 	uint8_t atio_q_address[8];
977 
978 	uint8_t interrupt_delay_timer[2];	/* 100us per */
979 	uint8_t login_timeout[2];
980 	/*
981 	 * BIT 0  = Hard Assigned Loop ID
982 	 * BIT 1  = Enable Fairness
983 	 * BIT 2  = Enable Full-Duplex
984 	 * BIT 3  = Reserved
985 	 * BIT 4  = Target Mode Enable
986 	 * BIT 5  = Initiator Mode Disable
987 	 * BIT 6  = Reserved
988 	 * BIT 7  = Reserved
989 	 *
990 	 * BIT 8  = Reserved
991 	 * BIT 9  = Disable Initial LIP
992 	 * BIT 10 = Descending Loop ID Search
993 	 * BIT 11 = Previous Assigned Loop ID
994 	 * BIT 12 = Reserved
995 	 * BIT 13 = Full Login after LIP
996 	 * BIT 14 = Node Name Option
997 	 * BIT 15-31 = Reserved
998 	 */
999 	uint8_t	firmware_options_1[4];
1000 
1001 	/*
1002 	 * BIT 0  = Operation Mode bit 0
1003 	 * BIT 1  = Operation Mode bit 1
1004 	 * BIT 2  = Operation Mode bit 2
1005 	 * BIT 3  = Operation Mode bit 3
1006 	 * BIT 4  = Connection Options bit 0
1007 	 * BIT 5  = Connection Options bit 1
1008 	 * BIT 6  = Connection Options bit 2
1009 	 * BIT 7  = Enable Non part on LIHA failure
1010 	 *
1011 	 * BIT 8  = Enable Class 2
1012 	 * BIT 9  = Enable ACK0
1013 	 * BIT 10 = Reserved
1014 	 * BIT 11 = Enable FC-SP Security
1015 	 * BIT 12 = FC Tape Enable
1016 	 * BIT 13 = Reserved
1017 	 * BIT 14 = Target PRLI Control
1018 	 * BIT 15 = Reserved
1019 	 *
1020 	 * BIT 16  = Enable Emulated MSIX
1021 	 * BIT 17  = Reserved
1022 	 * BIT 18  = Enable Alternate Device Number
1023 	 * BIT 19  = Enable Alternate Bus Number
1024 	 * BIT 20  = Enable Translated Address
1025 	 * BIT 21  = Enable VM Security
1026 	 * BIT 22  = Enable Interrupt Handshake
1027 	 * BIT 23  = Enable Multiple Queue
1028 	 *
1029 	 * BIT 24  = IOCB Security
1030 	 * BIT 25  = qos
1031 	 * BIT 26-31 = Reserved
1032 	 */
1033 	uint8_t firmware_options_2[4];
1034 
1035 	/*
1036 	 * BIT 0  = Reserved
1037 	 * BIT 1  = Soft ID only
1038 	 * BIT 2  = Reserved
1039 	 * BIT 3  = Reserved
1040 	 * BIT 4  = FCP RSP Payload bit 0
1041 	 * BIT 5  = FCP RSP Payload bit 1
1042 	 * BIT 6  = Enable Rec Out-of-Order data frame handling
1043 	 * BIT 7  = Disable Automatic PLOGI on Local Loop
1044 	 *
1045 	 * BIT 8  = Reserved
1046 	 * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative
1047 	 *	    offset handling
1048 	 * BIT 10 = Reserved
1049 	 * BIT 11 = Reserved
1050 	 * BIT 12 = Reserved
1051 	 * BIT 13 = Data Rate bit 0
1052 	 * BIT 14 = Data Rate bit 1
1053 	 * BIT 15 = Data Rate bit 2
1054 	 *
1055 	 * BIT 16 = 75-ohm Termination Select
1056 	 * BIT 17 = Enable Multiple FCFs
1057 	 * BIT 18 = MAC Addressing Mode
1058 	 * BIT 19 = MAC Addressing Mode
1059 	 * BIT 20 = MAC Addressing Mode
1060 	 * BIT 21 = Ethernet Data Rate
1061 	 * BIT 22 = Ethernet Data Rate
1062 	 * BIT 23 = Ethernet Data Rate
1063 	 *
1064 	 * BIT 24 = Ethernet Data Rate
1065 	 * BIT 25 = Ethernet Data Rate
1066 	 * BIT 26 = Enable Ethernet Header ATIO Queue
1067 	 * BIT 27 = Enable Ethernet Header Response Queue
1068 	 * BIT 28 = SPMA Selection
1069 	 * BIT 29 = SPMA Selection
1070 	 * BIT 30 = Reserved
1071 	 * BIT 31 = Reserved
1072 	 */
1073 	uint8_t firmware_options_3[4];
1074 
1075 	uint8_t	qos[2];
1076 	uint8_t	rid[2];
1077 
1078 	uint8_t	reserved_3[4];
1079 
1080 	uint8_t	enode_mac_addr[6];
1081 
1082 	uint8_t	reserved_4[10];
1083 
1084 	/*
1085 	 * Multi-ID firmware.
1086 	 */
1087 	uint8_t	vp_count[2];
1088 
1089 	/*
1090 	 * BIT 1  = Allows mode 2 connection option
1091 	 */
1092 	uint8_t		global_vp_option[2];
1093 
1094 	ql_vp_cfg_t	vpc[MAX_25_VIRTUAL_PORTS + 1];
1095 
1096 	/*
1097 	 * Extended Initialization Control Block
1098 	 */
1099 	ql_ext_icb_8100_t	ext_blk;
1100 } ql_init_24xx_cb_t;
1101 
1102 typedef union ql_comb_init_cb {
1103 	ql_init_cb_t		cb;
1104 	ql_init_24xx_cb_t	cb24;
1105 } ql_comb_init_cb_t;
1106 
1107 /*
1108  * ISP IP Initialization Control Block.
1109  * Little endian except where noted.
1110  */
1111 #define	IP_ICB_VERSION	1
1112 typedef struct ql_ip_init_cb {
1113 	uint8_t	version;
1114 	uint8_t	reserved;
1115 
1116 	/*
1117 	 * LSB BIT 0  = receive_buffer_address_length
1118 	 * LSB BIT 1  = fast post broadcast received
1119 	 * LSB BIT 2  = allow out of receive buffers AE
1120 	 */
1121 	uint8_t ip_firmware_options[2];
1122 	uint8_t ip_header_size[2];
1123 	uint8_t mtu_size[2];			/* max value is 65280 */
1124 	uint8_t buf_size[2];
1125 	uint8_t reserved_1[8];
1126 	uint8_t queue_size[2];			/* 8-1024 */
1127 	uint8_t low_water_mark[2];
1128 	uint8_t queue_address[8];
1129 	uint8_t queue_inpointer[2];
1130 	uint8_t fast_post_reg_count[2];		/* 0-14 */
1131 	uint8_t cc[2];
1132 	uint8_t reserved_2[28];
1133 } ql_ip_init_cb_t;
1134 
1135 #define	IP_ICB_24XX_VERSION	1
1136 typedef struct ql_ip_init_24xx_cb {
1137 	uint8_t	version;
1138 	uint8_t	reserved;
1139 	/*
1140 	 * LSB BIT 2  = allow out of receive buffers AE
1141 	 */
1142 	uint8_t ip_firmware_options[2];
1143 	uint8_t ip_header_size[2];
1144 	uint8_t mtu_size[2];
1145 	uint8_t buf_size[2];
1146 	uint8_t reserved_1[10];
1147 	uint8_t low_water_mark[2];
1148 	uint8_t reserved_3[12];
1149 	uint8_t cc[2];
1150 	uint8_t reserved_2[28];
1151 } ql_ip_init_24xx_cb_t;
1152 
1153 typedef union ql_comb_ip_init_cb {
1154 	ql_ip_init_cb_t		cb;
1155 	ql_ip_init_24xx_cb_t	cb24;
1156 } ql_comb_ip_init_cb_t;
1157 
1158 /*
1159  * f/w module table
1160  */
1161 struct fw_table {
1162 	uint32_t	fw_class;
1163 	int8_t		*fw_version;
1164 };
1165 
1166 /*
1167  * DMA memory type.
1168  */
1169 typedef enum mem_alloc_type {
1170 	UNKNOWN_MEMORY,
1171 	TASK_MEMORY,
1172 	LITTLE_ENDIAN_DMA,
1173 	BIG_ENDIAN_DMA,
1174 	KERNEL_MEM,
1175 	NO_SWAP_DMA
1176 } mem_alloc_type_t;
1177 
1178 /*
1179  * DMA memory alignment type.
1180  */
1181 typedef enum men_align_type {
1182 	QL_DMA_DATA_ALIGN,
1183 	QL_DMA_RING_ALIGN,
1184 } mem_alignment_t;
1185 
1186 /*
1187  * DMA memory object.
1188  */
1189 typedef struct dma_mem {
1190 	uint64_t		alignment;
1191 	void			*bp;
1192 	ddi_dma_cookie_t	*cookies;
1193 	ddi_acc_handle_t	acc_handle;
1194 	ddi_dma_handle_t	dma_handle;
1195 	ddi_dma_cookie_t	cookie;
1196 	uint32_t		max_cookie_count;
1197 	uint32_t		cookie_count;
1198 	uint32_t		size;
1199 	uint32_t		memflags;
1200 	mem_alloc_type_t	type;
1201 	uint32_t		flags;		/* Solaris DMA flags. */
1202 } dma_mem_t;
1203 
1204 /*
1205  * 24 bit port ID type definition.
1206  */
1207 typedef union {
1208 	struct {
1209 		uint8_t d_id[3];
1210 		uint8_t rsvd_1;
1211 	}r;
1212 
1213 	uint32_t	b24 : 24;
1214 
1215 #if defined(_BIT_FIELDS_LTOH)
1216 	struct {
1217 		uint8_t al_pa;
1218 		uint8_t area;
1219 		uint8_t domain;
1220 		uint8_t rsvd_1;
1221 	}b;
1222 #elif defined(_BIT_FIELDS_HTOL)
1223 	struct {
1224 		uint8_t domain;
1225 		uint8_t area;
1226 		uint8_t al_pa;
1227 		uint8_t rsvd_1;
1228 	}b;
1229 #else
1230 #error One of _BIT_FIELDS_LTOH or _BIT_FIELDS_HTOL must be defined
1231 #endif
1232 } port_id_t;
1233 
1234 /*
1235  * Link list definitions.
1236  */
1237 typedef struct ql_link {
1238 	struct ql_link	*prev;
1239 	struct ql_link	*next;
1240 	void		*base_address;
1241 	struct ql_head	*head;	/* the queue this link is on */
1242 } ql_link_t;
1243 
1244 typedef struct ql_head {
1245 	ql_link_t	*first;
1246 	ql_link_t	*last;
1247 } ql_head_t;
1248 
1249 /*
1250  * ISP request queue context
1251  */
1252 typedef struct ql_request_q {
1253 	struct cmd_entry	*req_ring_ptr;
1254 	dma_mem_t		req_ring;
1255 	uint32_t		*req_out_shadow_ptr;
1256 	uint32_t		req_out_shadow_ofst;
1257 	uint32_t		mbar_req_in;
1258 	uint32_t		mbar_req_out;
1259 	uint16_t		req_ring_index;
1260 	uint16_t		req_entry_cnt;
1261 	uint16_t		req_q_cnt;	/* # of available entries. */
1262 	uint16_t		req_q_number;
1263 } ql_request_q_t;
1264 
1265 /*
1266  * ISP response queue context
1267  */
1268 typedef struct ql_response_q {
1269 	struct ql_srb		*status_srb;
1270 	struct sts_entry	*rsp_ring_ptr;
1271 	dma_mem_t		rsp_ring;
1272 	kmutex_t		intr_mutex;
1273 	uint32_t		*rsp_in_shadow_ptr;
1274 	uint32_t		rsp_in_shadow_ofst;
1275 	uint32_t		mbar_rsp_in;
1276 	uint32_t		mbar_rsp_out;
1277 	uint16_t		rsp_ring_index;
1278 	uint16_t		rsp_entry_cnt;
1279 	uint16_t		isp_rsp_index;
1280 	uint16_t		rsp_q_number;
1281 	uint16_t		msi_x_vector;
1282 } ql_response_q_t;
1283 
1284 /*
1285  * This is the per-command structure
1286  */
1287 typedef struct ql_srb {
1288 	/* Command link. */
1289 	ql_link_t		cmd;
1290 
1291 	/* Watchdog link and timer. */
1292 	ql_link_t		wdg;
1293 	time_t			wdg_q_time;
1294 	time_t			init_wdg_q_time;
1295 	uint16_t		isp_timeout;
1296 
1297 	/* FCA and FC Transport data. */
1298 	fc_packet_t		*pkt;
1299 	struct ql_adapter_state	*ha;
1300 	uint32_t		magic_number;
1301 
1302 	/* unsolicited buffer context. */
1303 	dma_mem_t		ub_buffer;
1304 	uint32_t		ub_type;
1305 	uint32_t		ub_size;
1306 
1307 	/* FCP command. */
1308 	fcp_cmd_t		*fcp;
1309 
1310 	/* Request sense. */
1311 	uint32_t		request_sense_length;
1312 	caddr_t			request_sense_ptr;
1313 
1314 	/* Device queue pointer. */
1315 	struct ql_lun		*lun_queue;
1316 
1317 	/* Command state/status flags. */
1318 	volatile uint32_t	flags;
1319 
1320 	/* Command IOCB context. */
1321 	void			(*iocb)(struct ql_adapter_state *,
1322 	    ql_request_q_t *, struct ql_srb *, void *);
1323 	struct cmd_entry	*request_ring_ptr;
1324 	uint32_t		handle;
1325 	uint16_t		req_q_number;
1326 	uint16_t		req_cnt;
1327 	uint8_t			retry_count;
1328 	uint8_t			rsp_q_number;
1329 	dma_mem_t		sg_dma;
1330 } ql_srb_t;
1331 
1332 #define	SRB_ISP_STARTED		BIT_0 /* Command sent to ISP. */
1333 #define	SRB_ISP_COMPLETED	BIT_1 /* ISP finished with command. */
1334 #define	SRB_RETRY		BIT_2 /* Driver retrying command. */
1335 #define	SRB_POLL		BIT_3 /* Poll for completion. */
1336 
1337 #define	SRB_WATCHDOG_ENABLED	BIT_4 /* Command on watchdog list. */
1338 #define	SRB_ELS_PKT		BIT_5 /* Extended Link Services pkt */
1339 #define	SRB_UB_IN_FCA		BIT_6 /* FCA holds unsolicited buffer */
1340 #define	SRB_UB_IN_ISP		BIT_7 /* ISP holds unsolicited buffer */
1341 
1342 #define	SRB_UB_CALLBACK		BIT_8 /* Unsolicited callback needed. */
1343 #define	SRB_UB_RSCN		BIT_9 /* Unsolicited RSCN callback. */
1344 #define	SRB_UB_FCP		BIT_10 /* Unsolicited RSCN callback. */
1345 #define	SRB_FCP_CMD_PKT		BIT_11 /* FCP command type packet. */
1346 
1347 #define	SRB_FCP_DATA_PKT	BIT_12 /* FCP data type packet. */
1348 #define	SRB_FCP_RSP_PKT		BIT_13 /* FCP response type packet. */
1349 #define	SRB_IP_PKT		BIT_14 /* IP type packet. */
1350 #define	SRB_GENERIC_SERVICES_PKT BIT_15 /* Generic services type packet */
1351 
1352 #define	SRB_COMMAND_TIMEOUT	BIT_16 /* Command timed out. */
1353 #define	SRB_ABORTING		BIT_17 /* SRB aborting. */
1354 #define	SRB_IN_DEVICE_QUEUE	BIT_18 /* In Device Queue */
1355 #define	SRB_IN_TOKEN_ARRAY	BIT_19 /* In Token Array */
1356 
1357 #define	SRB_UB_FREE_REQUESTED	BIT_20 /* UB Free requested */
1358 #define	SRB_UB_ACQUIRED		BIT_21 /* UB selected for upcall */
1359 #define	SRB_MS_PKT		BIT_22 /* Management Service pkt */
1360 
1361 /*
1362  * This byte will be used to define flags for the LUN on the target.
1363  * Presently, we have untagged-command as one flag. Others can be
1364  * added later, if needed.
1365  */
1366 typedef struct tgt_lun_flags {
1367 	uint8_t
1368 		untagged_pending:1,
1369 		unused_bits:7;
1370 } tgt_lun_flags_t;
1371 
1372 #define	QL_IS_UNTAGGED_PENDING(q, lun_num) \
1373 	((q->lun_flags[lun_num].untagged_pending == TRUE) ? 1 : 0)
1374 #define	QL_SET_UNTAGGED_PENDING(q, lun_num) \
1375 	(q->lun_flags[lun_num].untagged_pending = TRUE)
1376 #define	QL_CLEAR_UNTAGGED_PENDING(q, lun_num) \
1377 	(q->lun_flags[lun_num].untagged_pending = FALSE)
1378 
1379 /*
1380  * Fibre Channel LUN Queue structure
1381  */
1382 typedef struct ql_lun {
1383 	/* Head command link. */
1384 	ql_head_t		cmd;
1385 
1386 	struct ql_target	*target_queue;
1387 
1388 	uint32_t		flags;
1389 
1390 	/* LUN execution throttle. */
1391 	uint16_t		lun_outcnt;
1392 
1393 	/* LUN number as reported by REPORT LUNS */
1394 	uint16_t		lun_no;
1395 
1396 	/*
1397 	 * Logical unit number in SCSI3 format, also
1398 	 * referred to as FCP lun or FCP entity address.
1399 	 */
1400 	uint64_t		lun_addr;
1401 
1402 	ql_link_t		link;
1403 } ql_lun_t;
1404 
1405 /*
1406  * LUN Queue flags
1407  */
1408 #define	LQF_UNTAGGED_PENDING	BIT_0
1409 
1410 /*
1411  * SCSI standard defined lun addressing methods.
1412  */
1413 #define	QL_LUN_AM_MASK		0xC0	/* Address Method Mask */
1414 #define	QL_LUN_AM_PDEV		0x00	/* Peripheral device AM */
1415 #define	QL_LUN_AM_FLAT		0x40	/* Flat space AM */
1416 #define	QL_LUN_AM_LUN		0x80	/* Logical unit AM */
1417 #define	QL_LUN_AM_EFLAT		0xC0	/* Extended flat space AM */
1418 #define	QL_LUN_AM_ELUN		0xC0	/* Extended logical unit AM */
1419 
1420 /*
1421  * Fibre Channel Device Queue structure
1422  */
1423 typedef struct ql_target {
1424 	/* Device queue lock. */
1425 	kmutex_t		mutex;
1426 
1427 	volatile uint32_t	flags;
1428 	port_id_t		d_id;
1429 	uint16_t		loop_id;
1430 	volatile uint16_t	outcnt;		/* # of cmds running in ISP */
1431 	uint32_t		iidma_rate;
1432 
1433 	/* Device link. */
1434 	ql_link_t		device;
1435 
1436 	/* Head watchdog link. */
1437 	ql_head_t		wdg;
1438 
1439 	/* Unsolicited buffer IP data. */
1440 	uint32_t		ub_frame_ro;
1441 	uint16_t		ub_sequence_length;
1442 	uint16_t		ub_loop_id;
1443 	uint8_t			ub_total_seg_cnt;
1444 	uint8_t			ub_seq_cnt;
1445 	uint8_t			ub_seq_id;
1446 
1447 	/* Port down retry counter. */
1448 	uint16_t		port_down_retry_count;
1449 	uint16_t		qfull_retry_count;
1450 
1451 	/* logout sent state */
1452 	uint8_t			logout_sent;
1453 
1454 	/* Data from Port database matches machine type. */
1455 	uint8_t			master_state;
1456 	uint8_t			slave_state;
1457 	port_id_t		hard_addr;
1458 	uint8_t			port_name[8];
1459 	uint8_t			node_name[8];
1460 	uint16_t		cmn_features;
1461 	uint16_t		conc_sequences;
1462 	uint16_t		relative_offset;
1463 	uint16_t		class3_recipient_ctl;
1464 	uint16_t		class3_rcv_data_size;
1465 	uint16_t		class3_conc_sequences;
1466 	uint16_t		class3_open_sequences_per_exch;
1467 	uint16_t		prli_payload_length;
1468 	uint16_t		prli_svc_param_word_0;
1469 	uint16_t		prli_svc_param_word_3;
1470 
1471 	/* LUN context. */
1472 	ql_head_t		lun_queues;
1473 	ql_lun_t		*last_lun_queue;
1474 } ql_tgt_t;
1475 
1476 /*
1477  * Target Queue flags
1478  */
1479 #define	TQF_TAPE_DEVICE		BIT_0
1480 #define	TQF_QUEUE_SUSPENDED	BIT_1  /* Queue suspended. */
1481 #define	TQF_FABRIC_DEVICE	BIT_2
1482 #define	TQF_INITIATOR_DEVICE	BIT_3
1483 #define	TQF_RSCN_RCVD		BIT_4
1484 #define	TQF_NEED_AUTHENTICATION	BIT_5
1485 #define	TQF_PLOGI_PROGRS	BIT_6
1486 #define	TQF_IIDMA_NEEDED	BIT_7
1487 #define	TQF_LOGIN_NEEDED	BIT_8
1488 
1489 /*
1490  * Tempoary N_Port information
1491  */
1492 typedef struct ql_n_port_info {
1493 	uint16_t	n_port_handle;
1494 	uint8_t		port_name[8];	/* Big endian. */
1495 	uint8_t		node_name[8];	/* Big endian. */
1496 	port_id_t	d_id;
1497 } ql_n_port_info_t;
1498 
1499 /*
1500  * iiDMA
1501  */
1502 #define	IIDMA_RATE_INIT		0xffffffff	/* init state */
1503 #define	IIDMA_RATE_NDEF		0xfffffffe	/* not defined in conf file */
1504 #define	IIDMA_RATE_1GB		0x0
1505 #define	IIDMA_RATE_2GB		0x1
1506 #define	IIDMA_RATE_AUTO		0x2
1507 #define	IIDMA_RATE_4GB		0x3
1508 #define	IIDMA_RATE_8GB		0x4
1509 #define	IIDMA_RATE_16GB		0x5
1510 #define	IIDMA_RATE_32GB		0x6
1511 #define	IIDMA_RATE_10GB		0x13
1512 #define	IIDMA_RATE_MAX		IIDMA_RATE_10GB
1513 
1514 /*
1515  * Kernel statistic structure definitions.
1516  */
1517 typedef struct ql_device_stat {
1518 	int logouts_recvd;
1519 	int task_mgmt_failures;
1520 	int data_ro_mismatches;
1521 	int dl_len_mismatches;
1522 } ql_device_stat_t;
1523 
1524 typedef struct ql_adapter_24xx_stat {
1525 	int version;			/* version of this struct */
1526 	int lip_count;			/* lips forced  */
1527 	int ncmds;			/* outstanding commands */
1528 	ql_adapter_revlvl_t revlvl;	/* adapter revision levels */
1529 	ql_device_stat_t d_stats[MAX_24_FIBRE_DEVICES]; /* per device stats */
1530 } ql_adapter_stat_t;
1531 
1532 /*
1533  * Firmware code segment.
1534  */
1535 #define	MAX_RISC_CODE_SEGMENTS 3
1536 typedef struct fw_code {
1537 	caddr_t			code;
1538 	uint32_t		addr;
1539 	uint32_t		length;
1540 } ql_fw_code_t;
1541 
1542 /* diagnostic els ECHO defines */
1543 #define	QL_ECHO_CMD		0x10000000	/* echo opcode */
1544 #define	QL_ECHO_CMD_LENGTH	220		/* command length */
1545 
1546 /* DUMP state flags. */
1547 #define	QL_DUMPING		BIT_0
1548 #define	QL_DUMP_VALID		BIT_1
1549 #define	QL_DUMP_UPLOADED	BIT_2
1550 
1551 #define	QL_LOG_ENTRIES	256		/* max # of EL entries */
1552 #define	QL_LOG_LENGTH	128		/* max # of bytes in each EL entry */
1553 
1554 typedef struct ql_trace_entry {
1555 	timespec_t	hs_time;	/* high resolution timestamp */
1556 	char		buf[QL_LOG_LENGTH];
1557 } ql_trace_entry_t;
1558 
1559 /* per instance based extended logging trace descriptor */
1560 typedef struct el_trace_desc {
1561 	kmutex_t	mutex;
1562 	uint32_t	nentries; /* max number of entries */
1563 	uint16_t	nindex;	/* next index to fill */
1564 	uint32_t	start;	/* starting point */
1565 	uint32_t	end;	/* ending point */
1566 	uint32_t	csize;	/* current filled queue size */
1567 	uint32_t	count;	/* sequence number */
1568 	size_t		trace_buffer_size;
1569 	ql_trace_entry_t *trace_buffer;
1570 } ql_trace_desc_t;
1571 
1572 /*
1573  * NVRAM cache descriptor.
1574  */
1575 typedef struct nvram_cache_desc {
1576 	uint32_t	valid;
1577 	uint32_t	size;
1578 	void		*cache;
1579 } nvram_cache_desc_t;
1580 
1581 /*
1582  * Plogi retry parameters
1583  */
1584 typedef struct plogi_params_desc {
1585 	uint32_t	retry_cnt;
1586 	uint32_t	retry_dly_usec;
1587 } plogi_params_desc_t;
1588 
1589 /*
1590  * ql attach progress indication
1591  */
1592 #define	QL_SOFT_STATE_ALLOCED		BIT_0
1593 #define	QL_REGS_MAPPED			BIT_1
1594 #define	QL_HBA_BUFFER_SETUP		BIT_2
1595 #define	QL_MUTEX_CV_INITED		BIT_3
1596 #define	QL_INTR_ADDED			BIT_4
1597 #define	QL_CONFIG_SPACE_SETUP		BIT_5
1598 #define	QL_TASK_DAEMON_STARTED		BIT_6
1599 #define	QL_KSTAT_CREATED		BIT_7
1600 #define	QL_MINOR_NODE_CREATED		BIT_8
1601 #define	QL_FCA_TRAN_ALLOCED		BIT_9
1602 #define	QL_FCA_ATTACH_DONE		BIT_10
1603 #define	QL_IOMAP_IOBASE_MAPPED		BIT_11
1604 #define	QL_N_PORT_INFO_CREATED		BIT_12
1605 #define	QL_DB_IOBASE_MAPPED		BIT_13
1606 #define	QL_FCA_INIT_FM			BIT_14
1607 #define	QL_NVRAM_CACHE_CREATED		BIT_15
1608 #define	QL_PLOGI_PARAMS_CREATED		BIT_16
1609 
1610 /* Device queue head list size (based on AL_PA address). */
1611 #define	DEVICE_HEAD_LIST_SIZE	0x81
1612 
1613 struct legacy_intr_set {
1614 	uint32_t	int_vec_bit;
1615 	uint32_t	tgt_status_reg;
1616 	uint32_t	tgt_mask_reg;
1617 	uint32_t	pci_int_reg;
1618 };
1619 
1620 /* Returned Mailbox registers. */
1621 typedef struct ql_mbx_data {
1622 	uint16_t	mb[MAX_MBOX_COUNT];
1623 } ql_mbx_data_t;
1624 
1625 typedef struct ql_ledstate {
1626 	uint32_t	BeaconState;
1627 	uint32_t	LEDflags;
1628 	uint32_t	flags;
1629 	uint32_t	led_blink_on;
1630 	uint32_t	select;
1631 	ql_mbx_data_t	cfg;
1632 } ql_ledstate_t;
1633 
1634 /*
1635  * Adapter state structure.
1636  */
1637 typedef struct ql_adapter_state {
1638 	ql_link_t		hba;
1639 
1640 	kmutex_t		mutex;
1641 	volatile uint64_t	flags;			/* State flags. */
1642 	uint32_t		state;
1643 	port_id_t		d_id;
1644 	uint16_t		loop_id;
1645 	uint16_t		sfp_stat;
1646 	uint16_t		idle_timer;
1647 	uint16_t		r_a_tov;	    /* 2 * R_A_TOV + 5 */
1648 	uint8_t			topology;
1649 	uint8_t			bbcr_runtime;
1650 	uint8_t			bbcr_initial;
1651 	uint8_t			loop_down_abort_time;
1652 	uint8_t			port_retry_timer;
1653 	uint8_t			loop_down_timer;
1654 	uint8_t			watchdog_timer;
1655 
1656 	/* Task Daemon context. */
1657 	ql_head_t		unsol_callback_queue;
1658 	ddi_taskq_t		*driver_thread_taskq;
1659 	kmutex_t		task_daemon_mutex;
1660 	kcondvar_t		cv_task_daemon;
1661 	kcondvar_t		cv_dr_suspended;
1662 	volatile uint64_t	task_daemon_flags;
1663 	uint32_t		driver_thread_awake;
1664 	uint64_t		df;
1665 	uint64_t		sf;
1666 	uint64_t		cf;
1667 
1668 	/* Completion thread context */
1669 	ddi_taskq_t		*completion_taskq;
1670 	ql_head_t		comp_q;
1671 	kmutex_t		comp_q_mutex;
1672 	kcondvar_t		cv_comp_thread;
1673 	uint8_t			comp_thds_active;
1674 	uint8_t			comp_thds_awake;
1675 	uint8_t			completion_thds;
1676 
1677 	/* Interrupt context. */
1678 	ddi_iblock_cookie_t	iblock_cookie;
1679 	ddi_intr_handle_t	*htable;
1680 	uint32_t		hsize;
1681 	int32_t			intr_cnt;
1682 	void			*intr_pri;
1683 	int32_t			intr_cap;
1684 	uint32_t		iflags;
1685 	volatile uint8_t	intr_claimed;
1686 	uint8_t			mq_msix_vectors;
1687 	uint8_t			interrupt_count;
1688 
1689 	/* Outstanding ISP commands. */
1690 	ql_head_t		pending_cmds;
1691 	ql_srb_t		**outstanding_cmds;
1692 	uint16_t		osc_index;
1693 	uint16_t		osc_max_cnt;
1694 
1695 	/* ISP request queue context. */
1696 	kmutex_t		req_ring_mutex;
1697 	ql_request_q_t		*req_q[2];
1698 
1699 	/* ISP response queue context. */
1700 	ql_response_q_t		**rsp_queues;
1701 	uint32_t		rsp_queues_size;
1702 	uint8_t			rsp_queues_cnt;
1703 	uint8_t			rsp_q_number;
1704 	uint8_t			io_min_rsp_q_number;
1705 
1706 	/* IP receive buffer queue context. */
1707 	ql_tgt_t		*rcv_dev_q;
1708 	dma_mem_t		rcv_ring;
1709 	struct rcvbuf		*rcvbuf_ring_ptr;
1710 	uint16_t		rcvbuf_ring_index;
1711 
1712 	/* Mailbox context. */
1713 	kmutex_t		mbx_mutex;
1714 	struct mbx_cmd		*mcp;
1715 	kcondvar_t		cv_mbx_wait;
1716 	kcondvar_t		cv_mbx_intr;
1717 	volatile uint8_t	mailbox_flags;
1718 
1719 	/* Unsolicited buffer data. */
1720 	uint16_t		ub_outcnt;
1721 	uint8_t			ub_seq_id;
1722 	uint8_t			ub_command_count;
1723 	uint8_t			ub_notify_count;
1724 	uint32_t		ub_allocated;
1725 	kmutex_t		ub_mutex;
1726 	kcondvar_t		cv_ub;
1727 	fc_unsol_buf_t		**ub_array;
1728 
1729 	/* Head of device queue list. */
1730 	ql_head_t		*dev;
1731 
1732 	/* Kernel statistics. */
1733 	kstat_t			*k_stats;
1734 	ql_adapter_stat_t	*adapter_stats;
1735 
1736 	/* PCI context */
1737 	ddi_acc_handle_t	pci_handle;	/* config space */
1738 	ddi_acc_handle_t	dev_handle;
1739 	caddr_t			iobase;
1740 	ddi_acc_handle_t	iomap_dev_handle;
1741 	caddr_t			iomap_iobase;
1742 	ddi_acc_handle_t	mbar_dev_handle;
1743 	caddr_t			mbar;
1744 	uint32_t		mbar_size;
1745 	uint32_t		mbar_queue_offset;
1746 	uint16_t		device_id;
1747 	uint16_t		subsys_id;
1748 	uint16_t		subven_id;
1749 	uint16_t		ven_id;
1750 	uint16_t		pci_max_read_req;
1751 	uint8_t			rev_id;
1752 	uint8_t			pci_function_number;
1753 
1754 	/* Solaris adapter configuration data */
1755 	dev_info_t		*dip;
1756 	fc_fca_tran_t		*tran;
1757 	uint32_t		instance;
1758 	int8_t			*devpath;
1759 	uint32_t		fru_hba_index;
1760 	uint32_t		fru_port_index;
1761 	uint8_t			adapInfo[18];
1762 
1763 	/* Adapter context */
1764 	la_els_logi_t		loginparams;
1765 	fc_fca_bind_info_t	bind_info;
1766 	ddi_modhandle_t		fw_module;
1767 	uint32_t		fw_major_version;
1768 	uint32_t		fw_minor_version;
1769 	uint32_t		fw_subminor_version;
1770 	uint32_t		fw_attributes;
1771 	uint32_t		fw_ext_attributes;
1772 	uint32_t		fw_ext_memory_end;
1773 	uint32_t		fw_ext_memory_size;
1774 	uint32_t		fw_shared_ram_start;
1775 	uint32_t		fw_shared_ram_end;
1776 	uint32_t		fw_ddr_ram_start;
1777 	uint32_t		fw_ddr_ram_end;
1778 	uint32_t		parity_pause_errors;
1779 	boolean_t		log_parity_pause;
1780 	uint32_t		fw_class;
1781 	uint16_t		fw_state[7];
1782 	uint16_t		rom_status;
1783 	ql_ledstate_t		ledstate;
1784 	uint16_t		parity_hccr_err;
1785 	uint32_t		parity_stat_err;
1786 	reg_off_t		*reg_off;
1787 	caddr_t			risc_code;
1788 	uint32_t		risc_code_size;
1789 	ql_fw_code_t		risc_fw[MAX_RISC_CODE_SEGMENTS];
1790 	uint32_t		risc_dump_size;
1791 	void			(*fcp_cmd)(struct ql_adapter_state *,
1792 				ql_request_q_t *, ql_srb_t *, void *);
1793 	void			(*ip_cmd)(struct ql_adapter_state *,
1794 				ql_request_q_t *, ql_srb_t *, void *);
1795 	void			(*ms_cmd)(struct ql_adapter_state *,
1796 				ql_request_q_t *, ql_srb_t *, void *);
1797 	void			(*els_cmd)(struct ql_adapter_state *,
1798 				ql_request_q_t *, ql_srb_t *, void *);
1799 	uint8_t			cmd_segs;
1800 	uint8_t			cmd_cont_segs;
1801 
1802 	/* NVRAM configuration data */
1803 	uint64_t		cfg_flags;
1804 	ql_comb_init_cb_t	init_ctrl_blk;
1805 	ql_comb_ip_init_cb_t	ip_init_ctrl_blk;
1806 	uint32_t		fw_transfer_size;
1807 	uint16_t		adapter_features;
1808 	uint16_t		execution_throttle;
1809 	uint16_t		port_down_retry_count;
1810 	uint16_t		serdes_param[4];
1811 	uint16_t		maximum_luns_per_target;
1812 	uint8_t			port_down_retry_delay;
1813 	uint8_t			qfull_retry_count;
1814 	uint8_t			qfull_retry_delay;
1815 	uint8_t			loop_reset_delay;
1816 
1817 	/* Power management context. */
1818 	kmutex_t		pm_mutex;
1819 	uint32_t		pm_busy;
1820 	uint8_t			power_level;
1821 	uint8_t			pm_capable;
1822 	uint8_t			config_saved;
1823 	uint8_t			lip_on_panic;
1824 
1825 	/* sbus card data */
1826 	caddr_t			sbus_fpga_iobase;
1827 	ddi_acc_handle_t	sbus_fpga_dev_handle;
1828 	ddi_acc_handle_t	sbus_config_handle;
1829 	caddr_t			sbus_config_base;
1830 
1831 	/* XIOCTL context pointer. */
1832 	struct ql_xioctl	*xioctl;
1833 
1834 	struct ql_fcache	*fcache;
1835 	int8_t			*vcache;
1836 	nvram_cache_desc_t	*nvram_cache;
1837 
1838 	/* f/w dump mutex */
1839 	uint32_t		ql_dump_size;
1840 	uint32_t		ql_dump_state;
1841 	void			*ql_dump_ptr;
1842 	kmutex_t		dump_mutex;
1843 
1844 	uint8_t			fwwait;
1845 
1846 	dma_mem_t		fwexttracebuf;		/* extended trace  */
1847 	dma_mem_t		fwfcetracebuf;		/* event trace */
1848 	ql_mbx_data_t		fw_fce_trace_enable;
1849 	uint32_t		fwfcetraceopt;
1850 	uint32_t		flash_errlog_start;	/* 32bit word addr */
1851 	uint32_t		flash_errlog_ptr;	/* 32bit word addr */
1852 	uint8_t			send_plogi_timer;
1853 
1854 	/* Plogi retry parameters */
1855 	plogi_params_desc_t	*plogi_params;
1856 
1857 	/* Virtual port context. */
1858 	fca_port_attrs_t	*pi_attrs;
1859 	struct ql_adapter_state	*pha;
1860 	struct ql_adapter_state *vp_next;
1861 	uint8_t			vp_index;
1862 	uint8_t			max_vports;
1863 
1864 	uint16_t		free_loop_id;
1865 
1866 	/* Tempoary N_Port information */
1867 	struct ql_n_port_info	*n_port;
1868 
1869 	ql_trace_desc_t		*ql_trace_desc;
1870 
1871 	uint32_t		flash_data_addr;
1872 	uint32_t		flash_fw_addr;
1873 	uint32_t		flash_golden_fw_addr;
1874 	uint32_t		boot_code_addr;
1875 	uint32_t		flash_vpd_addr;
1876 	uint32_t		flash_nvram_addr;
1877 	uint32_t		flash_desc_addr;
1878 	uint32_t		mpi_capability_list;
1879 	uint8_t			phy_fw_major_version;
1880 	uint8_t			phy_fw_minor_version;
1881 	uint8_t			phy_fw_subminor_version;
1882 	uint8_t			mpi_fw_major_version;
1883 	uint8_t			mpi_fw_minor_version;
1884 	uint8_t			mpi_fw_subminor_version;
1885 
1886 	uint16_t		idc_mb[8];
1887 	uint8_t			idc_restart_timer;
1888 
1889 	/* VLAN ID and MAC address */
1890 	uint8_t			fcoe_vnport_mac[6];
1891 	uint16_t		fabric_params;
1892 	uint16_t		fcoe_vlan_id;
1893 	uint16_t		fcoe_fcf_idx;
1894 
1895 	/* NetXen context */
1896 	ddi_acc_handle_t	db_dev_handle;
1897 	caddr_t			db_iobase;
1898 	caddr_t			nx_pcibase;	/* BAR0 base I/O address */
1899 	uint32_t		qdr_sn_window;
1900 	uint32_t		*nx_req_in;
1901 	caddr_t			db_read;
1902 	uint32_t		pci_bus_addr;
1903 	struct legacy_intr_set	nx_legacy_intr;
1904 	uint32_t		bootloader_size;
1905 	uint32_t		bootloader_addr;
1906 	uint32_t		flash_fw_size;
1907 	uint32_t		dev_state;
1908 	uint32_t		fw_heartbeat_counter;
1909 	dma_mem_t		dmp_template;
1910 	uint32_t		md_capture_mask;
1911 	uint32_t		md_capture_size;
1912 	uint16_t		iidma_rate;
1913 	uint8_t			function_number;
1914 	uint8_t			timeout_cnt;
1915 	uint8_t			seconds_since_last_heartbeat;
1916 
1917 	/* default dma attributes */
1918 	ddi_dma_attr_t		bit32_io_dma_attr;
1919 	ddi_dma_attr_t		bit64_io_dma_attr;
1920 
1921 	ddi_dma_attr_t		io_dma_attr;
1922 	ddi_dma_attr_t		fcsm_cmd_dma_attr;
1923 	ddi_dma_attr_t		fcsm_rsp_dma_attr;
1924 	ddi_dma_attr_t		fcip_cmd_dma_attr;
1925 	ddi_dma_attr_t		fcip_rsp_dma_attr;
1926 	ddi_dma_attr_t		fcp_cmd_dma_attr;
1927 	ddi_dma_attr_t		fcp_rsp_dma_attr;
1928 	ddi_dma_attr_t		fcp_data_dma_attr;
1929 
1930 	int			fm_capabilities;
1931 	uint16_t		errlog[4];
1932 } ql_adapter_state_t;
1933 
1934 /*
1935  * adapter state flags
1936  */
1937 #define	FCA_BOUND			(uint64_t)BIT_0
1938 #define	QL_OPENED			(uint64_t)BIT_1
1939 #define	ONLINE				(uint64_t)BIT_2
1940 #define	INTERRUPTS_ENABLED		(uint64_t)BIT_3
1941 
1942 #define	ABORT_CMDS_LOOP_DOWN_TMO	(uint64_t)BIT_4
1943 #define	POINT_TO_POINT			(uint64_t)BIT_5
1944 #define	IP_ENABLED			(uint64_t)BIT_6
1945 #define	IP_INITIALIZED			(uint64_t)BIT_7
1946 
1947 #define	MENLO_LOGIN_OPERATIONAL		(uint64_t)BIT_8
1948 #define	ADAPTER_SUSPENDED		(uint64_t)BIT_9
1949 #define	FW_DUMP_NEEDED			(uint64_t)BIT_10
1950 #define	PARITY_ERROR			(uint64_t)BIT_11
1951 
1952 #define	FLASH_ERRLOG_MARKER		(uint64_t)BIT_12
1953 #define	VP_ENABLED			(uint64_t)BIT_13
1954 #define	FDISC_ENABLED			(uint64_t)BIT_14
1955 #define	MULTI_QUEUE			(uint64_t)BIT_15
1956 
1957 #define	MPI_RESET_NEEDED		(uint64_t)BIT_16
1958 #define	VP_ID_NOT_ACQUIRED		(uint64_t)BIT_17
1959 #define	IDC_STALL_NEEDED		(uint64_t)BIT_18
1960 #define	POLL_INTR			(uint64_t)BIT_19
1961 
1962 #define	IDC_RESTART_NEEDED		(uint64_t)BIT_20
1963 #define	IDC_ACK_NEEDED			(uint64_t)BIT_21
1964 #define	LOOPBACK_ACTIVE			(uint64_t)BIT_22
1965 #define	QUEUE_SHADOW_PTRS		(uint64_t)BIT_23
1966 
1967 #define	NO_INTR_HANDSHAKE		(uint64_t)BIT_24
1968 #define	COMP_THD_TERMINATE		(uint64_t)BIT_25
1969 #define	DISABLE_NIC_FW_DMP		(uint64_t)BIT_26
1970 #define	MULTI_CHIP_ADAPTER		(uint64_t)BIT_27
1971 
1972 /*
1973  * task daemon flags
1974  */
1975 #define	TASK_DAEMON_STOP_FLG		(uint64_t)BIT_0
1976 #define	TASK_DAEMON_SLEEPING_FLG	(uint64_t)BIT_1
1977 #define	TASK_DAEMON_ALIVE_FLG		(uint64_t)BIT_2
1978 #define	TASK_DAEMON_IDLE_CHK_FLG	(uint64_t)BIT_3
1979 
1980 #define	SUSPENDED_WAKEUP_FLG		(uint64_t)BIT_4
1981 #define	FC_STATE_CHANGE			(uint64_t)BIT_5
1982 #define	NEED_UNSOLICITED_BUFFERS	(uint64_t)BIT_6
1983 #define	MARKER_NEEDED			(uint64_t)BIT_7
1984 
1985 #define	MARKER_ACTIVE			(uint64_t)BIT_8
1986 #define	ISP_ABORT_NEEDED		(uint64_t)BIT_9
1987 #define	ABORT_ISP_ACTIVE		(uint64_t)BIT_10
1988 #define	LOOP_RESYNC_NEEDED		(uint64_t)BIT_11
1989 
1990 #define	LOOP_RESYNC_ACTIVE		(uint64_t)BIT_12
1991 #define	LOOP_DOWN			(uint64_t)BIT_13
1992 #define	DRIVER_STALL			(uint64_t)BIT_14
1993 #define	COMMAND_WAIT_NEEDED		(uint64_t)BIT_15
1994 
1995 #define	COMMAND_WAIT_ACTIVE		(uint64_t)BIT_16
1996 #define	STATE_ONLINE			(uint64_t)BIT_17
1997 #define	ABORT_QUEUES_NEEDED		(uint64_t)BIT_18
1998 #define	TASK_DAEMON_STALLED_FLG		(uint64_t)BIT_19
1999 
2000 #define	SEND_PLOGI			(uint64_t)BIT_20
2001 #define	FIRMWARE_UP			(uint64_t)BIT_21
2002 #define	IDC_POLL_NEEDED			(uint64_t)BIT_22
2003 #define	FIRMWARE_LOADED			(uint64_t)BIT_23
2004 
2005 #define	RSCN_UPDATE_NEEDED		(uint64_t)BIT_24
2006 #define	HANDLE_PORT_BYPASS_CHANGE	(uint64_t)BIT_25
2007 #define	PORT_RETRY_NEEDED		(uint64_t)BIT_26
2008 #define	TASK_DAEMON_POWERING_DOWN	(uint64_t)BIT_27
2009 
2010 #define	TD_IIDMA_NEEDED			(uint64_t)BIT_28
2011 #define	WATCHDOG_NEEDED			(uint64_t)BIT_29
2012 #define	LED_BLINK			(uint64_t)BIT_30
2013 
2014 #define	DTF_EL_MSG_SKIP_FLGS	(IDC_POLL_NEEDED | WATCHDOG_NEEDED | \
2015     TASK_DAEMON_IDLE_CHK_FLG | LED_BLINK)
2016 /*
2017  * Mailbox flags
2018  */
2019 #define	MBX_WANT_FLG				BIT_0
2020 #define	MBX_BUSY_FLG				BIT_1
2021 #define	MBX_INTERRUPT				BIT_2
2022 #define	MBX_ABORT				BIT_3
2023 
2024 /*
2025  * Configuration flags
2026  */
2027 #define	CFG_CTRL_27XX				(uint64_t)BIT_0
2028 #define	CFG_ENABLE_64BIT_ADDRESSING		(uint64_t)BIT_1
2029 #define	CFG_ENABLE_LIP_RESET			(uint64_t)BIT_2
2030 #define	CFG_ENABLE_FULL_LIP_LOGIN		(uint64_t)BIT_3
2031 
2032 #define	CFG_ENABLE_TARGET_RESET			(uint64_t)BIT_4
2033 #define	CFG_ENABLE_LINK_DOWN_REPORTING		(uint64_t)BIT_5
2034 #define	CFG_LR_SUPPORT				(uint64_t)BIT_6
2035 #define	CFG_ENABLE_FCP_2_SUPPORT		(uint64_t)BIT_7
2036 
2037 #define	CFG_CTRL_83XX				(uint64_t)BIT_8
2038 #define	CFG_SBUS_CARD				(uint64_t)BIT_9
2039 #define	CFG_CTRL_23XX				(uint64_t)BIT_10
2040 #define	CFG_CTRL_63XX				(uint64_t)BIT_11
2041 
2042 #define	CFG_CTRL_22XX				(uint64_t)BIT_12
2043 #define	CFG_CTRL_24XX				(uint64_t)BIT_13
2044 #define	CFG_CTRL_25XX				(uint64_t)BIT_14
2045 #define	CFG_ENABLE_EXTENDED_LOGGING		(uint64_t)BIT_15
2046 
2047 #define	CFG_DISABLE_RISC_CODE_LOAD		(uint64_t)BIT_16
2048 #define	CFG_SET_CACHE_LINE_SIZE_1		(uint64_t)BIT_17
2049 #define	CFG_CTRL_MENLO				(uint64_t)BIT_18
2050 #define	CFG_EXT_FW_INTERFACE			(uint64_t)BIT_19
2051 
2052 #define	CFG_LOAD_FLASH_FW			(uint64_t)BIT_20
2053 #define	CFG_DUMP_MAILBOX_TIMEOUT		(uint64_t)BIT_21
2054 #define	CFG_DUMP_ISP_SYSTEM_ERROR		(uint64_t)BIT_22
2055 #define	CFG_DUMP_DRIVER_COMMAND_TIMEOUT		(uint64_t)BIT_23
2056 
2057 #define	CFG_DUMP_LOOP_OFFLINE_TIMEOUT		(uint64_t)BIT_24
2058 #define	CFG_ENABLE_FWEXTTRACE			(uint64_t)BIT_25
2059 #define	CFG_ENABLE_FWFCETRACE			(uint64_t)BIT_26
2060 #define	CFG_CTRL_80XX				(uint64_t)BIT_27
2061 
2062 #define	CFG_CTRL_81XX				(uint64_t)BIT_28
2063 #define	CFG_CTRL_82XX				(uint64_t)BIT_29
2064 #define	CFG_FAST_TIMEOUT			(uint64_t)BIT_30
2065 
2066 #define	CFG_CTRL_2363		(CFG_CTRL_23XX | CFG_CTRL_63XX)
2067 #define	CFG_CTRL_2425		(CFG_CTRL_24XX | CFG_CTRL_25XX)
2068 #define	CFG_CTRL_2783		(CFG_CTRL_27XX | CFG_CTRL_83XX)
2069 #define	CFG_CTRL_8081		(CFG_CTRL_80XX | CFG_CTRL_81XX)
2070 #define	CFG_CTRL_278083		(CFG_CTRL_80XX | CFG_CTRL_2783)
2071 #define	CFG_CTRL_27808183	(CFG_CTRL_8081 | CFG_CTRL_2783)
2072 #define	CFG_CTRL_2527808183	(CFG_CTRL_25XX | CFG_CTRL_27808183)
2073 #define	CFG_CTRL_252780818283	(CFG_CTRL_82XX | CFG_CTRL_2527808183)
2074 
2075 #define	CFG_ISP_FW_TYPE_1	(CFG_CTRL_22XX | CFG_CTRL_2363)
2076 #define	CFG_ISP_FW_TYPE_2	(CFG_CTRL_24XX | CFG_CTRL_252780818283)
2077 #define	CFG_FCIP_TYPE_1		(CFG_CTRL_22XX | CFG_CTRL_23XX)
2078 #define	CFG_FCIP_SUPPORT	(CFG_FCIP_TYPE_1 | CFG_CTRL_24XX)
2079 #define	CFG_FCOE_SUPPORT	(CFG_CTRL_82XX | CFG_CTRL_8081)
2080 #define	CFG_N2N_SUPPORT		(CFG_CTRL_2425 | CFG_CTRL_2783)
2081 #define	CFG_FC_TYPE_1		(CFG_CTRL_22XX | CFG_CTRL_2363)
2082 #define	CFG_FC_TYPE_2		(CFG_CTRL_2425 | CFG_CTRL_2783)
2083 #define	CFG_FC_TYPE		(CFG_FC_TYPE_1 | CFG_FC_TYPE_2)
2084 #define	CFG_NO_INTR_HSHAKE_SUP	(CFG_CTRL_27808183)
2085 #define	CFG_MWB_4096_SUPPORT	(CFG_CTRL_2425 | CFG_CTRL_81XX)
2086 #define	CFG_IIDMA_SUPPORT	(CFG_CTRL_8081 | CFG_FC_TYPE_2)
2087 #define	CFG_FLASH_ACC_SUPPORT	(CFG_CTRL_27808183)
2088 #define	CFG_FLASH_DMA_SUPPORT	(CFG_CTRL_2527808183)
2089 #define	CFG_LOOP_POINT_SUPPORT	(CFG_CTRL_8081)
2090 #define	CFG_LB_ECHO_SUPPORT	(CFG_CTRL_2363 | CFG_ISP_FW_TYPE_2)
2091 #define	CFG_SET_LEDS_SUPPORT	(CFG_CTRL_2363 | CFG_ISP_FW_TYPE_2)
2092 #define	CFG_SERDES_SUPPORT	(CFG_CTRL_2783)
2093 #define	CFG_BBCR_SUPPORT	(CFG_CTRL_2783)
2094 #define	CFG_MSI_SUPPORT		(CFG_CTRL_2425 | CFG_CTRL_81XX | CFG_CTRL_82XX)
2095 
2096 
2097 #define	CFG_IST(ha, cfgflags)	(ha->cfg_flags & (cfgflags))
2098 
2099 /*
2100  * Interrupt configuration flags
2101  */
2102 #define	IFLG_INTR_LEGACY			BIT_0
2103 #define	IFLG_INTR_FIXED				BIT_1
2104 #define	IFLG_INTR_MSI				BIT_2
2105 #define	IFLG_INTR_MSIX				BIT_3
2106 
2107 #define	IFLG_INTR_AIF	(IFLG_INTR_MSI | IFLG_INTR_FIXED | IFLG_INTR_MSIX)
2108 
2109 /*
2110  * Macros to help code, maintain, etc.
2111  */
2112 #define	LSB(x)		(uint8_t)(x)
2113 #define	MSB(x)		(uint8_t)((uint16_t)(x) >> 8)
2114 #define	MSW(x)		(uint16_t)((uint32_t)(x) >> 16)
2115 #define	LSW(x)		(uint16_t)(x)
2116 #define	LSD(x)		(uint32_t)(x)
2117 #define	MSD(x)		(uint32_t)((uint64_t)(x) >> 32)
2118 
2119 #define	LONG_TO_LLONG(lsl, msl) (uint64_t)((uint64_t)(msl) << 32 | \
2120 	(uint32_t)(lsl))
2121 #define	SHORT_TO_LONG(lsw, msw) (uint32_t)((uint32_t)msw << 16 | (uint16_t)lsw)
2122 #define	CHAR_TO_SHORT(lsb, msb) (uint16_t)((uint16_t)msb << 8 | (uint8_t)lsb)
2123 #define	CHAR_TO_LONG(lsb, b1, b2, msb) \
2124 	(uint32_t)(SHORT_TO_LONG(CHAR_TO_SHORT(lsb, b1), \
2125 	CHAR_TO_SHORT(b2, msb)))
2126 
2127 /* Little endian machine correction defines. */
2128 #ifdef _LITTLE_ENDIAN
2129 #define	LITTLE_ENDIAN_16(x)
2130 #define	LITTLE_ENDIAN_24(x)
2131 #define	LITTLE_ENDIAN_32(x)
2132 #define	LITTLE_ENDIAN_64(x)
2133 #define	LITTLE_ENDIAN(bp, bytes)
2134 #define	BIG_ENDIAN_16(x)	ql_chg_endian((uint8_t *)x, 2)
2135 #define	BIG_ENDIAN_24(x)	ql_chg_endian((uint8_t *)x, 3)
2136 #define	BIG_ENDIAN_32(x)	ql_chg_endian((uint8_t *)x, 4)
2137 #define	BIG_ENDIAN_64(x)	ql_chg_endian((uint8_t *)x, 8)
2138 #define	BIG_ENDIAN(bp, bytes)	ql_chg_endian((uint8_t *)bp, bytes)
2139 #endif /* _LITTLE_ENDIAN */
2140 
2141 /* Big endian machine correction defines. */
2142 #ifdef _BIG_ENDIAN
2143 #define	LITTLE_ENDIAN_16(x)		ql_chg_endian((uint8_t *)x, 2)
2144 #define	LITTLE_ENDIAN_24(x)		ql_chg_endian((uint8_t *)x, 3)
2145 #define	LITTLE_ENDIAN_32(x)		ql_chg_endian((uint8_t *)x, 4)
2146 #define	LITTLE_ENDIAN_64(x)		ql_chg_endian((uint8_t *)x, 8)
2147 #define	LITTLE_ENDIAN(bp, bytes)	ql_chg_endian((uint8_t *)bp, bytes)
2148 #define	BIG_ENDIAN_16(x)
2149 #define	BIG_ENDIAN_24(x)
2150 #define	BIG_ENDIAN_32(x)
2151 #define	BIG_ENDIAN_64(x)
2152 #define	BIG_ENDIAN(bp, bytes)
2153 #endif /* _BIG_ENDIAN */
2154 
2155 #define	LOCAL_LOOP_ID(x)	(x <= LAST_LOCAL_LOOP_ID)
2156 
2157 #define	FABRIC_LOOP_ID(x)	(x == FL_PORT_LOOP_ID || \
2158     x == SIMPLE_NAME_SERVER_LOOP_ID)
2159 
2160 #define	SNS_LOOP_ID(x)		(x >= SNS_FIRST_LOOP_ID && \
2161     x <= SNS_LAST_LOOP_ID)
2162 
2163 #define	BROADCAST_LOOP_ID(x)	(x == IP_BROADCAST_LOOP_ID)
2164 
2165 #define	VALID_LOOP_ID(x)	(LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x) || \
2166     FABRIC_LOOP_ID(x) || BROADCAST_LOOP_ID(x))
2167 
2168 #define	VALID_N_PORT_HDL(x)	(x <= LAST_N_PORT_HDL || \
2169 	(x >= SNS_24XX_HDL && x <= BROADCAST_24XX_HDL))
2170 
2171 #define	VALID_DEVICE_ID(ha, x)	(CFG_IST(ha, CFG_ISP_FW_TYPE_2) ? \
2172 	VALID_N_PORT_HDL(x) : VALID_LOOP_ID(x))
2173 
2174 #define	VALID_TARGET_ID(ha, x)	(CFG_IST(ha, CFG_ISP_FW_TYPE_2) ? \
2175 	(x <= LAST_N_PORT_HDL) : (LOCAL_LOOP_ID(x) || SNS_LOOP_ID(x)))
2176 
2177 #define	RESERVED_LOOP_ID(ha, x) (CFG_IST(ha, CFG_ISP_FW_TYPE_2) ? \
2178 	(x > LAST_N_PORT_HDL && x <= FL_PORT_24XX_HDL) : \
2179 	(x >= FL_PORT_LOOP_ID && x <= SIMPLE_NAME_SERVER_LOOP_ID))
2180 
2181 #define	QL_LOOP_TRANSITION	(MARKER_NEEDED | MARKER_ACTIVE | \
2182 				ISP_ABORT_NEEDED | ABORT_ISP_ACTIVE | \
2183 				LOOP_RESYNC_NEEDED | LOOP_RESYNC_ACTIVE | \
2184 				COMMAND_WAIT_NEEDED | COMMAND_WAIT_ACTIVE)
2185 
2186 #define	LOOP_RECONFIGURE(ha)	(ha->task_daemon_flags & (QL_LOOP_TRANSITION | \
2187 				DRIVER_STALL))
2188 
2189 #define	DRIVER_SUSPENDED(ha)	(ha->task_daemon_flags & (LOOP_DOWN | \
2190 				QL_LOOP_TRANSITION | DRIVER_STALL))
2191 
2192 #define	LOOP_NOT_READY(ha)	(ha->task_daemon_flags & (QL_LOOP_TRANSITION | \
2193 				LOOP_DOWN))
2194 
2195 #define	LOOP_READY(ha)		(LOOP_NOT_READY(ha) == 0)
2196 
2197 #define	QL_TASK_PENDING(ha)	( \
2198     ha->task_daemon_flags & (QL_LOOP_TRANSITION | ABORT_QUEUES_NEEDED | \
2199     PORT_RETRY_NEEDED) || ha->unsol_callback_queue.first != NULL)
2200 
2201 #define	QL_DAEMON_NOT_ACTIVE(ha)	( \
2202 	!(ha->task_daemon_flags & TASK_DAEMON_ALIVE_FLG) || \
2203 	ha->task_daemon_flags & (TASK_DAEMON_SLEEPING_FLG | \
2204 	TASK_DAEMON_STOP_FLG))
2205 
2206 #define	QL_ABORTED_SRB(ha)	((ql_srb_t *)ha)
2207 
2208 #define	INTERRUPT_PENDING(ha)	(CFG_IST(ha, CFG_CTRL_82XX) ? \
2209 				RD32_IO_REG(ha, nx_risc_int) & NX_RISC_INT : \
2210 				RD16_IO_REG(ha, istatus) & RISC_INT)
2211 /*
2212  * Locking Macro Definitions
2213  */
2214 #define	GLOBAL_STATE_LOCK()		mutex_enter(&ql_global_mutex)
2215 #define	GLOBAL_STATE_UNLOCK()		mutex_exit(&ql_global_mutex)
2216 
2217 #define	GLOBAL_TIMER_LOCK()		mutex_enter(&ql_global_timer_mutex)
2218 #define	GLOBAL_TIMER_UNLOCK()		mutex_exit(&ql_global_timer_mutex)
2219 
2220 #define	TRY_DEVICE_QUEUE_LOCK(q)	mutex_tryenter(&q->mutex)
2221 #define	DEVICE_QUEUE_LOCK(q)		mutex_enter(&q->mutex)
2222 #define	DEVICE_QUEUE_UNLOCK(q)		mutex_exit(&q->mutex)
2223 
2224 #define	TRY_MBX_REGISTER_LOCK(ha)	mutex_tryenter(&ha->pha->mbx_mutex)
2225 #define	MBX_REGISTER_LOCK_OWNER(ha)	mutex_owner(&ha->pha->mbx_mutex)
2226 #define	MBX_REGISTER_LOCK(ha)		mutex_enter(&ha->pha->mbx_mutex)
2227 #define	MBX_REGISTER_UNLOCK(ha)		mutex_exit(&ha->pha->mbx_mutex)
2228 
2229 #define	INTR_LOCK(ha)			ql_intr_lock(ha->pha)
2230 #define	INTR_UNLOCK(ha)			ql_intr_unlock(ha->pha)
2231 
2232 #define	INDX_INTR_LOCK(ha, i)	mutex_enter(&ha->pha->rsp_queues[i]->intr_mutex)
2233 #define	INDX_INTR_UNLOCK(ha, i)	mutex_exit(&ha->pha->rsp_queues[i]->intr_mutex)
2234 
2235 #define	TASK_DAEMON_LOCK(ha)		mutex_enter(&ha->pha->task_daemon_mutex)
2236 #define	TASK_DAEMON_UNLOCK(ha)		mutex_exit(&ha->pha->task_daemon_mutex)
2237 
2238 #define	REQUEST_RING_LOCK(ha)		mutex_enter(&ha->pha->req_ring_mutex)
2239 #define	REQUEST_RING_UNLOCK(ha)		mutex_exit(&ha->pha->req_ring_mutex)
2240 
2241 #define	COMP_Q_LOCK(ha)			mutex_enter(&ha->pha->comp_q_mutex)
2242 #define	COMP_Q_UNLOCK(ha)		mutex_exit(&ha->pha->comp_q_mutex)
2243 
2244 #define	ADAPTER_STATE_LOCK(ha)		mutex_enter(&ha->pha->mutex)
2245 #define	ADAPTER_STATE_UNLOCK(ha)	mutex_exit(&ha->pha->mutex)
2246 
2247 #define	QL_DUMP_LOCK(ha)		mutex_enter(&ha->pha->dump_mutex)
2248 #define	QL_DUMP_UNLOCK(ha)		mutex_exit(&ha->pha->dump_mutex)
2249 
2250 #define	QL_PM_LOCK(ha)			mutex_enter(&ha->pha->pm_mutex)
2251 #define	QL_PM_UNLOCK(ha)		mutex_exit(&ha->pha->pm_mutex)
2252 
2253 #define	QL_UB_LOCK(ha)			mutex_enter(&ha->pha->ub_mutex)
2254 #define	QL_UB_UNLOCK(ha)		mutex_exit(&ha->pha->ub_mutex)
2255 
2256 #define	GLOBAL_HW_LOCK()		mutex_enter(&ql_global_hw_mutex)
2257 #define	GLOBAL_HW_UNLOCK()		mutex_exit(&ql_global_hw_mutex)
2258 
2259 /*
2260  * PCI power management control/status register location
2261  */
2262 #define	QL_PM_CS_REG			0x48
2263 
2264 /*
2265  * ql component
2266  */
2267 #define	QL_POWER_COMPONENT		0
2268 
2269 typedef struct ql_config_space {
2270 	uint16_t	chs_command;
2271 	uint8_t		chs_cache_line_size;
2272 	uint8_t		chs_latency_timer;
2273 	uint8_t		chs_header_type;
2274 	uint8_t		chs_sec_latency_timer;
2275 	uint8_t		chs_bridge_control;
2276 	uint32_t	chs_base0;
2277 	uint32_t	chs_base1;
2278 	uint32_t	chs_base2;
2279 	uint32_t	chs_base3;
2280 	uint32_t	chs_base4;
2281 	uint32_t	chs_base5;
2282 } ql_config_space_t;
2283 
2284 #ifdef	USE_DDI_INTERFACES
2285 
2286 #define	QL_SAVE_CONFIG_REGS(dip)		pci_save_config_regs(dip)
2287 #define	QL_RESTORE_CONFIG_REGS(dip)		pci_restore_config_regs(dip)
2288 
2289 #else /* USE_DDI_INTERFACES */
2290 
2291 #define	QL_SAVE_CONFIG_REGS(dip)		ql_save_config_regs(dip)
2292 #define	QL_RESTORE_CONFIG_REGS(dip)		ql_restore_config_regs(dip)
2293 
2294 #endif /* USE_DDI_INTERFACES */
2295 
2296 /*
2297  * QL local function return status codes
2298  */
2299 #define	QL_SUCCESS			0x4000
2300 #define	QL_INVALID_COMMAND		0x4001
2301 #define	QL_INTERFACE_ERROR		0x4002
2302 #define	QL_TEST_FAILED			0x4003
2303 #define	QL_COMMAND_ERROR		0x4005
2304 #define	QL_PARAMETER_ERROR		0x4006
2305 #define	QL_PORT_ID_USED			0x4007
2306 #define	QL_LOOP_ID_USED			0x4008
2307 #define	QL_ALL_IDS_IN_USE		0x4009
2308 #define	QL_NOT_LOGGED_IN		0x400A
2309 #define	QL_LOOP_DOWN			0x400B
2310 #define	QL_LOOP_BACK_ERROR		0x400C
2311 #define	QL_CHECKSUM_ERROR		0x4010
2312 #define	QL_CONSUMED			0x4011
2313 
2314 #define	QL_FUNCTION_TIMEOUT		0x100
2315 #define	QL_FUNCTION_PARAMETER_ERROR	0x101
2316 #define	QL_FUNCTION_FAILED		0x102
2317 #define	QL_MEMORY_ALLOC_FAILED		0x103
2318 #define	QL_FABRIC_NOT_INITIALIZED	0x104
2319 #define	QL_LOCK_TIMEOUT			0x105
2320 #define	QL_ABORTED			0x106
2321 #define	QL_FUNCTION_SUSPENDED		0x107
2322 #define	QL_END_OF_DATA			0x108
2323 #define	QL_IP_UNSUPPORTED		0x109
2324 #define	QL_PM_ERROR			0x10a
2325 #define	QL_DATA_EXISTS			0x10b
2326 #define	QL_NOT_SUPPORTED		0x10c
2327 #define	QL_MEMORY_FULL			0x10d
2328 #define	QL_FW_NOT_SUPPORTED		0x10e
2329 #define	QL_FWMODLOAD_FAILED		0x10f
2330 #define	QL_FWSYM_NOT_FOUND		0x110
2331 #define	QL_LOGIN_NOT_SUPPORTED		0x111
2332 
2333 /*
2334  * SBus card FPGA register offsets.
2335  */
2336 #define	FPGA_CONF		0x100
2337 #define	FPGA_EEPROM_LOADDR	0x102
2338 #define	FPGA_EEPROM_HIADDR	0x104
2339 #define	FPGA_EEPROM_DATA	0x106
2340 #define	FPGA_REVISION		0x108
2341 
2342 #define	SBUS_FLASH_WRITE_ENABLE	0x0080
2343 #define	QL_SBUS_FCODE_SIZE	0x30000
2344 #define	QL_FCODE_OFFSET		0
2345 #define	QL_FPGA_SIZE		0x40000
2346 #define	QL_FPGA_OFFSET		0x40000
2347 
2348 #define	READ_PORT_ID(addr)	((uint32_t)((((uint32_t)((addr)[0])) << 16) | \
2349 					(((uint32_t)((addr)[1])) << 8) | \
2350 					(((uint32_t)((addr)[2])))))
2351 #define	READ_PORT_NAME(addr) ((u_longlong_t)((((uint64_t)((addr)[0])) << 56) | \
2352 					(((uint64_t)((addr)[1])) << 48) | \
2353 					(((uint64_t)((addr)[2])) << 40) | \
2354 					(((uint64_t)((addr)[3])) << 32) | \
2355 					(((uint64_t)((addr)[4])) << 24) | \
2356 					(((uint64_t)((addr)[5])) << 16) | \
2357 					(((uint64_t)((addr)[6])) << 8) | \
2358 					(((uint64_t)((addr)[7])))))
2359 /*
2360  * Structure used to associate cmds with strings which describe them.
2361  */
2362 typedef struct cmd_table_entry {
2363 	uint16_t cmd;
2364 	char    *string;
2365 } cmd_table_t;
2366 
2367 /*
2368  * ELS command table initializer
2369  */
2370 #define	ELS_CMD_TABLE()					\
2371 {							\
2372 	{LA_ELS_RJT, "LA_ELS_RJT"},			\
2373 	{LA_ELS_ACC, "LA_ELS_ACC"},			\
2374 	{LA_ELS_PLOGI, "LA_ELS_PLOGI"},			\
2375 	{LA_ELS_PDISC, "LA_ELS_PDISC"},			\
2376 	{LA_ELS_FLOGI, "LA_ELS_FLOGI"},			\
2377 	{LA_ELS_FDISC, "LA_ELS_FDISC"},			\
2378 	{LA_ELS_LOGO, "LA_ELS_LOGO"},			\
2379 	{LA_ELS_PRLI, "LA_ELS_PRLI"},			\
2380 	{LA_ELS_PRLO, "LA_ELS_PRLO"},			\
2381 	{LA_ELS_ADISC, "LA_ELS_ADISC"},			\
2382 	{LA_ELS_LINIT, "LA_ELS_LINIT"},			\
2383 	{LA_ELS_LPC, "LA_ELS_LPC"},			\
2384 	{LA_ELS_LSTS, "LA_ELS_LSTS"},			\
2385 	{LA_ELS_SCR, "LA_ELS_SCR"},			\
2386 	{LA_ELS_RSCN, "LA_ELS_RSCN"},			\
2387 	{LA_ELS_FARP_REQ, "LA_ELS_FARP_REQ"},		\
2388 	{LA_ELS_FARP_REPLY, "LA_ELS_FARP_REPLY"},	\
2389 	{LA_ELS_RLS, "LA_ELS_RLS"},			\
2390 	{LA_ELS_RNID, "LA_ELS_RNID"},			\
2391 	{0, NULL}					\
2392 }
2393 
2394 /*
2395  * ELS Passthru IOCB data segment descriptor.
2396  */
2397 typedef struct data_seg_desc {
2398 	uint32_t addr[2];
2399 	uint32_t length;
2400 } data_seg_desc_t;
2401 
2402 /*
2403  * ELS descriptor used to abstract the hosts fibre channel packet
2404  * from the ISP ELS code.
2405  */
2406 typedef struct els_desc {
2407 	uint8_t			els;		/* the ELS command code */
2408 	ddi_acc_handle_t	els_handle;
2409 	uint16_t		n_port_handle;
2410 	port_id_t		d_id;
2411 	port_id_t		s_id;
2412 	uint16_t		control_flags;
2413 	uint32_t		cmd_byte_count;
2414 	uint32_t		rsp_byte_count;
2415 	data_seg_desc_t		tx_dsd;		/* FC frame payload */
2416 	data_seg_desc_t		rx_dsd;		/* ELS resp payload buffer */
2417 } els_descriptor_t;
2418 
2419 typedef struct prli_svc_pram_resp_page {
2420 	uint8_t		type_code;
2421 	uint8_t		type_code_ext;
2422 	uint16_t	prli_resp_flags;
2423 	uint32_t	orig_process_associator;
2424 	uint32_t	resp_process_associator;
2425 	uint32_t	common_parameters;
2426 } prli_svc_pram_resp_page_t;
2427 
2428 /*
2429  * PRLI accept Service Parameter Page Word 3
2430  */
2431 #define	PRLI_W3_WRITE_FCP_XFR_RDY_DISABLED	BIT_0
2432 #define	PRLI_W3_READ_FCP_XFR_RDY_DISABLED	BIT_1
2433 #define	PRLI_W3_OBSOLETE_BIT_2			BIT_2
2434 #define	PRLI_W3_OBSOLETE_BIT_3			BIT_3
2435 #define	PRLI_W3_TARGET_FUNCTION			BIT_4
2436 #define	PRLI_W3_INITIATOR_FUNCTION		BIT_5
2437 #define	PRLI_W3_DATA_OVERLAY_ALLOWED		BIT_6
2438 #define	PRLI_W3_CONFIRMED_COMP_ALLOWED		BIT_7
2439 #define	PRLI_W3_RETRY				BIT_8
2440 #define	PRLI_W3_TASK_RETRY_ID_REQUESTED		BIT_9
2441 
2442 typedef struct prli_acc_resp {
2443 	uint8_t				ls_code;
2444 	uint8_t				page_length;
2445 	uint16_t			payload_length;
2446 	struct prli_svc_pram_resp_page	svc_params;
2447 } prli_acc_resp_t;
2448 
2449 #define	EL_TRACE_BUF_SIZE		8192
2450 
2451 #define	QL_PORT_ID_MASK			0xffffff
2452 
2453 #define	QL_PLOGI_RETRY_CNT		(5)
2454 #define	QL_PLOGI_RETRY_DLY_USEC		(10 * MILLISEC)
2455 
2456 /*
2457  * Global Data in ql_api.c source file.
2458  */
2459 extern void		*ql_state;		/* for soft state routine */
2460 extern uint32_t		ql_os_release_level;
2461 extern ql_head_t	ql_hba;
2462 extern kmutex_t		ql_global_mutex;
2463 extern kmutex_t		ql_global_hw_mutex;
2464 extern kmutex_t		ql_global_el_mutex;
2465 extern uint8_t		ql_ip_fast_post_count;
2466 extern uint32_t		ql_ip_buffer_count;
2467 extern uint32_t		ql_ip_low_water;
2468 extern uint8_t		ql_alpa_to_index[];
2469 extern uint32_t		ql_gfru_hba_index;
2470 extern uint32_t		ql_enable_ets;
2471 extern uint16_t		ql_osc_wait_count;
2472 
2473 /*
2474  * Global Function Prototypes in ql_api.c source file.
2475  */
2476 void ql_chg_endian(uint8_t *, size_t);
2477 void ql_populate_hba_fru_details(ql_adapter_state_t *, fc_fca_port_info_t *);
2478 void ql_setup_fruinfo(ql_adapter_state_t *);
2479 uint16_t ql_pci_config_get16(ql_adapter_state_t *, off_t);
2480 uint32_t ql_pci_config_get32(ql_adapter_state_t *, off_t);
2481 void ql_pci_config_put8(ql_adapter_state_t *, off_t, uint8_t);
2482 void ql_pci_config_put16(ql_adapter_state_t *, off_t, uint16_t);
2483 void ql_delay(ql_adapter_state_t *, clock_t);
2484 void ql_awaken_task_daemon(ql_adapter_state_t *, ql_srb_t *, uint64_t,
2485     uint64_t);
2486 int ql_abort_device(ql_adapter_state_t *, ql_tgt_t *, int);
2487 int ql_binary_fw_dump(ql_adapter_state_t *, int);
2488 void ql_done(ql_link_t *, boolean_t);
2489 int ql_24xx_flash_id(ql_adapter_state_t *);
2490 int ql_24xx_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t, uint32_t);
2491 int ql_poll_flash(ql_adapter_state_t *, uint32_t, uint8_t);
2492 void ql_flash_disable(ql_adapter_state_t *);
2493 void ql_flash_enable(ql_adapter_state_t *);
2494 int ql_erase_flash(ql_adapter_state_t *, int);
2495 void ql_write_flash_byte(ql_adapter_state_t *, uint32_t, uint8_t);
2496 uint8_t ql_read_flash_byte(ql_adapter_state_t *, uint32_t);
2497 int ql_24xx_read_flash(ql_adapter_state_t *, uint32_t, uint32_t *);
2498 int ql_24xx_write_flash(ql_adapter_state_t *, uint32_t, uint32_t);
2499 fc_unsol_buf_t *ql_get_unsolicited_buffer(ql_adapter_state_t *, uint32_t);
2500 int ql_dump_firmware(ql_adapter_state_t *);
2501 size_t ql_ascii_fw_dump(ql_adapter_state_t *, caddr_t);
2502 void ql_add_link_b(ql_head_t *, ql_link_t *);
2503 void ql_add_link_t(ql_head_t *, ql_link_t *);
2504 void ql_remove_link(ql_head_t *, ql_link_t *);
2505 void ql_next(ql_adapter_state_t *, ql_lun_t *);
2506 void ql_send_logo(ql_adapter_state_t *, ql_tgt_t *, ql_head_t *);
2507 void ql_cthdr_endian(ddi_acc_handle_t, caddr_t, boolean_t);
2508 ql_tgt_t *ql_d_id_to_queue(ql_adapter_state_t *, port_id_t);
2509 ql_tgt_t *ql_loop_id_to_queue(ql_adapter_state_t *, uint16_t);
2510 void ql_cmd_wait(ql_adapter_state_t *);
2511 void ql_loop_online(ql_adapter_state_t *);
2512 ql_tgt_t *ql_dev_init(ql_adapter_state_t *, port_id_t, uint16_t);
2513 int ql_ub_frame_hdr(ql_adapter_state_t *, ql_tgt_t *, uint16_t, ql_head_t *);
2514 void ql_rcv_rscn_els(ql_adapter_state_t *, uint16_t *, ql_head_t *);
2515 int ql_stall_driver(ql_adapter_state_t *, uint32_t);
2516 void ql_restart_driver(ql_adapter_state_t *);
2517 int ql_load_flash(ql_adapter_state_t *, uint8_t *, uint32_t);
2518 int ql_get_dma_mem(ql_adapter_state_t *, dma_mem_t *, uint32_t,
2519     mem_alloc_type_t, mem_alignment_t);
2520 void ql_free_dma_resource(ql_adapter_state_t *, dma_mem_t *);
2521 int ql_alloc_phys(ql_adapter_state_t *, dma_mem_t *, int);
2522 void ql_free_phys(ql_adapter_state_t *, dma_mem_t *);
2523 void ql_24xx_protect_flash(ql_adapter_state_t *);
2524 uint8_t ql_pci_config_get8(ql_adapter_state_t *, off_t);
2525 void ql_pci_config_put32(ql_adapter_state_t *, off_t, uint32_t);
2526 int ql_24xx_unprotect_flash(ql_adapter_state_t *);
2527 char *els_cmd_text(int);
2528 char *mbx_cmd_text(int);
2529 char *cmd_text(cmd_table_t *, int);
2530 uint32_t ql_fwmodule_resolve(ql_adapter_state_t *);
2531 void ql_port_state(ql_adapter_state_t *, uint32_t, uint32_t);
2532 void ql_isp_els_handle_cmd_endian(ql_adapter_state_t *ha, ql_srb_t *srb);
2533 void ql_isp_els_handle_rsp_endian(ql_adapter_state_t *ha, ql_srb_t *srb);
2534 void ql_isp_els_handle_endian(ql_adapter_state_t *ha, uint8_t *ptr,
2535     uint8_t ls_code);
2536 void ql_el_trace_alloc(ql_adapter_state_t *);
2537 void ql_el_trace_dealloc(ql_adapter_state_t *);
2538 int ql_nvram_cache_desc_ctor(ql_adapter_state_t *);
2539 int ql_nvram_cache_desc_dtor(ql_adapter_state_t *);
2540 int ql_plogi_params_desc_ctor(ql_adapter_state_t *);
2541 int ql_plogi_params_desc_dtor(ql_adapter_state_t *);
2542 int ql_wwn_cmp(ql_adapter_state_t *, la_wwn_t *, la_wwn_t *);
2543 void ql_dev_free(ql_adapter_state_t *, ql_tgt_t *);
2544 void ql_restart_queues(ql_adapter_state_t *);
2545 void ql_abort_queues(ql_adapter_state_t *);
2546 void ql_requeue_pending_cmds(ql_adapter_state_t *, ql_tgt_t *);
2547 void ql_toggle_loop_state(ql_adapter_state_t *);
2548 void ql_els_24xx_iocb(ql_adapter_state_t *, ql_request_q_t *, ql_srb_t *,
2549     void *);
2550 int ql_get_cap_ofst(ql_adapter_state_t *, uint8_t);
2551 void ql_intr_lock(ql_adapter_state_t *);
2552 void ql_intr_unlock(ql_adapter_state_t *);
2553 void ql_io_comp(ql_srb_t *sp);
2554 uint64_t ql_get_lun_addr(ql_tgt_t *, uint16_t);
2555 int ql_2700_get_flash_dmp_template(ql_adapter_state_t *);
2556 int ql_2700_get_module_dmp_template(ql_adapter_state_t *);
2557 
2558 #ifdef	__cplusplus
2559 }
2560 #endif
2561 
2562 #endif /* _QL_API_H */
2563