xref: /illumos-gate/usr/src/uts/i86pc/sys/machcpuvar.h (revision 7c8c0b8227679b4684566e408ccc96d6ef7175e9)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 /*
26  * Copyright 2019 Joyent, Inc.
27  */
28 
29 #ifndef	_SYS_MACHCPUVAR_H
30 #define	_SYS_MACHCPUVAR_H
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 #include <sys/inttypes.h>
37 #include <sys/x_call.h>
38 #include <sys/tss.h>
39 #include <sys/segments.h>
40 #include <sys/rm_platter.h>
41 #include <sys/avintr.h>
42 #include <sys/pte.h>
43 #include <sys/stddef.h>
44 #include <sys/debug.h>
45 #include <sys/cpuvar.h>
46 #include <sys/smt_machcpu.h>
47 
48 #ifndef	_ASM
49 /*
50  * On a virtualized platform a virtual cpu may not be actually
51  * on a physical cpu, especially in situations where a configuration has
52  * more vcpus than pcpus.  This function tells us (if it's able) if the
53  * specified vcpu is currently running on a pcpu.  Note if it is not
54  * known or not able to determine, it will return the unknown state.
55  */
56 #define	VCPU_STATE_UNKNOWN	0
57 #define	VCPU_ON_PCPU		1
58 #define	VCPU_NOT_ON_PCPU	2
59 
60 extern int vcpu_on_pcpu(processorid_t);
61 
62 /*
63  * Machine specific fields of the cpu struct
64  * defined in common/sys/cpuvar.h.
65  *
66  * Note:  This is kinda kludgy but seems to be the best
67  * of our alternatives.
68  */
69 
70 struct cpuid_info;
71 struct cpu_ucode_info;
72 struct cmi_hdl;
73 
74 /*
75  * A note about the hypervisor affinity bits: a one bit in the affinity mask
76  * means the corresponding event channel is allowed to be serviced
77  * by this cpu.
78  */
79 struct xen_evt_data {
80 	ulong_t		pending_sel[PIL_MAX + 1]; /* event array selectors */
81 	ulong_t		pending_evts[PIL_MAX + 1][sizeof (ulong_t) * 8];
82 	ulong_t		evt_affinity[sizeof (ulong_t) * 8]; /* service on cpu */
83 };
84 
85 enum fast_syscall_state {
86 	FSS_DISABLED		= 0,
87 	FSS_ASYSC_ENABLED	= (1 << 0),
88 	FSS_SEP_ENABLED		= (1 << 1)
89 };
90 
91 struct kpti_frame {
92 	uint64_t	kf_lower_redzone;
93 
94 	/* Stashed value of %cr3 when we entered the trampoline. */
95 	greg_t		kf_tr_cr3;
96 
97 	/*
98 	 * We use %r13-r14 as scratch registers in the trampoline code,
99 	 * so stash those here "below" the rest of the stack so they can be
100 	 * pushed/popped if needed.
101 	 */
102 	greg_t		kf_r14;
103 	greg_t		kf_r13;
104 
105 	/*
106 	 * Part of this struct is used as the HW stack frame when taking an
107 	 * interrupt on the user page table. The CPU is going to push a bunch
108 	 * of regs onto the stack pointer set in the TSS/IDT (which we set to
109 	 * &kf_rsp here).
110 	 *
111 	 * This is only a temporary holding area for them (we'll move them over
112 	 * to the real interrupt stack once we've set %cr3).
113 	 *
114 	 * Note that these must be cleared during a process switch on this cpu.
115 	 */
116 	greg_t		kf_err;		/* Bottom of initial hw stack frame */
117 	greg_t		kf_rip;
118 	greg_t		kf_cs;
119 	greg_t		kf_rflags;
120 	greg_t		kf_rsp;
121 	greg_t		kf_ss;
122 
123 	greg_t		kf_tr_rsp;	/* Top of HW stack frame */
124 	/* We also write this with the %rsp value on tramp entry */
125 
126 	/* Written to 0x1 when this kpti_frame is in use. */
127 	uint64_t	kf_tr_flag;
128 
129 	uint64_t	kf_middle_redzone;
130 
131 	/*
132 	 * The things we need to write to %cr3 to change between page tables.
133 	 * These live "above" the HW stack.
134 	 */
135 	greg_t		kf_kernel_cr3;
136 	greg_t		kf_user_cr3;
137 	greg_t		kf_tr_ret_rsp;
138 
139 	uint64_t	kf_unused;		/* For 16-byte align */
140 
141 	uint64_t	kf_upper_redzone;
142 };
143 
144 /*
145  * This first value, MACHCPU_SIZE is the size of all the members in the cpu_t
146  * AND struct machcpu, before we get to the mcpu_pad and the kpti area.
147  * The KPTI is used to contain per-CPU data that is visible in both sets of
148  * page-tables, and hence must be page-aligned and page-sized. See
149  * hat_pcp_setup().
150  *
151  * There are CTASSERTs in os/intr.c that verify this all works out.
152  */
153 #define	MACHCPU_SIZE	(1568 + 696)
154 #define	MACHCPU_PAD	(MMU_PAGESIZE - MACHCPU_SIZE)
155 #define	MACHCPU_PAD2	(MMU_PAGESIZE - 16 - 3 * sizeof (struct kpti_frame))
156 
157 struct	machcpu {
158 	/*
159 	 * x_call fields - used for interprocessor cross calls
160 	 */
161 	struct xc_msg	*xc_msgbox;
162 	struct xc_msg	*xc_curmsg;
163 	struct xc_msg	*xc_free;
164 	xc_data_t	xc_data;
165 	uint32_t	xc_wait_cnt;
166 	volatile uint32_t xc_work_cnt;
167 
168 	int		mcpu_nodeid;		/* node-id */
169 	int		mcpu_pri;		/* CPU priority */
170 
171 	struct hat	*mcpu_current_hat; /* cpu's current hat */
172 
173 	struct hat_cpu_info	*mcpu_hat_info;
174 
175 	volatile ulong_t	mcpu_tlb_info;
176 
177 	/* i86 hardware table addresses that cannot be shared */
178 
179 	user_desc_t	*mcpu_gdt;	/* GDT */
180 	gate_desc_t	*mcpu_idt;	/* current IDT */
181 
182 	tss_t		*mcpu_tss;	/* TSS */
183 	void		*mcpu_ldt;
184 	size_t		mcpu_ldt_len;
185 
186 	kmutex_t	mcpu_ppaddr_mutex;
187 	caddr_t		mcpu_caddr1;	/* per cpu CADDR1 */
188 	caddr_t		mcpu_caddr2;	/* per cpu CADDR2 */
189 	uint64_t	mcpu_caddr1pte;
190 	uint64_t	mcpu_caddr2pte;
191 
192 	struct softint	mcpu_softinfo;
193 	uint64_t	pil_high_start[HIGH_LEVELS];
194 	uint64_t	intrstat[PIL_MAX + 1][2];
195 
196 	struct cpuid_info	 *mcpu_cpi;
197 
198 #if defined(__amd64)
199 	greg_t	mcpu_rtmp_rsp;		/* syscall: temporary %rsp stash */
200 	greg_t	mcpu_rtmp_r15;		/* syscall: temporary %r15 stash */
201 #endif
202 
203 	struct vcpu_info *mcpu_vcpu_info;
204 	uint64_t	mcpu_gdtpa;	/* hypervisor: GDT physical address */
205 
206 	uint16_t mcpu_intr_pending;	/* hypervisor: pending intrpt levels */
207 	uint16_t mcpu_ec_mbox;		/* hypervisor: evtchn_dev mailbox */
208 	struct xen_evt_data *mcpu_evt_pend; /* hypervisor: pending events */
209 
210 	volatile uint32_t *mcpu_mwait;	/* MONITOR/MWAIT buffer */
211 	void (*mcpu_idle_cpu)(void);	/* idle function */
212 	uint16_t mcpu_idle_type;	/* CPU next idle type */
213 	uint16_t max_cstates;		/* supported max cstates */
214 
215 	enum fast_syscall_state	mcpu_fast_syscall_state;
216 
217 	struct cpu_ucode_info	*mcpu_ucode_info;
218 
219 	void			*mcpu_pm_mach_state;
220 	struct cmi_hdl		*mcpu_cmi_hdl;
221 	void			*mcpu_mach_ctx_ptr;
222 
223 	/*
224 	 * A stamp that is unique per processor and changes
225 	 * whenever an interrupt happens. Userful for detecting
226 	 * if a section of code gets interrupted.
227 	 * The high order 16 bits will hold the cpu->cpu_id.
228 	 * The low order bits will be incremented on every interrupt.
229 	 */
230 	volatile uint32_t	mcpu_istamp;
231 
232 	cpu_smt_t		mcpu_smt;
233 
234 	char			mcpu_pad[MACHCPU_PAD];
235 
236 	/* This is the start of the page */
237 	char			mcpu_pad2[MACHCPU_PAD2];
238 	struct kpti_frame	mcpu_kpti;
239 	struct kpti_frame	mcpu_kpti_flt;
240 	struct kpti_frame	mcpu_kpti_dbg;
241 	char			mcpu_pad3[16];
242 };
243 
244 #define	NINTR_THREADS	(LOCK_LEVEL-1)	/* number of interrupt threads */
245 #define	MWAIT_HALTED	(1)		/* mcpu_mwait set when halting */
246 #define	MWAIT_RUNNING	(0)		/* mcpu_mwait set to wakeup */
247 #define	MWAIT_WAKEUP_IPI	(2)	/* need IPI to wakeup */
248 #define	MWAIT_WAKEUP(cpu)	(*((cpu)->cpu_m.mcpu_mwait) = MWAIT_RUNNING)
249 
250 #endif	/* _ASM */
251 
252 /* Please DON'T add any more of this namespace-poisoning sewage here */
253 
254 #define	cpu_nodeid cpu_m.mcpu_nodeid
255 #define	cpu_pri cpu_m.mcpu_pri
256 #define	cpu_current_hat cpu_m.mcpu_current_hat
257 #define	cpu_hat_info cpu_m.mcpu_hat_info
258 #define	cpu_ppaddr_mutex cpu_m.mcpu_ppaddr_mutex
259 #define	cpu_gdt cpu_m.mcpu_gdt
260 #define	cpu_idt cpu_m.mcpu_idt
261 #define	cpu_tss cpu_m.mcpu_tss
262 #define	cpu_caddr1 cpu_m.mcpu_caddr1
263 #define	cpu_caddr2 cpu_m.mcpu_caddr2
264 #define	cpu_softinfo cpu_m.mcpu_softinfo
265 #define	cpu_caddr1pte cpu_m.mcpu_caddr1pte
266 #define	cpu_caddr2pte cpu_m.mcpu_caddr2pte
267 
268 #ifdef	__cplusplus
269 }
270 #endif
271 
272 #endif	/* _SYS_MACHCPUVAR_H */
273