xref: /illumos-gate/usr/src/uts/common/io/igc/core/igc_hw.h (revision 6bbbd4428a21d3f4d1d329851dbc599121cb5d31)
1 /*-
2  * Copyright 2021 Intel Corp
3  * Copyright 2021 Rubicon Communications, LLC (Netgate)
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef _IGC_HW_H_
8 #define _IGC_HW_H_
9 
10 #include "igc_osdep.h"
11 #include "igc_regs.h"
12 #include "igc_defines.h"
13 
14 struct igc_hw;
15 
16 #define IGC_DEV_ID_I225_LM			0x15F2
17 #define IGC_DEV_ID_I225_V			0x15F3
18 #define IGC_DEV_ID_I225_K			0x3100
19 #define IGC_DEV_ID_I225_I			0x15F8
20 #define IGC_DEV_ID_I220_V			0x15F7
21 #define IGC_DEV_ID_I225_K2			0x3101
22 #define IGC_DEV_ID_I225_LMVP			0x5502
23 #define IGC_DEV_ID_I226_K			0x3102
24 #define IGC_DEV_ID_I226_LMVP			0x5503
25 #define IGC_DEV_ID_I225_IT			0x0D9F
26 #define IGC_DEV_ID_I226_LM			0x125B
27 #define IGC_DEV_ID_I226_V			0x125C
28 #define IGC_DEV_ID_I226_IT			0x125D
29 #define IGC_DEV_ID_I221_V			0x125E
30 #define IGC_DEV_ID_I226_BLANK_NVM		0x125F
31 #define IGC_DEV_ID_I225_BLANK_NVM		0x15FD
32 
33 #define IGC_REVISION_0	0
34 #define IGC_REVISION_1	1
35 #define IGC_REVISION_2	2
36 #define IGC_REVISION_3	3
37 #define IGC_REVISION_4	4
38 
39 #define IGC_FUNC_1		1
40 
41 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0	0
42 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1	3
43 
44 enum igc_mac_type {
45 	igc_undefined = 0,
46 	igc_i225,
47 	igc_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
48 };
49 
50 enum igc_media_type {
51 	igc_media_type_unknown = 0,
52 	igc_media_type_copper = 1,
53 	igc_num_media_types
54 };
55 
56 enum igc_nvm_type {
57 	igc_nvm_unknown = 0,
58 	igc_nvm_eeprom_spi,
59 	igc_nvm_flash_hw,
60 	igc_nvm_invm,
61 };
62 
63 enum igc_phy_type {
64 	igc_phy_unknown = 0,
65 	igc_phy_none,
66 	igc_phy_i225,
67 };
68 
69 enum igc_bus_type {
70 	igc_bus_type_unknown = 0,
71 	igc_bus_type_pci,
72 	igc_bus_type_pcix,
73 	igc_bus_type_pci_express,
74 	igc_bus_type_reserved
75 };
76 
77 enum igc_bus_speed {
78 	igc_bus_speed_unknown = 0,
79 	igc_bus_speed_33,
80 	igc_bus_speed_66,
81 	igc_bus_speed_100,
82 	igc_bus_speed_120,
83 	igc_bus_speed_133,
84 	igc_bus_speed_2500,
85 	igc_bus_speed_5000,
86 	igc_bus_speed_reserved
87 };
88 
89 enum igc_bus_width {
90 	igc_bus_width_unknown = 0,
91 	igc_bus_width_pcie_x1,
92 	igc_bus_width_pcie_x2,
93 	igc_bus_width_pcie_x4 = 4,
94 	igc_bus_width_pcie_x8 = 8,
95 	igc_bus_width_32,
96 	igc_bus_width_64,
97 	igc_bus_width_reserved
98 };
99 
100 enum igc_fc_mode {
101 	igc_fc_none = 0,
102 	igc_fc_rx_pause,
103 	igc_fc_tx_pause,
104 	igc_fc_full,
105 	igc_fc_default = 0xFF
106 };
107 
108 enum igc_ms_type {
109 	igc_ms_hw_default = 0,
110 	igc_ms_force_master,
111 	igc_ms_force_slave,
112 	igc_ms_auto
113 };
114 
115 enum igc_smart_speed {
116 	igc_smart_speed_default = 0,
117 	igc_smart_speed_on,
118 	igc_smart_speed_off
119 };
120 
121 #define __le16 u16
122 #define __le32 u32
123 #define __le64 u64
124 /* Receive Descriptor */
125 struct igc_rx_desc {
126 	__le64 buffer_addr; /* Address of the descriptor's data buffer */
127 	__le16 length;      /* Length of data DMAed into data buffer */
128 	__le16 csum; /* Packet checksum */
129 	u8  status;  /* Descriptor status */
130 	u8  errors;  /* Descriptor Errors */
131 	__le16 special;
132 };
133 
134 /* Receive Descriptor - Extended */
135 union igc_rx_desc_extended {
136 	struct {
137 		__le64 buffer_addr;
138 		__le64 reserved;
139 	} read;
140 	struct {
141 		struct {
142 			__le32 mrq; /* Multiple Rx Queues */
143 			union {
144 				__le32 rss; /* RSS Hash */
145 				struct {
146 					__le16 ip_id;  /* IP id */
147 					__le16 csum;   /* Packet Checksum */
148 				} csum_ip;
149 			} hi_dword;
150 		} lower;
151 		struct {
152 			__le32 status_error;  /* ext status/error */
153 			__le16 length;
154 			__le16 vlan; /* VLAN tag */
155 		} upper;
156 	} wb;  /* writeback */
157 };
158 
159 #define MAX_PS_BUFFERS 4
160 
161 /* Number of packet split data buffers (not including the header buffer) */
162 #define PS_PAGE_BUFFERS	(MAX_PS_BUFFERS - 1)
163 
164 /* Receive Descriptor - Packet Split */
165 union igc_rx_desc_packet_split {
166 	struct {
167 		/* one buffer for protocol header(s), three data buffers */
168 		__le64 buffer_addr[MAX_PS_BUFFERS];
169 	} read;
170 	struct {
171 		struct {
172 			__le32 mrq;  /* Multiple Rx Queues */
173 			union {
174 				__le32 rss; /* RSS Hash */
175 				struct {
176 					__le16 ip_id;    /* IP id */
177 					__le16 csum;     /* Packet Checksum */
178 				} csum_ip;
179 			} hi_dword;
180 		} lower;
181 		struct {
182 			__le32 status_error;  /* ext status/error */
183 			__le16 length0;  /* length of buffer 0 */
184 			__le16 vlan;  /* VLAN tag */
185 		} middle;
186 		struct {
187 			__le16 header_status;
188 			/* length of buffers 1-3 */
189 			__le16 length[PS_PAGE_BUFFERS];
190 		} upper;
191 		__le64 reserved;
192 	} wb; /* writeback */
193 };
194 
195 /* Transmit Descriptor */
196 struct igc_tx_desc {
197 	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
198 	union {
199 		__le32 data;
200 		struct {
201 			__le16 length;  /* Data buffer length */
202 			u8 cso;  /* Checksum offset */
203 			u8 cmd;  /* Descriptor control */
204 		} flags;
205 	} lower;
206 	union {
207 		__le32 data;
208 		struct {
209 			u8 status; /* Descriptor status */
210 			u8 css;  /* Checksum start */
211 			__le16 special;
212 		} fields;
213 	} upper;
214 };
215 
216 /* Offload Context Descriptor */
217 struct igc_context_desc {
218 	union {
219 		__le32 ip_config;
220 		struct {
221 			u8 ipcss;  /* IP checksum start */
222 			u8 ipcso;  /* IP checksum offset */
223 			__le16 ipcse;  /* IP checksum end */
224 		} ip_fields;
225 	} lower_setup;
226 	union {
227 		__le32 tcp_config;
228 		struct {
229 			u8 tucss;  /* TCP checksum start */
230 			u8 tucso;  /* TCP checksum offset */
231 			__le16 tucse;  /* TCP checksum end */
232 		} tcp_fields;
233 	} upper_setup;
234 	__le32 cmd_and_length;
235 	union {
236 		__le32 data;
237 		struct {
238 			u8 status;  /* Descriptor status */
239 			u8 hdr_len;  /* Header length */
240 			__le16 mss;  /* Maximum segment size */
241 		} fields;
242 	} tcp_seg_setup;
243 };
244 
245 /* Offload data descriptor */
246 struct igc_data_desc {
247 	__le64 buffer_addr;  /* Address of the descriptor's buffer address */
248 	union {
249 		__le32 data;
250 		struct {
251 			__le16 length;  /* Data buffer length */
252 			u8 typ_len_ext;
253 			u8 cmd;
254 		} flags;
255 	} lower;
256 	union {
257 		__le32 data;
258 		struct {
259 			u8 status;  /* Descriptor status */
260 			u8 popts;  /* Packet Options */
261 			__le16 special;
262 		} fields;
263 	} upper;
264 };
265 
266 /* Statistics counters collected by the MAC */
267 struct igc_hw_stats {
268 	u64 crcerrs;
269 	u64 algnerrc;
270 	u64 symerrs;
271 	u64 rxerrc;
272 	u64 mpc;
273 	u64 scc;
274 	u64 ecol;
275 	u64 mcc;
276 	u64 latecol;
277 	u64 colc;
278 	u64 dc;
279 	u64 tncrs;
280 	u64 sec;
281 	u64 rlec;
282 	u64 xonrxc;
283 	u64 xontxc;
284 	u64 xoffrxc;
285 	u64 xofftxc;
286 	u64 fcruc;
287 	u64 prc64;
288 	u64 prc127;
289 	u64 prc255;
290 	u64 prc511;
291 	u64 prc1023;
292 	u64 prc1522;
293 	u64 tlpic;
294 	u64 rlpic;
295 	u64 gprc;
296 	u64 bprc;
297 	u64 mprc;
298 	u64 gptc;
299 	u64 gorc;
300 	u64 gotc;
301 	u64 rnbc;
302 	u64 ruc;
303 	u64 rfc;
304 	u64 roc;
305 	u64 rjc;
306 	u64 mgprc;
307 	u64 mgpdc;
308 	u64 mgptc;
309 	u64 tor;
310 	u64 tot;
311 	u64 tpr;
312 	u64 tpt;
313 	u64 ptc64;
314 	u64 ptc127;
315 	u64 ptc255;
316 	u64 ptc511;
317 	u64 ptc1023;
318 	u64 ptc1522;
319 	u64 mptc;
320 	u64 bptc;
321 	u64 tsctc;
322 	u64 iac;
323 	u64 rxdmtc;
324 	u64 htdpmc;
325 	u64 rpthc;
326 	u64 hgptc;
327 	u64 hgorc;
328 	u64 hgotc;
329 	u64 lenerrs;
330 	u64 scvpc;
331 	u64 hrmpc;
332 	u64 doosync;
333 	u64 o2bgptc;
334 	u64 o2bspc;
335 	u64 b2ospc;
336 	u64 b2ogprc;
337 };
338 
339 #include "igc_mac.h"
340 #include "igc_phy.h"
341 #include "igc_nvm.h"
342 
343 /* Function pointers for the MAC. */
344 struct igc_mac_operations {
345 	s32  (*init_params)(struct igc_hw *);
346 	s32  (*check_for_link)(struct igc_hw *);
347 	void (*clear_hw_cntrs)(struct igc_hw *);
348 	void (*clear_vfta)(struct igc_hw *);
349 	s32  (*get_bus_info)(struct igc_hw *);
350 	void (*set_lan_id)(struct igc_hw *);
351 	s32  (*get_link_up_info)(struct igc_hw *, u16 *, u16 *);
352 	void (*update_mc_addr_list)(struct igc_hw *, u8 *, u32);
353 	s32  (*reset_hw)(struct igc_hw *);
354 	s32  (*init_hw)(struct igc_hw *);
355 	s32  (*setup_link)(struct igc_hw *);
356 	s32  (*setup_physical_interface)(struct igc_hw *);
357 	void (*write_vfta)(struct igc_hw *, u32, u32);
358 	void (*config_collision_dist)(struct igc_hw *);
359 	int  (*rar_set)(struct igc_hw *, u8*, u32);
360 	s32  (*read_mac_addr)(struct igc_hw *);
361 	s32  (*validate_mdi_setting)(struct igc_hw *);
362 	s32  (*acquire_swfw_sync)(struct igc_hw *, u16);
363 	void (*release_swfw_sync)(struct igc_hw *, u16);
364 };
365 
366 /* When to use various PHY register access functions:
367  *
368  *                 Func   Caller
369  *   Function      Does   Does    When to use
370  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
371  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
372  *   X_reg_locked  P,A    L       for multiple accesses of different regs
373  *                                on different pages
374  *   X_reg_page    A      L,P     for multiple accesses of different regs
375  *                                on the same page
376  *
377  * Where X=[read|write], L=locking, P=sets page, A=register access
378  *
379  */
380 struct igc_phy_operations {
381 	s32  (*init_params)(struct igc_hw *);
382 	s32  (*acquire)(struct igc_hw *);
383 	s32  (*check_reset_block)(struct igc_hw *);
384 	s32  (*force_speed_duplex)(struct igc_hw *);
385 	s32  (*get_info)(struct igc_hw *);
386 	s32  (*set_page)(struct igc_hw *, u16);
387 	s32  (*read_reg)(struct igc_hw *, u32, u16 *);
388 	s32  (*read_reg_locked)(struct igc_hw *, u32, u16 *);
389 	s32  (*read_reg_page)(struct igc_hw *, u32, u16 *);
390 	void (*release)(struct igc_hw *);
391 	s32  (*reset)(struct igc_hw *);
392 	s32  (*set_d0_lplu_state)(struct igc_hw *, bool);
393 	s32  (*set_d3_lplu_state)(struct igc_hw *, bool);
394 	s32  (*write_reg)(struct igc_hw *, u32, u16);
395 	s32  (*write_reg_locked)(struct igc_hw *, u32, u16);
396 	s32  (*write_reg_page)(struct igc_hw *, u32, u16);
397 	void (*power_up)(struct igc_hw *);
398 	void (*power_down)(struct igc_hw *);
399 };
400 
401 /* Function pointers for the NVM. */
402 struct igc_nvm_operations {
403 	s32  (*init_params)(struct igc_hw *);
404 	s32  (*acquire)(struct igc_hw *);
405 	s32  (*read)(struct igc_hw *, u16, u16, u16 *);
406 	void (*release)(struct igc_hw *);
407 	void (*reload)(struct igc_hw *);
408 	s32  (*update)(struct igc_hw *);
409 	s32  (*validate)(struct igc_hw *);
410 	s32  (*write)(struct igc_hw *, u16, u16, u16 *);
411 };
412 
413 struct igc_info {
414 	s32 (*get_invariants)(struct igc_hw *hw);
415 	struct igc_mac_operations *mac_ops;
416 	const struct igc_phy_operations *phy_ops;
417 	struct igc_nvm_operations *nvm_ops;
418 };
419 
420 extern const struct igc_info igc_i225_info;
421 
422 struct igc_mac_info {
423 	struct igc_mac_operations ops;
424 	u8 addr[ETH_ADDR_LEN];
425 	u8 perm_addr[ETH_ADDR_LEN];
426 
427 	enum igc_mac_type type;
428 
429 	u32 mc_filter_type;
430 
431 	u16 current_ifs_val;
432 	u16 ifs_max_val;
433 	u16 ifs_min_val;
434 	u16 ifs_ratio;
435 	u16 ifs_step_size;
436 	u16 mta_reg_count;
437 	u16 uta_reg_count;
438 
439 	/* Maximum size of the MTA register table in all supported adapters */
440 #define MAX_MTA_REG 128
441 	u32 mta_shadow[MAX_MTA_REG];
442 	u16 rar_entry_count;
443 
444 	u8  forced_speed_duplex;
445 
446 	bool asf_firmware_present;
447 	bool autoneg;
448 	bool get_link_status;
449 	u32  max_frame_size;
450 };
451 
452 struct igc_phy_info {
453 	struct igc_phy_operations ops;
454 	enum igc_phy_type type;
455 
456 	enum igc_smart_speed smart_speed;
457 
458 	u32 addr;
459 	u32 id;
460 	u32 reset_delay_us; /* in usec */
461 	u32 revision;
462 
463 	enum igc_media_type media_type;
464 
465 	u16 autoneg_advertised;
466 	u16 autoneg_mask;
467 
468 	u8 mdix;
469 
470 	bool polarity_correction;
471 	bool speed_downgraded;
472 	bool autoneg_wait_to_complete;
473 };
474 
475 struct igc_nvm_info {
476 	struct igc_nvm_operations ops;
477 	enum igc_nvm_type type;
478 
479 	u16 word_size;
480 	u16 delay_usec;
481 	u16 address_bits;
482 	u16 opcode_bits;
483 	u16 page_size;
484 };
485 
486 struct igc_bus_info {
487 	enum igc_bus_type type;
488 	enum igc_bus_speed speed;
489 	enum igc_bus_width width;
490 
491 	u16 func;
492 	u16 pci_cmd_word;
493 };
494 
495 struct igc_fc_info {
496 	u32 high_water;  /* Flow control high-water mark */
497 	u32 low_water;  /* Flow control low-water mark */
498 	u16 pause_time;  /* Flow control pause timer */
499 	u16 refresh_time;  /* Flow control refresh timer */
500 	bool send_xon;  /* Flow control send XON */
501 	bool strict_ieee;  /* Strict IEEE mode */
502 	enum igc_fc_mode current_mode;  /* FC mode in effect */
503 	enum igc_fc_mode requested_mode;  /* FC mode requested by caller */
504 };
505 
506 struct igc_dev_spec_i225 {
507 	bool eee_disable;
508 	bool clear_semaphore_once;
509 	u32 mtu;
510 };
511 
512 struct igc_hw {
513 	void *back;
514 
515 	u8 *hw_addr;
516 	u8 *flash_address;
517 	unsigned long io_base;
518 
519 	struct igc_mac_info  mac;
520 	struct igc_fc_info   fc;
521 	struct igc_phy_info  phy;
522 	struct igc_nvm_info  nvm;
523 	struct igc_bus_info  bus;
524 
525 	union {
526 		struct igc_dev_spec_i225 _i225;
527 	} dev_spec;
528 
529 	u16 device_id;
530 	u16 subsystem_vendor_id;
531 	u16 subsystem_device_id;
532 	u16 vendor_id;
533 
534 	u8  revision_id;
535 };
536 
537 #include "igc_i225.h"
538 #include "igc_base.h"
539 
540 /* These functions must be implemented by drivers */
541 s32  igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
542 s32  igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
543 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
544 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
545 
546 #endif
547