xref: /illumos-gate/usr/src/uts/common/io/audio/drv/audioemu10k/audioemu10k.c (revision 8c16a0e6d0b3d6a8b804825076383c61979302ec)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 /*
28  * Copyright (C) 4Front Technologies 1996-2009.
29  */
30 
31 /*
32  * Purpose: Driver for the Creative Sound Blaster Live! and Audigy/2/4
33  * sound cards
34  */
35 
36 #include <sys/types.h>
37 #include <sys/modctl.h>
38 #include <sys/kmem.h>
39 #include <sys/conf.h>
40 #include <sys/ddi.h>
41 #include <sys/sunddi.h>
42 #include <sys/pci.h>
43 #include <sys/note.h>
44 #include <sys/stdbool.h>
45 #include <sys/audio/audio_driver.h>
46 #include <sys/audio/ac97.h>
47 
48 #include "audioemu10k.h"
49 #include <sys/promif.h>
50 
51 /*
52  * Include the DSP files for emu10k1 (Live!) and emu10k2 (Audigy)
53  */
54 #include "emu10k_gpr.h"
55 #include "emu10k1_dsp.h"
56 #include "emu10k2_dsp.h"
57 
58 static struct ddi_device_acc_attr dev_attr = {
59 	DDI_DEVICE_ATTR_V0,
60 	DDI_STRUCTURE_LE_ACC,
61 	DDI_STRICTORDER_ACC
62 };
63 
64 static struct ddi_device_acc_attr buf_attr = {
65 	DDI_DEVICE_ATTR_V0,
66 	DDI_NEVERSWAP_ACC,
67 	DDI_STRICTORDER_ACC
68 };
69 
70 
71 /*
72  * EMU10K routing stuff.
73  */
74 #define	MAX_SENDS		4
75 #define	SEND_L			0
76 #define	SEND_R			1
77 #define	SEND_SURRL		2
78 #define	SEND_SURRR		3
79 #define	SEND_CEN		4
80 #define	SEND_LFE		5
81 #define	SEND_SIDEL		6
82 #define	SEND_SIDER		7
83 
84 #define	SPDIF_L			20
85 #define	SPDIF_R			21
86 
87 /*
88  * Recording sources... we start from 16 to ensure that the
89  * record sources don't collide with AC'97 record sources in
90  * the control value.
91  */
92 #define	INPUT_AC97		1
93 #define	INPUT_SPD1		2
94 #define	INPUT_SPD2		3
95 #define	INPUT_DIGCD		4
96 #define	INPUT_AUX2		5
97 #define	INPUT_LINE2		6
98 #define	INPUT_STEREOMIX		7
99 
100 static uint8_t front_routing[MAX_SENDS] = {
101 	SEND_L, SEND_R, 0x3f, 0x3f
102 };
103 static uint8_t surr_routing[MAX_SENDS] = {
104 	SEND_SURRL, SEND_SURRR, 0x3f, 0x3f
105 };
106 static uint8_t clfe_routing[MAX_SENDS] = {
107 	SEND_CEN, SEND_LFE, 0x3f, 0x3f
108 };
109 static uint8_t side_routing[MAX_SENDS] = {
110 	SEND_SIDEL, SEND_SIDER, 0x3f, 0x3f
111 };
112 
113 /*
114  * SB Live! cannot do DMA above 2G addresses. Audigy/2/4 have special 8k page
115  * mode that supports high addresses.  However, we should not need this except
116  * on SPARC.  For simplicity's sake, we are only delivering this driver for
117  * x86 platforms.  If SPARC support is desired, then the code will have to
118  * be modified to support full 32-bit addressing.  (And again, SB Live!
119  * can't do it anyway.)
120  */
121 
122 static ddi_dma_attr_t dma_attr_buf = {
123 	DMA_ATTR_V0,		/* Version */
124 	0x00000000ULL,		/* Address low */
125 	0x7ffffff0ULL,		/* Address high */
126 	0xffffffffULL,		/* Counter max */
127 	1ULL,			/* Default byte align */
128 	0x7f,			/* Burst size */
129 	0x1,			/* Minimum xfer size */
130 	0xffffffffULL,		/* Maximum xfer size */
131 	0xffffffffULL,		/* Max segment size */
132 	1,			/* S/G list length */
133 	1,			/* Granularity */
134 	0			/* Flag */
135 };
136 
137 static int emu10k_attach(dev_info_t *);
138 static int emu10k_resume(dev_info_t *);
139 static int emu10k_detach(emu10k_devc_t *);
140 static int emu10k_suspend(emu10k_devc_t *);
141 
142 static int emu10k_open(void *, int, unsigned *, caddr_t *);
143 static void emu10k_close(void *);
144 static int emu10k_start(void *);
145 static void emu10k_stop(void *);
146 static int emu10k_format(void *);
147 static int emu10k_channels(void *);
148 static int emu10k_rate(void *);
149 static uint64_t emu10k_count(void *);
150 static void emu10k_sync(void *, unsigned);
151 static void emu10k_chinfo(void *, int, unsigned *, unsigned *);
152 
153 static uint16_t emu10k_read_ac97(void *, uint8_t);
154 static void emu10k_write_ac97(void *, uint8_t, uint16_t);
155 static int emu10k_alloc_port(emu10k_devc_t *, int);
156 static void emu10k_destroy(emu10k_devc_t *);
157 static int emu10k_hwinit(emu10k_devc_t *);
158 static void emu10k_init_effects(emu10k_devc_t *);
159 
160 static audio_engine_ops_t emu10k_engine_ops = {
161 	AUDIO_ENGINE_VERSION,
162 	emu10k_open,
163 	emu10k_close,
164 	emu10k_start,
165 	emu10k_stop,
166 	emu10k_count,
167 	emu10k_format,
168 	emu10k_channels,
169 	emu10k_rate,
170 	emu10k_sync,
171 	NULL,
172 	emu10k_chinfo,
173 	NULL
174 };
175 
176 static uint16_t
emu10k_read_ac97(void * arg,uint8_t index)177 emu10k_read_ac97(void *arg, uint8_t index)
178 {
179 	emu10k_devc_t *devc = arg;
180 	int dtemp = 0, i;
181 
182 	mutex_enter(&devc->mutex);
183 	OUTB(devc, index, devc->regs + 0x1e);
184 	for (i = 0; i < 10000; i++)
185 		if (INB(devc, devc->regs + 0x1e) & 0x80)
186 			break;
187 
188 	if (i == 1000) {
189 		mutex_exit(&devc->mutex);
190 		return (0);			/* Timeout */
191 	}
192 	dtemp = INW(devc, devc->regs + 0x1c);
193 
194 	mutex_exit(&devc->mutex);
195 
196 	return (dtemp & 0xffff);
197 }
198 
199 static void
emu10k_write_ac97(void * arg,uint8_t index,uint16_t data)200 emu10k_write_ac97(void *arg, uint8_t index, uint16_t data)
201 {
202 	emu10k_devc_t *devc = arg;
203 	int i;
204 
205 	mutex_enter(&devc->mutex);
206 
207 	OUTB(devc, index, devc->regs + 0x1e);
208 	for (i = 0; i < 10000; i++)
209 		if (INB(devc, devc->regs + 0x1e) & 0x80)
210 			break;
211 	OUTW(devc, data, devc->regs + 0x1c);
212 
213 	mutex_exit(&devc->mutex);
214 }
215 
216 static uint32_t
emu10k_read_reg(emu10k_devc_t * devc,int reg,int chn)217 emu10k_read_reg(emu10k_devc_t *devc, int reg, int chn)
218 {
219 	uint32_t ptr, ptr_addr_mask, val, mask, size, offset;
220 
221 	ptr_addr_mask = (devc->feature_mask &
222 	    (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) ?
223 	    0x0fff0000 : 0x07ff0000;
224 	ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f);
225 	OUTL(devc, ptr, devc->regs + 0x00);	/* Pointer */
226 	val = INL(devc, devc->regs + 0x04);	/* Data */
227 	if (reg & 0xff000000) {
228 		size = (reg >> 24) & 0x3f;
229 		offset = (reg >> 16) & 0x1f;
230 		mask = ((1 << size) - 1) << offset;
231 		val &= mask;
232 		val >>= offset;
233 	}
234 
235 	return (val);
236 }
237 
238 static void
emu10k_write_reg(emu10k_devc_t * devc,int reg,int chn,uint32_t value)239 emu10k_write_reg(emu10k_devc_t *devc, int reg, int chn, uint32_t value)
240 {
241 	uint32_t ptr, ptr_addr_mask, mask, size, offset;
242 
243 	ptr_addr_mask = (devc->feature_mask &
244 	    (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) ?
245 	    0x0fff0000 : 0x07ff0000;
246 	ptr = ((reg << 16) & ptr_addr_mask) | (chn & 0x3f);
247 	OUTL(devc, ptr, devc->regs + 0x00);	/* Pointer */
248 	if (reg & 0xff000000) {
249 		size = (reg >> 24) & 0x3f;
250 		offset = (reg >> 16) & 0x1f;
251 		mask = ((1 << size) - 1) << offset;
252 		value <<= offset;
253 		value &= mask;
254 		value |= INL(devc, devc->regs + 0x04) & ~mask;	/* data */
255 	}
256 	OUTL(devc, value, devc->regs + 0x04);	/* Data */
257 }
258 
259 static void
emu10k_write_routing(emu10k_devc_t * devc,int voice,unsigned char * routing)260 emu10k_write_routing(emu10k_devc_t *devc, int voice, unsigned char *routing)
261 {
262 	int i;
263 
264 	ASSERT(routing != NULL);
265 
266 	if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
267 		unsigned int srda = 0;
268 
269 		for (i = 0; i < 4; i++)
270 			srda |= routing[i] << (i * 8);
271 
272 		emu10k_write_reg(devc, SRDA, voice, srda);
273 	} else {
274 		int fxrt = 0;
275 
276 		for (i = 0; i < 4; i++)
277 			fxrt |= routing[i] << ((i * 4) + 16);
278 		emu10k_write_reg(devc, FXRT, voice, fxrt);
279 	}
280 }
281 
282 static void
emu10k_write_efx(emu10k_devc_t * devc,int reg,unsigned int value)283 emu10k_write_efx(emu10k_devc_t *devc, int reg, unsigned int value)
284 {
285 	emu10k_write_reg(devc, reg, 0, value);
286 }
287 
288 /*
289  * Audio routines
290  */
291 
292 static void
emu10k_update_output_volume(emu10k_portc_t * portc,int voice,int chn)293 emu10k_update_output_volume(emu10k_portc_t *portc, int voice, int chn)
294 {
295 	emu10k_devc_t *devc = portc->devc;
296 	unsigned int tmp;
297 	unsigned char send[2];
298 
299 	/*
300 	 * Each voice operator of EMU10k has 4 sends (0=left, 1=right,
301 	 * 2=surround_left, 3=surround_right). The original OSS driver
302 	 * used all of them to spread stereo output to two different
303 	 * speaker pairs. This Boomer version uses only the first two
304 	 * sends. The other sends are set to 0.
305 	 *
306 	 * Boomer uses multiple voice pairs to play multichannel
307 	 * audio. This function is used to update only one of these
308 	 * pairs.
309 	 */
310 
311 	send[0] = 0xff;		/* Max */
312 	send[1] = 0xff;		/* Max */
313 
314 	/* Analog voice */
315 	if (chn == LEFT_CH) {
316 		send[1] = 0;
317 	} else {
318 		send[0] = 0;
319 	}
320 
321 	tmp = emu10k_read_reg(devc, PTAB, voice) & 0xffff0000;
322 	emu10k_write_reg(devc, PTAB, voice, tmp | (send[0] << 8) | send[1]);
323 }
324 
325 static void
emu10k_setup_voice(emu10k_portc_t * portc,int voice,int chn,int buf_offset)326 emu10k_setup_voice(emu10k_portc_t *portc, int voice, int chn, int buf_offset)
327 {
328 	emu10k_devc_t *devc = portc->devc;
329 	unsigned int nCRA = 0;
330 
331 	unsigned int loop_start, loop_end, buf_size;
332 
333 	int sz;
334 	int start_pos;
335 
336 	emu10k_write_reg(devc, VEDS, voice, 0x0);	/* OFF */
337 	emu10k_write_reg(devc, VTFT, voice, 0xffff);
338 	emu10k_write_reg(devc, CVCF, voice, 0xffff);
339 
340 	sz = 2;			/* Shift value for 16 bits stereo */
341 
342 	/* Size of one stereo sub buffer */
343 	buf_size = (portc->buf_size / portc->channels) * 2;
344 	loop_start = (portc->memptr + buf_offset) >> sz;
345 	loop_end = (portc->memptr + buf_offset + buf_size) >> sz;
346 
347 	/* set stereo */
348 	emu10k_write_reg(devc, CPF, voice, 0x8000);
349 
350 	nCRA = 28;			/* Stereo (16 bits) */
351 	start_pos = loop_start + nCRA;
352 
353 	/* SDL, ST, CA */
354 
355 	emu10k_write_reg(devc, SDL, voice, loop_end);
356 	emu10k_write_reg(devc, SCSA, voice, loop_start);
357 	emu10k_write_reg(devc, PTAB, voice, 0);
358 
359 	emu10k_update_output_volume(portc, voice, chn);	/* Set volume */
360 
361 	emu10k_write_reg(devc, QKBCA, voice, start_pos);
362 
363 	emu10k_write_reg(devc, Z1, voice, 0);
364 	emu10k_write_reg(devc, Z2, voice, 0);
365 
366 	/* This is really a physical address */
367 	emu10k_write_reg(devc, MAPA, voice,
368 	    0x1fff | (devc->silence_paddr << 1));
369 	emu10k_write_reg(devc, MAPB, voice,
370 	    0x1fff | (devc->silence_paddr << 1));
371 
372 	emu10k_write_reg(devc, VTFT, voice, 0x0000ffff);
373 	emu10k_write_reg(devc, CVCF, voice, 0x0000ffff);
374 	emu10k_write_reg(devc, MEHA, voice, 0);
375 	emu10k_write_reg(devc, MEDS, voice, 0x7f);
376 	emu10k_write_reg(devc, MLV, voice, 0x8000);
377 	emu10k_write_reg(devc, VLV, voice, 0x8000);
378 	emu10k_write_reg(devc, VFM, voice, 0);
379 	emu10k_write_reg(devc, TMFQ, voice, 0);
380 	emu10k_write_reg(devc, VVFQ, voice, 0);
381 	emu10k_write_reg(devc, MEV, voice, 0x8000);
382 	emu10k_write_reg(devc, VEHA, voice, 0x7f7f);	/* OK */
383 	/* No volume envelope delay (OK) */
384 	emu10k_write_reg(devc, VEV, voice, 0x8000);
385 	emu10k_write_reg(devc, PEFE_FILTERAMOUNT, voice, 0x7f);
386 	emu10k_write_reg(devc, PEFE_PITCHAMOUNT, voice, 0x00);
387 }
388 
389 int
emu10k_open(void * arg,int flag,unsigned * nframes,caddr_t * bufp)390 emu10k_open(void *arg, int flag, unsigned *nframes, caddr_t *bufp)
391 {
392 	emu10k_portc_t *portc = arg;
393 	emu10k_devc_t *devc = portc->devc;
394 
395 	_NOTE(ARGUNUSED(flag));
396 
397 	portc->active = B_FALSE;
398 	*nframes = portc->nframes;
399 	*bufp = portc->buf_kaddr;
400 
401 	mutex_enter(&devc->mutex);
402 	portc->count = 0;
403 	mutex_exit(&devc->mutex);
404 
405 	return (0);
406 }
407 
408 void
emu10k_close(void * arg)409 emu10k_close(void *arg)
410 {
411 	_NOTE(ARGUNUSED(arg));
412 }
413 
414 int
emu10k_start(void * arg)415 emu10k_start(void *arg)
416 {
417 	emu10k_portc_t *portc = arg;
418 	emu10k_devc_t *devc = portc->devc;
419 
420 	mutex_enter(&devc->mutex);
421 	portc->reset_port(portc);
422 	portc->start_port(portc);
423 	mutex_exit(&devc->mutex);
424 	return (0);
425 }
426 
427 void
emu10k_stop(void * arg)428 emu10k_stop(void *arg)
429 {
430 	emu10k_portc_t *portc = arg;
431 	emu10k_devc_t *devc = portc->devc;
432 
433 	mutex_enter(&devc->mutex);
434 	portc->stop_port(portc);
435 	mutex_exit(&devc->mutex);
436 }
437 
438 int
emu10k_format(void * arg)439 emu10k_format(void *arg)
440 {
441 	_NOTE(ARGUNUSED(arg));
442 
443 	return (AUDIO_FORMAT_S16_LE);
444 }
445 
446 int
emu10k_channels(void * arg)447 emu10k_channels(void *arg)
448 {
449 	emu10k_portc_t *portc = arg;
450 
451 	return (portc->channels);
452 }
453 
454 int
emu10k_rate(void * arg)455 emu10k_rate(void *arg)
456 {
457 	_NOTE(ARGUNUSED(arg));
458 
459 	return (SAMPLE_RATE);
460 }
461 
462 void
emu10k_sync(void * arg,unsigned nframes)463 emu10k_sync(void *arg, unsigned nframes)
464 {
465 	emu10k_portc_t *portc = arg;
466 	_NOTE(ARGUNUSED(nframes));
467 
468 	(void) ddi_dma_sync(portc->buf_dmah, 0, 0, portc->syncdir);
469 }
470 
471 uint64_t
emu10k_count(void * arg)472 emu10k_count(void *arg)
473 {
474 	emu10k_portc_t *portc = arg;
475 	emu10k_devc_t *devc = portc->devc;
476 	uint64_t count;
477 
478 	mutex_enter(&devc->mutex);
479 	portc->update_port(portc);
480 	count = portc->count;
481 	mutex_exit(&devc->mutex);
482 
483 	return (count);
484 }
485 
486 static void
emu10k_chinfo(void * arg,int chan,unsigned * offset,unsigned * incr)487 emu10k_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr)
488 {
489 	emu10k_portc_t *portc = arg;
490 
491 	*offset = portc->nframes * (chan / 2) * 2 + (chan % 2);
492 	*incr = 2;
493 }
494 
495 /* private implementation bits */
496 
497 static void
emu10k_set_loop_stop(emu10k_devc_t * devc,int voice,int s)498 emu10k_set_loop_stop(emu10k_devc_t *devc, int voice, int s)
499 {
500 	unsigned int tmp;
501 	int offs, bit;
502 
503 	offs = voice / 32;
504 	bit = voice % 32;
505 	s = !!s;
506 
507 	tmp = emu10k_read_reg(devc, SOLL + offs, 0);
508 	tmp &= ~(1 << bit);
509 
510 	if (s)
511 		tmp |= (1 << bit);
512 	emu10k_write_reg(devc, SOLL + offs, 0, tmp);
513 }
514 
515 static unsigned int
emu10k_rate_to_pitch(unsigned int rate)516 emu10k_rate_to_pitch(unsigned int rate)
517 {
518 	static unsigned int logMagTable[128] = {
519 		0x00000, 0x02dfc, 0x05b9e, 0x088e6,
520 		0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2,
521 		0x1663f, 0x1918a, 0x1bc84, 0x1e72e,
522 		0x2118b, 0x23b9a, 0x2655d, 0x28ed5,
523 		0x2b803, 0x2e0e8, 0x30985, 0x331db,
524 		0x359eb, 0x381b6, 0x3a93d, 0x3d081,
525 		0x3f782, 0x41e42, 0x444c1, 0x46b01,
526 		0x49101, 0x4b6c4, 0x4dc49, 0x50191,
527 		0x5269e, 0x54b6f, 0x57006, 0x59463,
528 		0x5b888, 0x5dc74, 0x60029, 0x623a7,
529 		0x646ee, 0x66a00, 0x68cdd, 0x6af86,
530 		0x6d1fa, 0x6f43c, 0x7164b, 0x73829,
531 		0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5,
532 		0x7dea1, 0x7ff5e, 0x81fed, 0x8404e,
533 		0x86082, 0x88089, 0x8a064, 0x8c014,
534 		0x8df98, 0x8fef1, 0x91e20, 0x93d26,
535 		0x95c01, 0x97ab4, 0x9993e, 0x9b79f,
536 		0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d,
537 		0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537,
538 		0xac241, 0xadf26, 0xafbe7, 0xb1885,
539 		0xb3500, 0xb5157, 0xb6d8c, 0xb899f,
540 		0xba58f, 0xbc15e, 0xbdd0c, 0xbf899,
541 		0xc1404, 0xc2f50, 0xc4a7b, 0xc6587,
542 		0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c,
543 		0xceaec, 0xd053f, 0xd1f73, 0xd398a,
544 		0xd5384, 0xd6d60, 0xd8720, 0xda0c3,
545 		0xdba4a, 0xdd3b4, 0xded03, 0xe0636,
546 		0xe1f4e, 0xe384a, 0xe512c, 0xe69f3,
547 		0xe829f, 0xe9b31, 0xeb3a9, 0xecc08,
548 		0xee44c, 0xefc78, 0xf148a, 0xf2c83,
549 		0xf4463, 0xf5c2a, 0xf73da, 0xf8b71,
550 		0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df
551 	};
552 	static char logSlopeTable[128] = {
553 		0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58,
554 		0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53,
555 		0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f,
556 		0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b,
557 		0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47,
558 		0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44,
559 		0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41,
560 		0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e,
561 		0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c,
562 		0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39,
563 		0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37,
564 		0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35,
565 		0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34,
566 		0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32,
567 		0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30,
568 		0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f
569 	};
570 	int i;
571 
572 	if (rate == 0)
573 		return (0);			/* Bail out if no leading "1" */
574 	rate *= 11185;		/* Scale 48000 to 0x20002380 */
575 	for (i = 31; i > 0; i--) {
576 		if (rate & 0x80000000) {	/* Detect leading "1" */
577 			return (((unsigned int) (i - 15) << 20) +
578 			    logMagTable[0x7f & (rate >> 24)] +
579 			    (0x7f & (rate >> 17)) *
580 			    logSlopeTable[0x7f & (rate >> 24)]);
581 		}
582 		rate <<= 1;
583 	}
584 
585 	return (0);			/* Should never reach this point */
586 }
587 
588 static unsigned int
emu10k_rate_to_linearpitch(unsigned int rate)589 emu10k_rate_to_linearpitch(unsigned int rate)
590 {
591 	rate = (rate << 8) / 375;
592 	return (rate >> 1) + (rate & 1);
593 }
594 
595 static void
emu10k_prepare_voice(emu10k_devc_t * devc,int voice)596 emu10k_prepare_voice(emu10k_devc_t *devc, int voice)
597 {
598 	unsigned int sample, initial_pitch, pitch_target;
599 	unsigned int cra, cs, ccis, i;
600 
601 	/* setup CCR regs */
602 	cra = 64;
603 	cs = 4;			/* Stereo */
604 	ccis = 28;		/* Stereo */
605 	sample = 0;		/* 16 bit silence */
606 
607 	for (i = 0; i < cs; i++)
608 		emu10k_write_reg(devc, CD0 + i, voice, sample);
609 
610 	emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, 0);
611 	emu10k_write_reg(devc, CCR_READADDRESS, voice, cra);
612 	emu10k_write_reg(devc, CCR_CACHEINVALIDSIZE, voice, ccis);
613 
614 	/* Set current pitch */
615 	emu10k_write_reg(devc, IFA, voice, 0xff00);
616 	emu10k_write_reg(devc, VTFT, voice, 0xffffffff);
617 	emu10k_write_reg(devc, CVCF, voice, 0xffffffff);
618 	emu10k_set_loop_stop(devc, voice, 0);
619 
620 	pitch_target = emu10k_rate_to_linearpitch(SAMPLE_RATE);
621 	initial_pitch = emu10k_rate_to_pitch(SAMPLE_RATE) >> 8;
622 	emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, pitch_target);
623 	emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, pitch_target);
624 	emu10k_write_reg(devc, IP, voice, initial_pitch);
625 }
626 
627 static void
emu10k_stop_voice(emu10k_devc_t * devc,int voice)628 emu10k_stop_voice(emu10k_devc_t *devc, int voice)
629 {
630 	emu10k_write_reg(devc, IFA, voice, 0xffff);
631 	emu10k_write_reg(devc, VTFT, voice, 0xffff);
632 	emu10k_write_reg(devc, PTRX_PITCHTARGET, voice, 0);
633 	emu10k_write_reg(devc, CPF_CURRENTPITCH, voice, 0);
634 	emu10k_write_reg(devc, IP, voice, 0);
635 	emu10k_set_loop_stop(devc, voice, 1);
636 }
637 
638 static void
emu10k_reset_pair(emu10k_portc_t * portc,int voice,uint8_t * routing,int buf_offset)639 emu10k_reset_pair(emu10k_portc_t *portc, int voice, uint8_t *routing,
640     int buf_offset)
641 {
642 	emu10k_devc_t *devc = portc->devc;
643 
644 	/* Left channel */
645 	/* Intial filter cutoff and attenuation */
646 	emu10k_write_reg(devc, IFA, voice, 0xffff);
647 	/* Volume envelope decay and sustain */
648 	emu10k_write_reg(devc, VEDS, voice, 0x0);
649 	/* Volume target and Filter cutoff target */
650 	emu10k_write_reg(devc, VTFT, voice, 0xffff);
651 	/* Pitch target and sends A and B */
652 	emu10k_write_reg(devc, PTAB, voice, 0x0);
653 
654 	/* The same for right channel */
655 	emu10k_write_reg(devc, IFA, voice + 1, 0xffff);
656 	emu10k_write_reg(devc, VEDS, voice + 1, 0x0);
657 	emu10k_write_reg(devc, VTFT, voice + 1, 0xffff);
658 	emu10k_write_reg(devc, PTAB, voice + 1, 0x0);
659 
660 	/* now setup the voices and go! */
661 	emu10k_setup_voice(portc, voice, LEFT_CH, buf_offset);
662 	emu10k_setup_voice(portc, voice + 1, RIGHT_CH, buf_offset);
663 
664 	emu10k_write_routing(devc, voice, routing);
665 	emu10k_write_routing(devc, voice + 1, routing);
666 }
667 
668 void
emu10k_start_play(emu10k_portc_t * portc)669 emu10k_start_play(emu10k_portc_t *portc)
670 {
671 	emu10k_devc_t *devc = portc->devc;
672 
673 	ASSERT(mutex_owned(&devc->mutex));
674 	emu10k_prepare_voice(devc, 0);
675 	emu10k_prepare_voice(devc, 1);
676 
677 	emu10k_prepare_voice(devc, 2);
678 	emu10k_prepare_voice(devc, 3);
679 
680 	emu10k_prepare_voice(devc, 4);
681 	emu10k_prepare_voice(devc, 5);
682 
683 	emu10k_prepare_voice(devc, 6);
684 	emu10k_prepare_voice(devc, 7);
685 
686 	/* Trigger playback on all voices */
687 	emu10k_write_reg(devc, VEDS, 0, 0x7f7f);
688 	emu10k_write_reg(devc, VEDS, 1, 0x7f7f);
689 	emu10k_write_reg(devc, VEDS, 2, 0x7f7f);
690 	emu10k_write_reg(devc, VEDS, 3, 0x7f7f);
691 	emu10k_write_reg(devc, VEDS, 4, 0x7f7f);
692 	emu10k_write_reg(devc, VEDS, 5, 0x7f7f);
693 	emu10k_write_reg(devc, VEDS, 6, 0x7f7f);
694 	emu10k_write_reg(devc, VEDS, 7, 0x7f7f);
695 
696 	portc->active = B_TRUE;
697 }
698 
699 void
emu10k_stop_play(emu10k_portc_t * portc)700 emu10k_stop_play(emu10k_portc_t *portc)
701 {
702 	emu10k_devc_t *devc = portc->devc;
703 
704 	emu10k_stop_voice(devc, 0);
705 	emu10k_stop_voice(devc, 1);
706 	emu10k_stop_voice(devc, 2);
707 	emu10k_stop_voice(devc, 3);
708 	emu10k_stop_voice(devc, 4);
709 	emu10k_stop_voice(devc, 5);
710 	emu10k_stop_voice(devc, 6);
711 	emu10k_stop_voice(devc, 7);
712 
713 	portc->active = B_FALSE;
714 }
715 
716 void
emu10k_reset_play(emu10k_portc_t * portc)717 emu10k_reset_play(emu10k_portc_t *portc)
718 {
719 	emu10k_devc_t *devc = portc->devc;
720 	uint32_t offs;
721 
722 	offs = (portc->buf_size / portc->channels) * 2;
723 
724 	if (devc->feature_mask & SB_71) {
725 		emu10k_reset_pair(portc, 0, front_routing, 0);
726 		emu10k_reset_pair(portc, 2, clfe_routing, offs);
727 		emu10k_reset_pair(portc, 4, surr_routing, 2 * offs);
728 		emu10k_reset_pair(portc, 6, side_routing, 3 * offs);
729 	} else if (devc->feature_mask & SB_51) {
730 		emu10k_reset_pair(portc, 0, front_routing, 0);
731 		emu10k_reset_pair(portc, 2, clfe_routing, offs);
732 		emu10k_reset_pair(portc, 4, surr_routing, 2 * offs);
733 	} else {
734 		emu10k_reset_pair(portc, 0, front_routing, 0);
735 		emu10k_reset_pair(portc, 2, surr_routing, offs);
736 	}
737 
738 	portc->pos = 0;
739 }
740 
741 uint32_t emu10k_vars[5];
742 
743 void
emu10k_update_play(emu10k_portc_t * portc)744 emu10k_update_play(emu10k_portc_t *portc)
745 {
746 	emu10k_devc_t *devc = portc->devc;
747 	uint32_t cnt, pos;
748 
749 	/*
750 	 * Note: position is given as stereo samples, i.e. frames.
751 	 */
752 	pos = emu10k_read_reg(devc, QKBCA, 0) & 0xffffff;
753 	pos -= (portc->memptr >> 2);
754 	if (pos > portc->nframes) {
755 		/*
756 		 * This should never happen!  If it happens, we should
757 		 * throw an FMA fault.  (When we support FMA.)  For now
758 		 * we just assume the device is stuck, and report no
759 		 * change in position.
760 		 */
761 		pos = portc->pos;
762 	}
763 	ASSERT(pos <= portc->nframes);
764 
765 	if (pos < portc->pos) {
766 		cnt = (portc->nframes - portc->pos) + pos;
767 	} else {
768 		cnt = (pos - portc->pos);
769 	}
770 	ASSERT(cnt <= portc->nframes);
771 	if (portc->dopos) {
772 		emu10k_vars[0] = portc->pos;
773 		emu10k_vars[1] = pos;
774 		emu10k_vars[2] = (uint32_t)portc->count;
775 		emu10k_vars[3] = cnt;
776 		portc->dopos = 0;
777 	}
778 	portc->count += cnt;
779 	portc->pos = pos;
780 }
781 
782 void
emu10k_start_rec(emu10k_portc_t * portc)783 emu10k_start_rec(emu10k_portc_t *portc)
784 {
785 	emu10k_devc_t *devc = portc->devc;
786 	uint32_t tmp;
787 
788 	tmp = 0;			/* setup 48Kz */
789 	if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL))
790 		tmp |= 0x30;		/* Left/right channel enable */
791 	else
792 		tmp |= 0x18;		/* Left/right channel enable */
793 	emu10k_write_reg(devc, ADCSR, 0, tmp);	/* GO */
794 
795 	portc->active = B_TRUE;
796 }
797 
798 void
emu10k_stop_rec(emu10k_portc_t * portc)799 emu10k_stop_rec(emu10k_portc_t *portc)
800 {
801 	emu10k_devc_t *devc = portc->devc;
802 
803 	ASSERT(mutex_owned(&devc->mutex));
804 	emu10k_write_reg(devc, ADCSR, 0, 0);
805 
806 	portc->active = B_FALSE;
807 }
808 void
emu10k_reset_rec(emu10k_portc_t * portc)809 emu10k_reset_rec(emu10k_portc_t *portc)
810 {
811 	emu10k_devc_t *devc = portc->devc;
812 	uint32_t sz;
813 
814 	switch (portc->buf_size) {
815 	case 4096:
816 		sz = 15;
817 		break;
818 	case 8192:
819 		sz = 19;
820 		break;
821 	case 16384:
822 		sz = 23;
823 		break;
824 	case 32768:
825 		sz = 27;
826 		break;
827 	case 65536:
828 		sz = 31;
829 		break;
830 	default:
831 		/*
832 		 * Can't really reach here, but this keeps the compiler quiet.
833 		 */
834 		return;
835 	}
836 	emu10k_write_reg(devc, ADCBA, 0, portc->buf_paddr);
837 	emu10k_write_reg(devc, ADCBS, 0, sz);
838 	emu10k_write_reg(devc, ADCSR, 0, 0);	/* reset for phase */
839 	portc->pos = 0;
840 }
841 
842 void
emu10k_update_rec(emu10k_portc_t * portc)843 emu10k_update_rec(emu10k_portc_t *portc)
844 {
845 	emu10k_devc_t *devc = portc->devc;
846 	uint32_t cnt, pos;
847 
848 	/* given in bytes, we divide all counts by 4 to get samples */
849 	pos = emu10k_read_reg(devc,
850 	    (devc->feature_mask & SB_LIVE) ? MIDX : ADCIDX, 0);
851 	if (pos <= portc->pos) {
852 		cnt = ((portc->buf_size) - portc->pos) >> 2;
853 		cnt += (pos >> 2);
854 	} else {
855 		cnt = ((pos - portc->pos) >> 2);
856 	}
857 	portc->count += cnt;
858 	portc->pos = pos;
859 }
860 
861 int
emu10k_alloc_port(emu10k_devc_t * devc,int num)862 emu10k_alloc_port(emu10k_devc_t *devc, int num)
863 {
864 	emu10k_portc_t *portc;
865 	size_t len;
866 	ddi_dma_cookie_t cookie;
867 	uint_t count;
868 	int dir;
869 	unsigned caps;
870 	audio_dev_t *adev;
871 	int i, n;
872 
873 	adev = devc->adev;
874 	portc = kmem_zalloc(sizeof (*portc), KM_SLEEP);
875 	devc->portc[num] = portc;
876 	portc->devc = devc;
877 
878 	portc->memptr = devc->audio_memptr;
879 	devc->audio_memptr += (DMABUF_SIZE + 4095) & ~4095;
880 
881 	switch (num) {
882 	case EMU10K_REC:
883 		portc->syncdir = DDI_DMA_SYNC_FORKERNEL;
884 		caps = ENGINE_INPUT_CAP;
885 		dir = DDI_DMA_READ;
886 		portc->channels = 2;
887 		portc->start_port = emu10k_start_rec;
888 		portc->stop_port = emu10k_stop_rec;
889 		portc->reset_port = emu10k_reset_rec;
890 		portc->update_port = emu10k_update_rec;
891 		/* This is the minimum record buffer size. */
892 		portc->buf_size = 4096;
893 		portc->nframes = portc->buf_size / 4;
894 		break;
895 	case EMU10K_PLAY:
896 		portc->syncdir = DDI_DMA_SYNC_FORDEV;
897 		caps = ENGINE_OUTPUT_CAP;
898 		dir = DDI_DMA_WRITE;
899 		portc->channels = 8;
900 		portc->start_port = emu10k_start_play;
901 		portc->stop_port = emu10k_stop_play;
902 		portc->reset_port = emu10k_reset_play;
903 		portc->update_port = emu10k_update_play;
904 		/* This could probably be tunable. */
905 		portc->nframes = 2048;
906 		portc->buf_size = portc->nframes * portc->channels * 2;
907 		break;
908 	default:
909 		return (DDI_FAILURE);
910 	}
911 
912 	/*
913 	 * Fragments that are not powers of two don't seem to work
914 	 * at all with EMU10K.  For simplicity's sake, we eliminate
915 	 * the question and fix the interrupt rate.  This is also the
916 	 * logical minimum for record, which requires at least 4K for
917 	 * the record size.
918 	 */
919 
920 	if (portc->buf_size > DMABUF_SIZE) {
921 		cmn_err(CE_NOTE, "Buffer size %d is too large (max %d)",
922 		    (int)portc->buf_size, DMABUF_SIZE);
923 		portc->buf_size = DMABUF_SIZE;
924 	}
925 
926 	/* Alloc buffers */
927 	if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL,
928 	    &portc->buf_dmah) != DDI_SUCCESS) {
929 		audio_dev_warn(adev, "failed to allocate BUF handle");
930 		return (DDI_FAILURE);
931 	}
932 
933 	if (ddi_dma_mem_alloc(portc->buf_dmah, portc->buf_size,
934 	    &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
935 	    &portc->buf_kaddr, &len, &portc->buf_acch) != DDI_SUCCESS) {
936 		audio_dev_warn(adev, "failed to allocate BUF memory");
937 		return (DDI_FAILURE);
938 	}
939 
940 	if (ddi_dma_addr_bind_handle(portc->buf_dmah, NULL, portc->buf_kaddr,
941 	    len, DDI_DMA_CONSISTENT | dir, DDI_DMA_SLEEP,
942 	    NULL, &cookie, &count) != DDI_SUCCESS) {
943 		audio_dev_warn(adev, "failed binding BUF DMA handle");
944 		return (DDI_FAILURE);
945 	}
946 	portc->buf_paddr = cookie.dmac_address;
947 
948 	if ((devc->feature_mask & SB_LIVE) &&
949 	    (portc->buf_paddr & 0x80000000)) {
950 		audio_dev_warn(adev, "Got DMA buffer beyond 2G limit.");
951 		return (DDI_FAILURE);
952 	}
953 
954 	if (num == EMU10K_PLAY) {	/* Output device */
955 		n = portc->memptr / 4096;
956 		/*
957 		 * Fill the page table
958 		 */
959 		for (i = 0; i < portc->buf_size / 4096; i++) {
960 			FILL_PAGE_MAP_ENTRY(n + i,
961 			    portc->buf_paddr + i * 4096);
962 		}
963 
964 		(void) ddi_dma_sync(devc->pt_dmah, 0, 0, DDI_DMA_SYNC_FORDEV);
965 	}
966 
967 	portc->engine = audio_engine_alloc(&emu10k_engine_ops, caps);
968 	if (portc->engine == NULL) {
969 		audio_dev_warn(adev, "audio_engine_alloc failed");
970 		return (DDI_FAILURE);
971 	}
972 
973 	audio_engine_set_private(portc->engine, portc);
974 	audio_dev_add_engine(adev, portc->engine);
975 
976 	return (DDI_SUCCESS);
977 }
978 
979 void
emu10k_destroy(emu10k_devc_t * devc)980 emu10k_destroy(emu10k_devc_t *devc)
981 {
982 	mutex_destroy(&devc->mutex);
983 
984 	if (devc->silence_paddr) {
985 		(void) ddi_dma_unbind_handle(devc->silence_dmah);
986 	}
987 	if (devc->silence_acch) {
988 		ddi_dma_mem_free(&devc->silence_acch);
989 	}
990 	if (devc->silence_dmah) {
991 		ddi_dma_free_handle(&devc->silence_dmah);
992 	}
993 
994 	if (devc->pt_paddr) {
995 		(void) ddi_dma_unbind_handle(devc->pt_dmah);
996 	}
997 	if (devc->pt_acch) {
998 		ddi_dma_mem_free(&devc->pt_acch);
999 	}
1000 	if (devc->pt_dmah) {
1001 		ddi_dma_free_handle(&devc->pt_dmah);
1002 	}
1003 
1004 
1005 	for (int i = 0; i < CTL_MAX; i++) {
1006 		emu10k_ctrl_t *ec = &devc->ctrls[i];
1007 		if (ec->ctrl != NULL) {
1008 			audio_dev_del_control(ec->ctrl);
1009 			ec->ctrl = NULL;
1010 		}
1011 	}
1012 
1013 	for (int i = 0; i < EMU10K_NUM_PORTC; i++) {
1014 		emu10k_portc_t *portc = devc->portc[i];
1015 		if (!portc)
1016 			continue;
1017 		if (portc->engine) {
1018 			audio_dev_remove_engine(devc->adev, portc->engine);
1019 			audio_engine_free(portc->engine);
1020 		}
1021 		if (portc->buf_paddr) {
1022 			(void) ddi_dma_unbind_handle(portc->buf_dmah);
1023 		}
1024 		if (portc->buf_acch) {
1025 			ddi_dma_mem_free(&portc->buf_acch);
1026 		}
1027 		if (portc->buf_dmah) {
1028 			ddi_dma_free_handle(&portc->buf_dmah);
1029 		}
1030 		kmem_free(portc, sizeof (*portc));
1031 	}
1032 
1033 	if (devc->ac97 != NULL) {
1034 		ac97_free(devc->ac97);
1035 	}
1036 	if (devc->adev != NULL) {
1037 		audio_dev_free(devc->adev);
1038 	}
1039 	if (devc->regsh != NULL) {
1040 		ddi_regs_map_free(&devc->regsh);
1041 	}
1042 	if (devc->pcih != NULL) {
1043 		pci_config_teardown(&devc->pcih);
1044 	}
1045 
1046 	kmem_free(devc, sizeof (*devc));
1047 }
1048 
1049 static void
emu10k_init_voice(emu10k_devc_t * devc,int voice)1050 emu10k_init_voice(emu10k_devc_t *devc, int voice)
1051 {
1052 	emu10k_set_loop_stop(devc, voice, 1);
1053 
1054 	emu10k_write_reg(devc, VEDS, voice, 0x0);
1055 	emu10k_write_reg(devc, IP, voice, 0x0);
1056 	emu10k_write_reg(devc, VTFT, voice, 0xffff);
1057 	emu10k_write_reg(devc, CVCF, voice, 0xffff);
1058 	emu10k_write_reg(devc, PTAB, voice, 0x0);
1059 	emu10k_write_reg(devc, CPF, voice, 0x0);
1060 	emu10k_write_reg(devc, CCR, voice, 0x0);
1061 	emu10k_write_reg(devc, SCSA, voice, 0x0);
1062 	emu10k_write_reg(devc, SDL, voice, 0x10);
1063 	emu10k_write_reg(devc, QKBCA, voice, 0x0);
1064 	emu10k_write_reg(devc, Z1, voice, 0x0);
1065 	emu10k_write_reg(devc, Z2, voice, 0x0);
1066 
1067 	if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL))
1068 		emu10k_write_reg(devc, SRDA, voice, 0x03020100);
1069 	else
1070 		emu10k_write_reg(devc, FXRT, voice, 0x32100000);
1071 
1072 	emu10k_write_reg(devc, MEHA, voice, 0x0);
1073 	emu10k_write_reg(devc, MEDS, voice, 0x0);
1074 	emu10k_write_reg(devc, IFA, voice, 0xffff);
1075 	emu10k_write_reg(devc, PEFE, voice, 0x0);
1076 	emu10k_write_reg(devc, VFM, voice, 0x0);
1077 	emu10k_write_reg(devc, TMFQ, voice, 24);
1078 	emu10k_write_reg(devc, VVFQ, voice, 24);
1079 	emu10k_write_reg(devc, TMPE, voice, 0x0);
1080 	emu10k_write_reg(devc, VLV, voice, 0x0);
1081 	emu10k_write_reg(devc, MLV, voice, 0x0);
1082 	emu10k_write_reg(devc, VEHA, voice, 0x0);
1083 	emu10k_write_reg(devc, VEV, voice, 0x0);
1084 	emu10k_write_reg(devc, MEV, voice, 0x0);
1085 
1086 	if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1087 		emu10k_write_reg(devc, CSBA, voice, 0x0);
1088 		emu10k_write_reg(devc, CSDC, voice, 0x0);
1089 		emu10k_write_reg(devc, CSFE, voice, 0x0);
1090 		emu10k_write_reg(devc, CSHG, voice, 0x0);
1091 		emu10k_write_reg(devc, SRHE, voice, 0x3f3f3f3f);
1092 	}
1093 }
1094 
1095 int
emu10k_hwinit(emu10k_devc_t * devc)1096 emu10k_hwinit(emu10k_devc_t *devc)
1097 {
1098 
1099 	unsigned int tmp, i;
1100 	unsigned int reg;
1101 
1102 	ASSERT(mutex_owned(&devc->mutex));
1103 
1104 	emu10k_write_reg(devc, AC97SLOT, 0, AC97SLOT_CENTER | AC97SLOT_LFE);
1105 
1106 	OUTL(devc, 0x00000000, devc->regs + 0x0c);	/* Intr disable */
1107 	OUTL(devc, HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK |
1108 	    HCFG_MUTEBUTTONENABLE,
1109 	    devc->regs + HCFG);
1110 
1111 	emu10k_write_reg(devc, MBS, 0, 0x0);
1112 	emu10k_write_reg(devc, MBA, 0, 0x0);
1113 	emu10k_write_reg(devc, FXBS, 0, 0x0);
1114 	emu10k_write_reg(devc, FXBA, 0, 0x0);
1115 	emu10k_write_reg(devc, ADCBS, 0, 0x0);
1116 	emu10k_write_reg(devc, ADCBA, 0, 0x0);
1117 
1118 	/* Ensure all interrupts are disabled */
1119 	OUTL(devc, 0, devc->regs + IE);
1120 	emu10k_write_reg(devc, CLIEL, 0, 0x0);
1121 	emu10k_write_reg(devc, CLIEH, 0, 0x0);
1122 	if (!(devc->feature_mask & SB_LIVE)) {
1123 		emu10k_write_reg(devc, HLIEL, 0, 0x0);
1124 		emu10k_write_reg(devc, HLIEH, 0, 0x0);
1125 	}
1126 	emu10k_write_reg(devc, CLIPL, 0, 0xffffffff);
1127 	emu10k_write_reg(devc, CLIPH, 0, 0xffffffff);
1128 	emu10k_write_reg(devc, SOLL, 0, 0xffffffff);
1129 	emu10k_write_reg(devc, SOLH, 0, 0xffffffff);
1130 
1131 
1132 	if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1133 		emu10k_write_reg(devc, SOC, 0, 0xf00);	/* ?? */
1134 		emu10k_write_reg(devc, AC97SLOT, 0, 0x3);	/* ?? */
1135 	}
1136 
1137 	for (i = 0; i < 64; i++)
1138 		emu10k_init_voice(devc, i);
1139 
1140 	emu10k_write_reg(devc, SCS0, 0, 0x2109204);
1141 	emu10k_write_reg(devc, SCS1, 0, 0x2109204);
1142 	emu10k_write_reg(devc, SCS2, 0, 0x2109204);
1143 
1144 	emu10k_write_reg(devc, PTBA, 0, devc->pt_paddr);
1145 	tmp = emu10k_read_reg(devc, PTBA, 0);
1146 
1147 	emu10k_write_reg(devc, TCBA, 0, 0x0);
1148 	emu10k_write_reg(devc, TCBS, 0, 0x4);
1149 
1150 	reg = 0;
1151 	if (devc->feature_mask & SB_71) {
1152 		reg = AC97SLOT_CENTER | AC97SLOT_LFE | AC97SLOT_REAR_LEFT |
1153 		    AC97SLOT_REAR_RIGHT;
1154 	} else if (devc->feature_mask & SB_51) {
1155 		reg = AC97SLOT_CENTER | AC97SLOT_LFE;
1156 	}
1157 	if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL))
1158 		reg |= 0x40;
1159 	emu10k_write_reg(devc, AC97SLOT, 0, reg);
1160 
1161 	if (devc->feature_mask & SB_AUDIGY2) {
1162 		/* Enable analog outputs on Audigy2 */
1163 		int tmp;
1164 
1165 		/* Setup SRCMulti_I2S SamplingRate */
1166 		tmp = emu10k_read_reg(devc, EHC, 0);
1167 		tmp &= 0xfffff1ff;
1168 		tmp |= (0x2 << 9);
1169 		emu10k_write_reg(devc, EHC, 0, tmp);
1170 		/* emu10k_write_reg (devc, SOC, 0, 0x00000000); */
1171 
1172 		/* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
1173 		OUTL(devc, 0x600000, devc->regs + 0x20);
1174 		OUTL(devc, 0x14, devc->regs + 0x24);
1175 
1176 		/* Setup SRCMulti Input Audio Enable */
1177 		OUTL(devc, 0x6E0000, devc->regs + 0x20);
1178 
1179 		OUTL(devc, 0xFF00FF00, devc->regs + 0x24);
1180 
1181 		/* Setup I2S ASRC Enable  (HC register) */
1182 		tmp = INL(devc, devc->regs + HCFG);
1183 		tmp |= 0x00000070;
1184 		OUTL(devc, tmp, devc->regs + HCFG);
1185 
1186 		/*
1187 		 * Unmute Analog now.  Set GPO6 to 1 for Apollo.
1188 		 * This has to be done after init ALice3 I2SOut beyond 48KHz.
1189 		 * So, sequence is important
1190 		 */
1191 		tmp = INL(devc, devc->regs + 0x18);
1192 		tmp |= 0x0040;
1193 
1194 		OUTL(devc, tmp, devc->regs + 0x18);
1195 	}
1196 
1197 	if (devc->feature_mask & SB_AUDIGY2VAL) {
1198 		/* Enable analog outputs on Audigy2 */
1199 		int tmp;
1200 
1201 		/* Setup SRCMulti_I2S SamplingRate */
1202 		tmp = emu10k_read_reg(devc, EHC, 0);
1203 		tmp &= 0xfffff1ff;
1204 		tmp |= (0x2 << 9);
1205 		emu10k_write_reg(devc, EHC, 0, tmp);
1206 
1207 		/* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
1208 		OUTL(devc, 0x600000, devc->regs + 0x20);
1209 		OUTL(devc, 0x14, devc->regs + 0x24);
1210 
1211 		/* Setup SRCMulti Input Audio Enable */
1212 		OUTL(devc, 0x7B0000, devc->regs + 0x20);
1213 		OUTL(devc, 0xFF000000, devc->regs + 0x24);
1214 
1215 		/* SPDIF output enable */
1216 		OUTL(devc, 0x7A0000, devc->regs + 0x20);
1217 		OUTL(devc, 0xFF000000, devc->regs + 0x24);
1218 
1219 		tmp = INL(devc, devc->regs + 0x18) & ~0x8;
1220 		OUTL(devc, tmp, devc->regs + 0x18);
1221 	}
1222 
1223 	emu10k_write_reg(devc, SOLL, 0, 0xffffffff);
1224 	emu10k_write_reg(devc, SOLH, 0, 0xffffffff);
1225 
1226 	if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1227 		unsigned int mode = 0;
1228 
1229 		if (devc->feature_mask & (SB_AUDIGY2|SB_AUDIGY2VAL))
1230 			mode |= HCFG_AC3ENABLE_GPSPDIF | HCFG_AC3ENABLE_CDSPDIF;
1231 		OUTL(devc,
1232 		    HCFG_AUDIOENABLE | HCFG_AUTOMUTE |
1233 		    HCFG_JOYENABLE | A_HCFG_VMUTE |
1234 		    A_HCFG_AUTOMUTE | mode, devc->regs + HCFG);
1235 
1236 		OUTL(devc, INL(devc, devc->regs + 0x18) |
1237 		    0x0004, devc->regs + 0x18);	/* GPIO (S/PDIF enable) */
1238 
1239 
1240 		/* enable IR port */
1241 		tmp = INL(devc, devc->regs + 0x18);
1242 		OUTL(devc, tmp | A_IOCFG_GPOUT2, devc->regs + 0x18);
1243 		drv_usecwait(500);
1244 		OUTL(devc, tmp | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2,
1245 		    devc->regs + 0x18);
1246 		drv_usecwait(100);
1247 		OUTL(devc, tmp, devc->regs + 0x18);
1248 	} else {
1249 		OUTL(devc,
1250 		    HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK |
1251 		    HCFG_AUTOMUTE | HCFG_JOYENABLE, devc->regs + HCFG);
1252 	}
1253 
1254 
1255 	/* enable IR port */
1256 	tmp = INL(devc, devc->regs + HCFG);
1257 	OUTL(devc, tmp | HCFG_GPOUT2, devc->regs + HCFG);
1258 	drv_usecwait(500);
1259 	OUTL(devc, tmp | HCFG_GPOUT1 | HCFG_GPOUT2, devc->regs + HCFG);
1260 	drv_usecwait(100);
1261 	OUTL(devc, tmp, devc->regs + HCFG);
1262 
1263 
1264 	/*
1265 	 * Start by configuring for analog mode.
1266 	 */
1267 	if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1268 		reg = INL(devc, devc->regs + 0x18) & ~A_IOCFG_GPOUT0;
1269 		reg |= ((devc->feature_mask & SB_INVSP) ? 0x4 : 0);
1270 		OUTL(devc, reg, devc->regs + 0x18);
1271 	}
1272 	if (devc->feature_mask & SB_LIVE) {	/* SBLIVE */
1273 		reg = INL(devc, devc->regs + HCFG) & ~HCFG_GPOUT0;
1274 		reg |= ((devc->feature_mask & SB_INVSP) ? HCFG_GPOUT0 : 0);
1275 		OUTL(devc, reg, devc->regs + HCFG);
1276 	}
1277 
1278 	if (devc->feature_mask & SB_AUDIGY2VAL) {
1279 		OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0060,
1280 		    devc->regs + 0x18);
1281 	} else if (devc->feature_mask & SB_AUDIGY2) {
1282 		OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0040,
1283 		    devc->regs + 0x18);
1284 	} else if (devc->feature_mask & SB_AUDIGY) {
1285 		OUTL(devc, INL(devc, devc->regs + 0x18) | 0x0080,
1286 		    devc->regs + 0x18);
1287 	}
1288 
1289 	emu10k_init_effects(devc);
1290 
1291 	return (DDI_SUCCESS);
1292 }
1293 
1294 static const int db2lin_101[101] = {
1295 	0x00000000,
1296 	0x0024B53A, 0x002750CA, 0x002A1BC6, 0x002D198D, 0x00304DBA, 0x0033BC2A,
1297 	0x00376901, 0x003B58AF, 0x003F8FF1, 0x004413DF, 0x0048E9EA, 0x004E17E9,
1298 	0x0053A419, 0x0059952C, 0x005FF24E, 0x0066C32A, 0x006E0FFB, 0x0075E18D,
1299 	0x007E414F, 0x0087395B, 0x0090D482, 0x009B1E5B, 0x00A6234F, 0x00B1F0A7,
1300 	0x00BE94A1, 0x00CC1E7C, 0x00DA9E8D, 0x00EA2650, 0x00FAC881, 0x010C9931,
1301 	0x011FADDC, 0x01341D87, 0x014A00D8, 0x01617235, 0x017A8DE6, 0x01957233,
1302 	0x01B23F8D, 0x01D118B1, 0x01F222D4, 0x021585D1, 0x023B6C57, 0x0264041D,
1303 	0x028F7E19, 0x02BE0EBD, 0x02EFEE33, 0x032558A2, 0x035E8E7A, 0x039BD4BC,
1304 	0x03DD7551, 0x0423BF61, 0x046F07B5, 0x04BFA91B, 0x051604D5, 0x0572830D,
1305 	0x05D59354, 0x063FAD27, 0x06B15080, 0x072B0673, 0x07AD61CD, 0x0838FFCA,
1306 	0x08CE88D3, 0x096EB147, 0x0A1A3A53, 0x0AD1F2E0, 0x0B96B889, 0x0C6978A5,
1307 	0x0D4B316A, 0x0E3CF31B, 0x0F3FE155, 0x10553469, 0x117E3AD9, 0x12BC5AEA,
1308 	0x14111457, 0x157E0219, 0x1704DC5E, 0x18A77A97, 0x1A67D5B6, 0x1C480A87,
1309 	0x1E4A5C45, 0x2071374D, 0x22BF3412, 0x25371A37, 0x27DBE3EF, 0x2AB0C18F,
1310 	0x2DB91D6F, 0x30F89FFD, 0x34733433, 0x382D0C46, 0x3C2AA6BD, 0x4070D3D9,
1311 	0x4504BB66, 0x49EBE2F1, 0x4F2C346F, 0x54CC0565, 0x5AD21E86, 0x6145C3E7,
1312 	0x682EBDBD, 0x6F9561C4, 0x77829D4D,
1313 	0x7fffffff
1314 };
1315 
1316 static int
emu10k_convert_fixpoint(int val)1317 emu10k_convert_fixpoint(int val)
1318 {
1319 	if (val < 0)
1320 		val = 0;
1321 	if (val > 100)
1322 		val = 100;
1323 	return (db2lin_101[val]);
1324 }
1325 
1326 static void
emu10k_write_gpr(emu10k_devc_t * devc,int gpr,uint32_t value)1327 emu10k_write_gpr(emu10k_devc_t *devc, int gpr, uint32_t value)
1328 {
1329 	ASSERT(gpr < MAX_GPR);
1330 	devc->gpr_shadow[gpr].valid = B_TRUE;
1331 	devc->gpr_shadow[gpr].value = value;
1332 	emu10k_write_reg(devc, gpr + GPR0, 0, value);
1333 }
1334 
1335 static int
emu10k_set_stereo(void * arg,uint64_t val)1336 emu10k_set_stereo(void *arg, uint64_t val)
1337 {
1338 	emu10k_ctrl_t *ec = arg;
1339 	emu10k_devc_t *devc = ec->devc;
1340 	uint32_t left, right;
1341 
1342 	left = (val >> 8) & 0xff;
1343 	right = val & 0xff;
1344 	if ((left > 100) || (right > 100) || (val & ~(0xffff)))
1345 		return (EINVAL);
1346 
1347 	left = emu10k_convert_fixpoint(left);
1348 	right = emu10k_convert_fixpoint(right);
1349 
1350 	mutex_enter(&devc->mutex);
1351 	ec->val = val;
1352 
1353 	emu10k_write_gpr(devc, ec->gpr_num, left);
1354 	emu10k_write_gpr(devc, ec->gpr_num + 1, right);
1355 
1356 	mutex_exit(&devc->mutex);
1357 	return (0);
1358 }
1359 
1360 static int
emu10k_set_mono(void * arg,uint64_t val)1361 emu10k_set_mono(void *arg, uint64_t val)
1362 {
1363 	emu10k_ctrl_t *ec = arg;
1364 	emu10k_devc_t *devc = ec->devc;
1365 	uint32_t v;
1366 
1367 	if (val > 100)
1368 		return (EINVAL);
1369 
1370 	v = emu10k_convert_fixpoint(val & 0xff);
1371 
1372 	mutex_enter(&devc->mutex);
1373 	ec->val = val;
1374 	emu10k_write_gpr(devc, ec->gpr_num, v);
1375 	mutex_exit(&devc->mutex);
1376 	return (0);
1377 }
1378 
1379 static int
emu10k_get_control(void * arg,uint64_t * val)1380 emu10k_get_control(void *arg, uint64_t *val)
1381 {
1382 	emu10k_ctrl_t *ec = arg;
1383 	emu10k_devc_t *devc = ec->devc;
1384 
1385 	mutex_enter(&devc->mutex);
1386 	*val = ec->val;
1387 	mutex_exit(&devc->mutex);
1388 	return (0);
1389 }
1390 
1391 #define	PLAYCTL	(AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_PLAY)
1392 #define	RECCTL	(AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_REC)
1393 #define	MONCTL	(AUDIO_CTRL_FLAG_RW | AUDIO_CTRL_FLAG_MONITOR)
1394 #define	MAINVOL	(PLAYCTL | AUDIO_CTRL_FLAG_MAINVOL)
1395 #define	PCMVOL	(PLAYCTL | AUDIO_CTRL_FLAG_PCMVOL)
1396 #define	RECVOL	(RECCTL | AUDIO_CTRL_FLAG_RECVOL)
1397 #define	MONVOL	(MONCTL | AUDIO_CTRL_FLAG_MONVOL)
1398 
1399 static int
emu10k_get_ac97src(void * arg,uint64_t * valp)1400 emu10k_get_ac97src(void *arg, uint64_t *valp)
1401 {
1402 	ac97_ctrl_t *ctrl = arg;
1403 
1404 	return (ac97_control_get(ctrl, valp));
1405 }
1406 
1407 static int
emu10k_set_ac97src(void * arg,uint64_t value)1408 emu10k_set_ac97src(void *arg, uint64_t value)
1409 {
1410 	ac97_ctrl_t	*ctrl = arg;
1411 
1412 	return (ac97_control_set(ctrl, value));
1413 }
1414 
1415 static int
emu10k_set_jack3(void * arg,uint64_t value)1416 emu10k_set_jack3(void *arg, uint64_t value)
1417 {
1418 	emu10k_ctrl_t	*ec = arg;
1419 	emu10k_devc_t	*devc = ec->devc;
1420 	uint32_t	set_val;
1421 	uint32_t	val;
1422 
1423 	set_val = ddi_ffs(value & 0xffffffffU);
1424 	set_val--;
1425 	mutex_enter(&devc->mutex);
1426 	switch (set_val) {
1427 	case 0:
1428 	case 1:
1429 		break;
1430 	default:
1431 		mutex_exit(&devc->mutex);
1432 		return (EINVAL);
1433 	}
1434 	ec->val = value;
1435 	/* center/lfe */
1436 	if (devc->feature_mask & SB_INVSP) {
1437 		set_val = !set_val;
1438 	}
1439 	if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1440 		val = INL(devc, devc->regs + 0x18);
1441 		val &= ~A_IOCFG_GPOUT0;
1442 		val |= set_val ? 0x44 : 0x40;
1443 		OUTL(devc, val, devc->regs + 0x18);
1444 
1445 	} else if (devc->feature_mask & SB_LIVE) {
1446 		val = INL(devc, devc->regs + HCFG);
1447 		val &= ~HCFG_GPOUT0;
1448 		val |= set_val ? HCFG_GPOUT0 : 0;
1449 		OUTL(devc, val, devc->regs + HCFG);
1450 	}
1451 	mutex_exit(&devc->mutex);
1452 	return (0);
1453 }
1454 
1455 static int
emu10k_set_recsrc(void * arg,uint64_t value)1456 emu10k_set_recsrc(void *arg, uint64_t value)
1457 {
1458 	emu10k_ctrl_t	*ec = arg;
1459 	emu10k_devc_t	*devc = ec->devc;
1460 	uint32_t	set_val;
1461 
1462 	set_val = ddi_ffs(value & 0xffffffffU);
1463 	set_val--;
1464 
1465 	/*
1466 	 * We start assuming well set up AC'97 for stereomix recording.
1467 	 */
1468 	switch (set_val) {
1469 	case INPUT_AC97:
1470 	case INPUT_SPD1:
1471 	case INPUT_SPD2:
1472 	case INPUT_DIGCD:
1473 	case INPUT_AUX2:
1474 	case INPUT_LINE2:
1475 	case INPUT_STEREOMIX:
1476 		break;
1477 	default:
1478 		return (EINVAL);
1479 	}
1480 
1481 	mutex_enter(&devc->mutex);
1482 	ec->val = value;
1483 
1484 	emu10k_write_gpr(devc, GPR_REC_AC97, (set_val == INPUT_AC97));
1485 	emu10k_write_gpr(devc, GPR_REC_SPDIF1, (set_val == INPUT_SPD1));
1486 	emu10k_write_gpr(devc, GPR_REC_SPDIF2, (set_val == INPUT_SPD2));
1487 	emu10k_write_gpr(devc, GPR_REC_DIGCD, (set_val == INPUT_DIGCD));
1488 	emu10k_write_gpr(devc, GPR_REC_AUX2, (set_val == INPUT_AUX2));
1489 	emu10k_write_gpr(devc, GPR_REC_LINE2, (set_val == INPUT_LINE2));
1490 	emu10k_write_gpr(devc, GPR_REC_PCM, (set_val == INPUT_STEREOMIX));
1491 
1492 	mutex_exit(&devc->mutex);
1493 
1494 	return (0);
1495 }
1496 
1497 static void
emu10k_create_stereo(emu10k_devc_t * devc,int ctl,int gpr,const char * id,int flags,int defval)1498 emu10k_create_stereo(emu10k_devc_t *devc, int ctl, int gpr,
1499     const char *id, int flags, int defval)
1500 {
1501 	emu10k_ctrl_t *ec;
1502 	audio_ctrl_desc_t desc;
1503 
1504 	bzero(&desc, sizeof (desc));
1505 
1506 	ec = &devc->ctrls[ctl];
1507 	ec->devc = devc;
1508 	ec->gpr_num = gpr;
1509 
1510 	desc.acd_name = id;
1511 	desc.acd_type = AUDIO_CTRL_TYPE_STEREO;
1512 	desc.acd_minvalue = 0;
1513 	desc.acd_maxvalue = 100;
1514 	desc.acd_flags = flags;
1515 
1516 	ec->val = (defval << 8) | defval;
1517 	ec->ctrl = audio_dev_add_control(devc->adev, &desc,
1518 	    emu10k_get_control, emu10k_set_stereo, ec);
1519 
1520 	mutex_enter(&devc->mutex);
1521 	emu10k_write_gpr(devc, gpr, emu10k_convert_fixpoint(defval));
1522 	emu10k_write_gpr(devc, gpr + 1, emu10k_convert_fixpoint(defval));
1523 	mutex_exit(&devc->mutex);
1524 }
1525 
1526 static void
emu10k_create_mono(emu10k_devc_t * devc,int ctl,int gpr,const char * id,int flags,int defval)1527 emu10k_create_mono(emu10k_devc_t *devc, int ctl, int gpr,
1528     const char *id, int flags, int defval)
1529 {
1530 	emu10k_ctrl_t *ec;
1531 	audio_ctrl_desc_t desc;
1532 
1533 	bzero(&desc, sizeof (desc));
1534 
1535 	ec = &devc->ctrls[ctl];
1536 	ec->devc = devc;
1537 	ec->gpr_num = gpr;
1538 
1539 	desc.acd_name = id;
1540 	desc.acd_type = AUDIO_CTRL_TYPE_MONO;
1541 	desc.acd_minvalue = 0;
1542 	desc.acd_maxvalue = 100;
1543 	desc.acd_flags = flags;
1544 
1545 	ec->val = defval;
1546 	ec->ctrl = audio_dev_add_control(devc->adev, &desc,
1547 	    emu10k_get_control, emu10k_set_mono, ec);
1548 
1549 	mutex_enter(&devc->mutex);
1550 	emu10k_write_gpr(devc, gpr, emu10k_convert_fixpoint(defval));
1551 	mutex_exit(&devc->mutex);
1552 }
1553 
1554 /*
1555  * AC'97 source.  The AC'97 PCM record channel is routed to our
1556  * mixer.  While we could support the direct monitoring capability of
1557  * the AC'97 part itself, this would not work correctly with outputs
1558  * that are not routed via AC'97 (such as the Live Drive headphones
1559  * or digital outputs.)  So we just offer the ability to select one
1560  * AC'97 source, and then offer independent ability to either monitor
1561  * or record from the AC'97 mixer's PCM record channel.
1562  */
1563 static void
emu10k_create_ac97src(emu10k_devc_t * devc)1564 emu10k_create_ac97src(emu10k_devc_t *devc)
1565 {
1566 	emu10k_ctrl_t *ec;
1567 	audio_ctrl_desc_t desc;
1568 	ac97_ctrl_t *ac;
1569 	const audio_ctrl_desc_t *acd;
1570 
1571 	bzero(&desc, sizeof (desc));
1572 
1573 	ec = &devc->ctrls[CTL_AC97SRC];
1574 	desc.acd_name = "ac97-source";
1575 	desc.acd_type = AUDIO_CTRL_TYPE_ENUM;
1576 	desc.acd_flags = RECCTL;
1577 	ec->devc = devc;
1578 	ac = ac97_control_find(devc->ac97, AUDIO_CTRL_ID_RECSRC);
1579 	if (ac == NULL) {
1580 		return;
1581 	}
1582 
1583 	acd = ac97_control_desc(ac);
1584 
1585 	for (int i = 0; i < 64; i++) {
1586 		const char *n;
1587 		if (((acd->acd_minvalue & (1ULL << i)) == 0) ||
1588 		    ((n = acd->acd_enum[i]) == NULL)) {
1589 			continue;
1590 		}
1591 		desc.acd_enum[i] = acd->acd_enum[i];
1592 		/* we suppress some port options */
1593 		if ((strcmp(n, AUDIO_PORT_STEREOMIX) == 0) ||
1594 		    (strcmp(n, AUDIO_PORT_MONOMIX) == 0) ||
1595 		    (strcmp(n, AUDIO_PORT_VIDEO) == 0)) {
1596 			continue;
1597 		}
1598 		desc.acd_minvalue |= (1ULL << i);
1599 		desc.acd_maxvalue |= (1ULL << i);
1600 	}
1601 
1602 	ec->ctrl = audio_dev_add_control(devc->adev, &desc,
1603 	    emu10k_get_ac97src, emu10k_set_ac97src, ac);
1604 }
1605 
1606 /*
1607  * Record source... this one is tricky.  While the chip will
1608  * conceivably let us *mix* some of the audio streams for recording,
1609  * the AC'97 inputs don't have this capability.  Offering it to users
1610  * is likely to be confusing, so we offer a single record source
1611  * selection option.  Its not ideal, but it ought to be good enough
1612  * for the vast majority of users.
1613  */
1614 static void
emu10k_create_recsrc(emu10k_devc_t * devc)1615 emu10k_create_recsrc(emu10k_devc_t *devc)
1616 {
1617 	emu10k_ctrl_t *ec;
1618 	audio_ctrl_desc_t desc;
1619 	ac97_ctrl_t *ac;
1620 
1621 	bzero(&desc, sizeof (desc));
1622 
1623 	ec = &devc->ctrls[CTL_RECSRC];
1624 	desc.acd_name = AUDIO_CTRL_ID_RECSRC;
1625 	desc.acd_type = AUDIO_CTRL_TYPE_ENUM;
1626 	desc.acd_flags = RECCTL;
1627 	desc.acd_minvalue = 0;
1628 	desc.acd_maxvalue = 0;
1629 	bzero(desc.acd_enum, sizeof (desc.acd_enum));
1630 	ec->devc = devc;
1631 	ac = ac97_control_find(devc->ac97, AUDIO_CTRL_ID_RECSRC);
1632 
1633 	/* only low order bits set by AC'97 */
1634 	ASSERT(desc.acd_minvalue == desc.acd_maxvalue);
1635 	ASSERT((desc.acd_minvalue & ~0xffff) == 0);
1636 
1637 	/*
1638 	 * It would be really cool if we could detect whether these
1639 	 * options are all sensible on a given configuration.  Units
1640 	 * without live-drive support, and units without a physical
1641 	 * live-drive, simply can't do all these.
1642 	 */
1643 	if (ac != NULL) {
1644 		desc.acd_minvalue |= (1 << INPUT_AC97);
1645 		desc.acd_maxvalue |= (1 << INPUT_AC97);
1646 		desc.acd_enum[INPUT_AC97] = "ac97";
1647 		ec->val = (1 << INPUT_AC97);
1648 	} else {
1649 		/* next best guess */
1650 		ec->val = (1 << INPUT_LINE2);
1651 	}
1652 
1653 	desc.acd_minvalue |= (1 << INPUT_SPD1);
1654 	desc.acd_maxvalue |= (1 << INPUT_SPD1);
1655 	desc.acd_enum[INPUT_SPD1] = AUDIO_PORT_SPDIFIN;
1656 
1657 	desc.acd_minvalue |= (1 << INPUT_SPD2);
1658 	desc.acd_maxvalue |= (1 << INPUT_SPD2);
1659 	desc.acd_enum[INPUT_SPD2] = "spdif2-in";
1660 
1661 	desc.acd_minvalue |= (1 << INPUT_DIGCD);
1662 	desc.acd_maxvalue |= (1 << INPUT_DIGCD);
1663 	desc.acd_enum[INPUT_DIGCD] = "digital-cd";
1664 
1665 	desc.acd_minvalue |= (1 << INPUT_AUX2);
1666 	desc.acd_maxvalue |= (1 << INPUT_AUX2);
1667 	desc.acd_enum[INPUT_AUX2] = AUDIO_PORT_AUX2IN;
1668 
1669 	desc.acd_minvalue |= (1 << INPUT_LINE2);
1670 	desc.acd_maxvalue |= (1 << INPUT_LINE2);
1671 	desc.acd_enum[INPUT_LINE2] = "line2-in";
1672 
1673 	desc.acd_minvalue |= (1 << INPUT_STEREOMIX);
1674 	desc.acd_maxvalue |= (1 << INPUT_STEREOMIX);
1675 	desc.acd_enum[INPUT_STEREOMIX] = AUDIO_PORT_STEREOMIX;
1676 
1677 	emu10k_write_gpr(devc, GPR_REC_SPDIF1, 0);
1678 	emu10k_write_gpr(devc, GPR_REC_SPDIF2, 0);
1679 	emu10k_write_gpr(devc, GPR_REC_DIGCD, 0);
1680 	emu10k_write_gpr(devc, GPR_REC_AUX2, 0);
1681 	emu10k_write_gpr(devc, GPR_REC_LINE2, 0);
1682 	emu10k_write_gpr(devc, GPR_REC_PCM, 0);
1683 	emu10k_write_gpr(devc, GPR_REC_AC97, 1);
1684 
1685 	ec->ctrl = audio_dev_add_control(devc->adev, &desc,
1686 	    emu10k_get_control, emu10k_set_recsrc, ec);
1687 }
1688 
1689 static void
emu10k_create_jack3(emu10k_devc_t * devc)1690 emu10k_create_jack3(emu10k_devc_t *devc)
1691 {
1692 	emu10k_ctrl_t *ec;
1693 	audio_ctrl_desc_t desc;
1694 
1695 	bzero(&desc, sizeof (desc));
1696 
1697 	ec = &devc->ctrls[CTL_JACK3];
1698 	desc.acd_name = AUDIO_CTRL_ID_JACK3;
1699 	desc.acd_type = AUDIO_CTRL_TYPE_ENUM;
1700 	desc.acd_flags = AUDIO_CTRL_FLAG_RW;
1701 	desc.acd_minvalue = 0x3;
1702 	desc.acd_maxvalue = 0x3;
1703 	bzero(desc.acd_enum, sizeof (desc.acd_enum));
1704 	ec->devc = devc;
1705 	ec->val = 0x1;
1706 
1707 	desc.acd_enum[0] = AUDIO_PORT_CENLFE;
1708 	desc.acd_enum[1] = AUDIO_PORT_SPDIFOUT;
1709 
1710 	ec->ctrl = audio_dev_add_control(devc->adev, &desc,
1711 	    emu10k_get_control, emu10k_set_jack3, ec);
1712 }
1713 
1714 
1715 static void
emu10k_create_controls(emu10k_devc_t * devc)1716 emu10k_create_controls(emu10k_devc_t *devc)
1717 {
1718 	ac97_t		*ac97;
1719 	ac97_ctrl_t	*ac;
1720 
1721 	emu10k_create_mono(devc, CTL_VOLUME, GPR_VOL_PCM,
1722 	    AUDIO_CTRL_ID_VOLUME, PCMVOL, 75);
1723 
1724 	emu10k_create_stereo(devc, CTL_FRONT, GPR_VOL_FRONT,
1725 	    AUDIO_CTRL_ID_FRONT, MAINVOL, 100);
1726 	emu10k_create_stereo(devc, CTL_SURROUND, GPR_VOL_SURR,
1727 	    AUDIO_CTRL_ID_SURROUND, MAINVOL, 100);
1728 	if (devc->feature_mask & (SB_51 | SB_71)) {
1729 		emu10k_create_mono(devc, CTL_CENTER, GPR_VOL_CEN,
1730 		    AUDIO_CTRL_ID_CENTER, MAINVOL, 100);
1731 		emu10k_create_mono(devc, CTL_LFE, GPR_VOL_LFE,
1732 		    AUDIO_CTRL_ID_LFE, MAINVOL, 100);
1733 	}
1734 	if (devc->feature_mask & SB_71) {
1735 		emu10k_create_stereo(devc, CTL_SIDE, GPR_VOL_SIDE,
1736 		    "side", MAINVOL, 100);
1737 	}
1738 
1739 	emu10k_create_stereo(devc, CTL_RECGAIN, GPR_VOL_REC,
1740 	    AUDIO_CTRL_ID_RECGAIN, RECVOL, 50);
1741 
1742 	emu10k_create_ac97src(devc);
1743 	emu10k_create_recsrc(devc);
1744 	/*
1745 	 * 5.1 devices have versa jack.  Note that from what we can
1746 	 * tell, none of the 7.1 devices have or need this versa jack,
1747 	 * as they all seem to have a dedicated digital I/O port.
1748 	 */
1749 	if ((devc->feature_mask & SB_51) &&
1750 	    !(devc->feature_mask & SB_AUDIGY2VAL)) {
1751 		emu10k_create_jack3(devc);
1752 	}
1753 
1754 	/* these ones AC'97 can manage directly */
1755 	ac97 = devc->ac97;
1756 
1757 	if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_MICBOOST)) != NULL)
1758 		ac97_control_register(ac);
1759 	if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_MICGAIN)) != NULL)
1760 		ac97_control_register(ac);
1761 
1762 	/* set any AC'97 analog outputs to full volume (no attenuation) */
1763 	if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_FRONT)) != NULL)
1764 		(void) ac97_control_set(ac, (100 << 8) | 100);
1765 	if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_LINEOUT)) != NULL)
1766 		(void) ac97_control_set(ac, (100 << 8) | 100);
1767 	if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_SURROUND)) != NULL)
1768 		(void) ac97_control_set(ac, (100 << 8) | 100);
1769 	if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_CENTER)) != NULL)
1770 		(void) ac97_control_set(ac, 100);
1771 	if ((ac = ac97_control_find(ac97, AUDIO_CTRL_ID_LFE)) != NULL)
1772 		(void) ac97_control_set(ac, 100);
1773 
1774 	/* Monitor sources */
1775 	emu10k_create_stereo(devc, CTL_AC97, GPR_MON_AC97,
1776 	    "ac97-monitor", MONVOL, 0);
1777 	emu10k_create_stereo(devc, CTL_SPD1, GPR_MON_SPDIF1,
1778 	    AUDIO_PORT_SPDIFIN, MONVOL, 0);
1779 	emu10k_create_stereo(devc, CTL_DIGCD, GPR_MON_DIGCD,
1780 	    "digital-cd", MONVOL, 0);
1781 	emu10k_create_stereo(devc, CTL_SPD1, GPR_MON_SPDIF1,
1782 	    AUDIO_PORT_SPDIFIN, MONVOL, 0);
1783 
1784 	if ((devc->feature_mask & SB_NOEXP) == 0) {
1785 		/*
1786 		 * These ports are only available via an external
1787 		 * expansion box.  Don't expose them for cards  that
1788 		 * don't have support for it.
1789 		 */
1790 		emu10k_create_stereo(devc, CTL_HEADPH, GPR_VOL_HEADPH,
1791 		    AUDIO_CTRL_ID_HEADPHONE, MAINVOL, 100);
1792 		emu10k_create_stereo(devc, CTL_SPD2, GPR_MON_SPDIF2,
1793 		    "spdif2-in", MONVOL, 0);
1794 		emu10k_create_stereo(devc, CTL_LINE2, GPR_MON_LINE2,
1795 		    "line2-in", MONVOL, 0);
1796 		emu10k_create_stereo(devc, CTL_AUX2, GPR_MON_AUX2,
1797 		    AUDIO_PORT_AUX2IN, MONVOL, 0);
1798 	}
1799 }
1800 
1801 static void
emu10k_load_dsp(emu10k_devc_t * devc,uint32_t * code,int ncode,uint32_t * init,int ninit)1802 emu10k_load_dsp(emu10k_devc_t *devc, uint32_t *code, int ncode,
1803     uint32_t *init, int ninit)
1804 {
1805 	int i;
1806 
1807 	if (ncode > 1024) {
1808 		audio_dev_warn(devc->adev, "DSP file size too big");
1809 		return;
1810 	}
1811 	if (ninit > MAX_GPR) {
1812 		audio_dev_warn(devc->adev, "Too many inits");
1813 		return;
1814 	}
1815 
1816 	/* Upload our DSP code */
1817 	for (i = 0; i < ncode; i++) {
1818 		emu10k_write_efx(devc, UC0 + i, code[i]);
1819 	}
1820 
1821 	/* Upload the initialization settings */
1822 	for (i = 0; i < ninit; i += 2) {
1823 		emu10k_write_reg(devc, init[i] + GPR0, 0, init[i + 1]);
1824 	}
1825 }
1826 
1827 #define	LIVE_NOP()					\
1828 	emu10k_write_efx(devc, UC0 + (pc * 2), 0x10040);	\
1829 	emu10k_write_efx(devc, UC0 + (pc * 2 + 1), 0x610040);	\
1830 	pc++
1831 #define	LIVE_ACC3(r, a, x, y) /* z=w+x+y */				\
1832 	emu10k_write_efx(devc, UC0 + (pc * 2), (x << 10) | y);		\
1833 	emu10k_write_efx(devc, UC0 + (pc * 2 + 1), (6 << 20) | (r << 10) | a); \
1834 	pc++
1835 
1836 #define	AUDIGY_ACC3(r, a, x, y) /* z=w+x+y */				\
1837 	emu10k_write_efx(devc, UC0 + (pc * 2), (x << 12) | y);		\
1838 	emu10k_write_efx(devc, UC0 + (pc * 2+1), (6 << 24) | (r << 12) | a); \
1839 	pc++
1840 #define	AUDIGY_NOP() AUDIGY_ACC3(0xc0, 0xc0, 0xc0, 0xc0)
1841 
1842 static void
emu10k_init_effects(emu10k_devc_t * devc)1843 emu10k_init_effects(emu10k_devc_t *devc)
1844 {
1845 	int i;
1846 	unsigned short pc;
1847 
1848 	ASSERT(mutex_owned(&devc->mutex));
1849 
1850 	if (devc->feature_mask & (SB_AUDIGY|SB_AUDIGY2|SB_AUDIGY2VAL)) {
1851 		pc = 0;
1852 		for (i = 0; i < 512; i++) {
1853 			AUDIGY_NOP();
1854 		}
1855 
1856 		for (i = 0; i < 256; i++)
1857 			emu10k_write_efx(devc, GPR0 + i, 0);
1858 		emu10k_write_reg(devc, AUDIGY_DBG, 0, 0);
1859 		emu10k_load_dsp(devc,
1860 		    emu10k2_code,
1861 		    sizeof (emu10k2_code) / sizeof (emu10k2_code[0]),
1862 		    emu10k2_init,
1863 		    sizeof (emu10k2_init) / sizeof (emu10k2_init[0]));
1864 
1865 	} else {
1866 		pc = 0;
1867 		for (i = 0; i < 512; i++) {
1868 			LIVE_NOP();
1869 		}
1870 
1871 		for (i = 0; i < 256; i++)
1872 			emu10k_write_efx(devc, GPR0 + i, 0);
1873 		emu10k_write_reg(devc, DBG, 0, 0);
1874 		emu10k_load_dsp(devc,
1875 		    emu10k1_code,
1876 		    sizeof (emu10k1_code) / sizeof (emu10k1_code[0]),
1877 		    emu10k1_init,
1878 		    sizeof (emu10k1_init) / sizeof (emu10k1_init[0]));
1879 	}
1880 }
1881 
1882 /* mixer */
1883 
1884 static struct {
1885 	uint16_t	devid;
1886 	uint16_t	subid;
1887 	const char	*model;
1888 	const char	*prod;
1889 	unsigned	feature_mask;
1890 } emu10k_cards[] = {
1891 	{ 0x2, 0x0020, "CT4670", "Live! Value", SB_LIVE | SB_NOEXP },
1892 	{ 0x2, 0x0021, "CT4621", "Live!", SB_LIVE },
1893 	{ 0x2, 0x100a, "SB0220", "Live! 5.1 Digital",
1894 	    SB_LIVE | SB_51 | SB_NOEXP },
1895 	{ 0x2, 0x8022, "CT4780", "Live! Value", SB_LIVE },
1896 	{ 0x2, 0x8023, "CT4790", "PCI512", SB_LIVE | SB_NOEXP },
1897 	{ 0x2, 0x8026, "CT4830", "Live! Value", SB_LIVE },
1898 	{ 0x2, 0x8028, "CT4870", "Live! Value", SB_LIVE },
1899 	{ 0x2, 0x8031, "CT4831", "Live! Value", SB_LIVE },
1900 	{ 0x2, 0x8040, "CT4760", "Live!", SB_LIVE },
1901 	{ 0x2, 0x8051, "CT4850", "Live! Value", SB_LIVE },
1902 	{ 0x2, 0x8061, "SB0060", "Live! 5.1", SB_LIVE | SB_51 },
1903 	{ 0x2, 0x8064, "SB0100", "Live! 5.1", SB_LIVE | SB_51 },
1904 	{ 0x2, 0x8065, "SB0220", "Live! 5.1", SB_LIVE | SB_51 },
1905 	{ 0x2, 0x8066, "SB0228", "Live! 5.1", SB_LIVE | SB_51 },
1906 	{ 0x4, 0x0051, "SB0090", "Audigy", SB_AUDIGY | SB_51 },
1907 	{ 0x4, 0x0052, "SB0160", "Audigy ES", SB_AUDIGY | SB_51 },
1908 	{ 0x4, 0x0053, "SB0092", "Audigy", SB_AUDIGY | SB_51 },
1909 	{ 0x4, 0x1002, "SB0240P", "Audigy 2 Platinum",
1910 	    SB_AUDIGY2 | SB_71 | SB_INVSP },
1911 	{ 0x4, 0x1003, "SB0353", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP },
1912 	{ 0x4, 0x1005, "SB0280", "Audigy 2 Platinum EX", SB_AUDIGY2 | SB_71 },
1913 	{ 0x4, 0x1007, "SB0240", "Audigy 2", SB_AUDIGY2 | SB_71 },
1914 	{ 0x4, 0x2001, "SB0360", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP },
1915 	{ 0x4, 0x2002, "SB0350", "Audigy 2 ZS", SB_AUDIGY2 | SB_71 | SB_INVSP },
1916 	{ 0x4, 0x2006, "SB0350", "Audigy 2", SB_AUDIGY2 | SB_71 | SB_INVSP },
1917 	{ 0x4, 0x2007, "SB0380", "Audigy 4 Pro", SB_AUDIGY2 | SB_71 },
1918 	{ 0x8, 0x1001, "SB0400", "Audigy 2 Value",
1919 	    SB_AUDIGY2VAL | SB_71 | SB_NOEXP },
1920 	{ 0x8, 0x1021, "SB0610", "Audigy 4",
1921 	    SB_AUDIGY2VAL | SB_71 | SB_NOEXP },
1922 	{ 0x8, 0x1024, "SB1550", "Audigy RX",
1923 	    SB_AUDIGY2VAL | SB_71 | SB_NOEXP },
1924 	{ 0x8, 0x2001, "SB0530", "Audigy 2 ZS Notebook",
1925 	    SB_AUDIGY2VAL | SB_71 },
1926 	{ 0, 0, NULL, NULL, 0 },
1927 };
1928 
1929 int
emu10k_attach(dev_info_t * dip)1930 emu10k_attach(dev_info_t *dip)
1931 {
1932 	uint16_t pci_command;
1933 	uint16_t subid;
1934 	uint16_t devid;
1935 	emu10k_devc_t *devc;
1936 	ddi_acc_handle_t pcih;
1937 	ddi_dma_cookie_t cookie;
1938 	uint_t count;
1939 	ulong_t len;
1940 	int i;
1941 	const char *name;
1942 	const char *model;
1943 	char namebuf[64];
1944 	int feature_mask;
1945 
1946 	devc = kmem_zalloc(sizeof (*devc), KM_SLEEP);
1947 	devc->dip = dip;
1948 	ddi_set_driver_private(dip, devc);
1949 
1950 	if ((devc->adev = audio_dev_alloc(dip, 0)) == NULL) {
1951 		cmn_err(CE_WARN, "audio_dev_alloc failed");
1952 		goto error;
1953 	}
1954 
1955 	if (pci_config_setup(dip, &pcih) != DDI_SUCCESS) {
1956 		audio_dev_warn(devc->adev, "pci_config_setup failed");
1957 		goto error;
1958 	}
1959 	devc->pcih = pcih;
1960 
1961 	devid = pci_config_get16(pcih, PCI_CONF_DEVID);
1962 	subid = pci_config_get16(pcih, PCI_CONF_SUBSYSID);
1963 
1964 	pci_command = pci_config_get16(pcih, PCI_CONF_COMM);
1965 	pci_command |= PCI_COMM_ME | PCI_COMM_IO;
1966 	pci_config_put16(pcih, PCI_CONF_COMM, pci_command);
1967 
1968 	if ((ddi_regs_map_setup(dip, 1, &devc->regs, 0, 0, &dev_attr,
1969 	    &devc->regsh)) != DDI_SUCCESS) {
1970 		audio_dev_warn(devc->adev, "failed to map registers");
1971 		goto error;
1972 	}
1973 
1974 	switch (devid) {
1975 	case PCI_DEVICE_ID_SBLIVE:
1976 		name = "Live!";
1977 		model = "CT????";
1978 		feature_mask = SB_LIVE;
1979 		break;
1980 
1981 	case PCI_DEVICE_ID_AUDIGYVALUE:
1982 		name = "Audigy 2 Value";
1983 		model = "SB????";
1984 		feature_mask = SB_AUDIGY2VAL;
1985 		break;
1986 
1987 	case PCI_DEVICE_ID_AUDIGY:
1988 		if (subid >= 0x1002 && subid <= 0x2005) {
1989 			name = "Audigy 2";
1990 			model = "SB????";
1991 			feature_mask = SB_AUDIGY2;
1992 		} else {
1993 			name = "Audigy";
1994 			model = "SB????";
1995 			feature_mask = SB_AUDIGY;
1996 		}
1997 		break;
1998 
1999 	default:
2000 		audio_dev_warn(devc->adev, "Unrecognized device");
2001 		goto error;
2002 	}
2003 
2004 	for (i = 0; emu10k_cards[i].prod; i++) {
2005 		if ((devid == emu10k_cards[i].devid) &&
2006 		    (subid == emu10k_cards[i].subid)) {
2007 			name = emu10k_cards[i].prod;
2008 			model = emu10k_cards[i].model;
2009 			feature_mask = emu10k_cards[i].feature_mask;
2010 			break;
2011 		}
2012 	}
2013 	devc->feature_mask = feature_mask;
2014 
2015 	(void) snprintf(namebuf, sizeof (namebuf), "Sound Blaster %s", name);
2016 
2017 	audio_dev_set_description(devc->adev, namebuf);
2018 	audio_dev_set_version(devc->adev, model);
2019 
2020 	mutex_init(&devc->mutex, NULL, MUTEX_DRIVER, 0);
2021 
2022 	/* allocate static page table memory */
2023 
2024 	devc->max_mem = AUDIO_MEMSIZE;
2025 
2026 	/* SB Live/Audigy supports at most 32M of memory) */
2027 	if (devc->max_mem > 32 * 1024 * 1024)
2028 		devc->max_mem = 32 * 1024 * 1024;
2029 
2030 	devc->max_pages = devc->max_mem / 4096;
2031 	if (devc->max_pages < 1024)
2032 		devc->max_pages = 1024;
2033 
2034 	/* Allocate page table */
2035 	if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL,
2036 	    &devc->pt_dmah) != DDI_SUCCESS) {
2037 		audio_dev_warn(devc->adev,
2038 		    "failed to allocate page table handle");
2039 		goto error;
2040 	}
2041 
2042 	if (ddi_dma_mem_alloc(devc->pt_dmah, devc->max_pages * 4,
2043 	    &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
2044 	    &devc->pt_kaddr, &len, &devc->pt_acch) !=
2045 	    DDI_SUCCESS) {
2046 		audio_dev_warn(devc->adev,
2047 		    "failed to allocate memory for page table");
2048 		goto error;
2049 	}
2050 
2051 	if (ddi_dma_addr_bind_handle(devc->pt_dmah, NULL,
2052 	    devc->pt_kaddr, len, DDI_DMA_CONSISTENT | DDI_DMA_WRITE,
2053 	    DDI_DMA_SLEEP, NULL, &cookie, &count) != DDI_SUCCESS) {
2054 		audio_dev_warn(devc->adev,
2055 		    "failed binding page table DMA handle");
2056 		goto error;
2057 	}
2058 
2059 	devc->page_map = (void *)devc->pt_kaddr;
2060 	devc->pt_paddr = cookie.dmac_address;
2061 	bzero(devc->pt_kaddr, devc->max_pages * 4);
2062 
2063 	/* Allocate silent page */
2064 	if (ddi_dma_alloc_handle(devc->dip, &dma_attr_buf, DDI_DMA_SLEEP, NULL,
2065 	    &devc->silence_dmah) != DDI_SUCCESS) {
2066 		audio_dev_warn(devc->adev,
2067 		    "failed to allocate silent page handle");
2068 		goto error;
2069 	}
2070 
2071 	if (ddi_dma_mem_alloc(devc->silence_dmah, 4096,
2072 	    &buf_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
2073 	    &devc->silence_kaddr, &len,
2074 	    &devc->silence_acch) != DDI_SUCCESS) {
2075 		audio_dev_warn(devc->adev,
2076 		    "failed to allocate silent page memory");
2077 		goto error;
2078 	}
2079 
2080 	(void) ddi_dma_sync(devc->silence_dmah, 0, 0, DDI_DMA_SYNC_FORDEV);
2081 
2082 	if (ddi_dma_addr_bind_handle(devc->silence_dmah, NULL,
2083 	    devc->silence_kaddr, len, DDI_DMA_CONSISTENT | DDI_DMA_WRITE,
2084 	    DDI_DMA_SLEEP, NULL, &cookie, &count) != DDI_SUCCESS) {
2085 		audio_dev_warn(devc->adev,
2086 		    "failed binding silent page DMA handle");
2087 		goto error;
2088 	}
2089 
2090 	devc->silence_paddr = cookie.dmac_address;
2091 	bzero(devc->silence_kaddr, 4096);
2092 	devc->audio_memptr = 4096;	/* Skip the silence page */
2093 
2094 	for (i = 0; i < devc->max_pages; i++)
2095 		FILL_PAGE_MAP_ENTRY(i, devc->silence_paddr);
2096 
2097 	(void) ddi_dma_sync(devc->pt_dmah, 0, 0, DDI_DMA_SYNC_FORDEV);
2098 
2099 	devc->ac97 = ac97_allocate(devc->adev, dip,
2100 	    emu10k_read_ac97, emu10k_write_ac97, devc);
2101 	if (devc->ac97 == NULL) {
2102 		audio_dev_warn(devc->adev, "failed to allocate ac97 handle");
2103 		goto error;
2104 	}
2105 
2106 	ac97_probe_controls(devc->ac97);
2107 
2108 	/* allocate voice 0 for play */
2109 	if (emu10k_alloc_port(devc, EMU10K_REC) != DDI_SUCCESS)
2110 		goto error;
2111 
2112 	if (emu10k_alloc_port(devc, EMU10K_PLAY) != DDI_SUCCESS)
2113 		goto error;
2114 
2115 	/* now initialize the hardware */
2116 	mutex_enter(&devc->mutex);
2117 	if (emu10k_hwinit(devc) != DDI_SUCCESS) {
2118 		mutex_exit(&devc->mutex);
2119 		goto error;
2120 	}
2121 	mutex_exit(&devc->mutex);
2122 
2123 	emu10k_create_controls(devc);
2124 
2125 	if (audio_dev_register(devc->adev) != DDI_SUCCESS) {
2126 		audio_dev_warn(devc->adev, "unable to register audio device");
2127 		goto error;
2128 	}
2129 
2130 	ddi_report_dev(dip);
2131 
2132 	return (DDI_SUCCESS);
2133 
2134 error:
2135 	emu10k_destroy(devc);
2136 	return (DDI_FAILURE);
2137 }
2138 
2139 int
emu10k_resume(dev_info_t * dip)2140 emu10k_resume(dev_info_t *dip)
2141 {
2142 	emu10k_devc_t *devc;
2143 
2144 	devc = ddi_get_driver_private(dip);
2145 
2146 	mutex_enter(&devc->mutex);
2147 	if (emu10k_hwinit(devc) != DDI_SUCCESS) {
2148 		mutex_exit(&devc->mutex);
2149 		/*
2150 		 * In case of failure, we leave the chip suspended,
2151 		 * but don't panic.  Audio service is not normally a a
2152 		 * critical service.
2153 		 */
2154 		audio_dev_warn(devc->adev, "FAILED to RESUME device");
2155 		return (DDI_SUCCESS);
2156 	}
2157 
2158 	mutex_exit(&devc->mutex);
2159 
2160 	/* resume ac97 */
2161 	ac97_reset(devc->ac97);
2162 
2163 	audio_dev_resume(devc->adev);
2164 
2165 	return (DDI_SUCCESS);
2166 }
2167 
2168 int
emu10k_detach(emu10k_devc_t * devc)2169 emu10k_detach(emu10k_devc_t *devc)
2170 {
2171 	if (audio_dev_unregister(devc->adev) != DDI_SUCCESS)
2172 		return (DDI_FAILURE);
2173 
2174 	emu10k_destroy(devc);
2175 	return (DDI_SUCCESS);
2176 }
2177 
2178 int
emu10k_suspend(emu10k_devc_t * devc)2179 emu10k_suspend(emu10k_devc_t *devc)
2180 {
2181 	audio_dev_suspend(devc->adev);
2182 
2183 	return (DDI_SUCCESS);
2184 }
2185 
2186 static int emu10k_ddi_attach(dev_info_t *, ddi_attach_cmd_t);
2187 static int emu10k_ddi_detach(dev_info_t *, ddi_detach_cmd_t);
2188 static int emu10k_ddi_quiesce(dev_info_t *);
2189 
2190 static struct dev_ops emu10k_dev_ops = {
2191 	DEVO_REV,			/* rev */
2192 	0,				/* refcnt */
2193 	NULL,				/* getinfo */
2194 	nulldev,			/* identify */
2195 	nulldev,			/* probe */
2196 	emu10k_ddi_attach,		/* attach */
2197 	emu10k_ddi_detach,		/* detach */
2198 	nodev,				/* reset */
2199 	NULL,				/* cb_ops */
2200 	NULL,				/* bus_ops */
2201 	NULL,				/* power */
2202 	emu10k_ddi_quiesce,		/* quiesce */
2203 };
2204 
2205 static struct modldrv emu10k_modldrv = {
2206 	&mod_driverops,			/* drv_modops */
2207 	"Creative EMU10K Audio",	/* linkinfo */
2208 	&emu10k_dev_ops,		/* dev_ops */
2209 };
2210 
2211 static struct modlinkage modlinkage = {
2212 	MODREV_1,
2213 	{ &emu10k_modldrv, NULL }
2214 };
2215 
2216 int
_init(void)2217 _init(void)
2218 {
2219 	int rv;
2220 
2221 	audio_init_ops(&emu10k_dev_ops, EMU10K_NAME);
2222 	if ((rv = mod_install(&modlinkage)) != 0) {
2223 		audio_fini_ops(&emu10k_dev_ops);
2224 	}
2225 	return (rv);
2226 }
2227 
2228 int
_fini(void)2229 _fini(void)
2230 {
2231 	int rv;
2232 
2233 	if ((rv = mod_remove(&modlinkage)) == 0) {
2234 		audio_fini_ops(&emu10k_dev_ops);
2235 	}
2236 	return (rv);
2237 }
2238 
2239 int
_info(struct modinfo * modinfop)2240 _info(struct modinfo *modinfop)
2241 {
2242 	return (mod_info(&modlinkage, modinfop));
2243 }
2244 
2245 int
emu10k_ddi_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)2246 emu10k_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
2247 {
2248 	switch (cmd) {
2249 	case DDI_ATTACH:
2250 		return (emu10k_attach(dip));
2251 
2252 	case DDI_RESUME:
2253 		return (emu10k_resume(dip));
2254 
2255 	default:
2256 		return (DDI_FAILURE);
2257 	}
2258 }
2259 
2260 int
emu10k_ddi_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)2261 emu10k_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
2262 {
2263 	emu10k_devc_t *devc;
2264 
2265 	devc = ddi_get_driver_private(dip);
2266 
2267 	switch (cmd) {
2268 	case DDI_DETACH:
2269 		return (emu10k_detach(devc));
2270 
2271 	case DDI_SUSPEND:
2272 		return (emu10k_suspend(devc));
2273 
2274 	default:
2275 		return (DDI_FAILURE);
2276 	}
2277 }
2278 
2279 int
emu10k_ddi_quiesce(dev_info_t * dip)2280 emu10k_ddi_quiesce(dev_info_t *dip)
2281 {
2282 	emu10k_devc_t *devc;
2283 
2284 	devc = ddi_get_driver_private(dip);
2285 
2286 	/* stop all voices */
2287 	for (int i = 0; i < 64; i++) {
2288 		emu10k_write_reg(devc, VEDS, i, 0);
2289 	}
2290 	for (int i = 0; i < 64; i++) {
2291 		emu10k_write_reg(devc, VTFT, i, 0);
2292 		emu10k_write_reg(devc, CVCF, i, 0);
2293 		emu10k_write_reg(devc, PTAB, i, 0);
2294 		emu10k_write_reg(devc, CPF, i, 0);
2295 	}
2296 
2297 	/*
2298 	 * Turn off the hardware
2299 	 */
2300 	OUTL(devc,
2301 	    HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK |
2302 	    HCFG_MUTEBUTTONENABLE, devc->regs + HCFG);
2303 
2304 	/* stop ADC recording */
2305 	emu10k_write_reg(devc, ADCSR, 0, 0x0);
2306 	emu10k_write_reg(devc, ADCBA, 0, 0x0);
2307 	emu10k_write_reg(devc, ADCBA, 0, 0x0);
2308 
2309 	emu10k_write_reg(devc, PTBA, 0, 0);
2310 
2311 	return (DDI_SUCCESS);
2312 }
2313