xref: /illumos-gate/usr/src/uts/common/sys/i8272A.h (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright (c) 1995 by Sun Microsystems, Inc.
24  * All rights reserved.
25  */
26 
27 #ifndef	_SYS_I8272A_H
28 #define	_SYS_I8272A_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 /*
35  * i/o port numbers
36  */
37 #define	FCR_BASE	0x3f0	/* default i/o base address */
38 
39 #define	FCR_SRA		0x000	/* only 82077AA (not AT mode) or SMC */
40 #define	FCR_SRB		0x001	/* only 82077AA (not AT mode) or SMC */
41 #define	FCR_DOR		0x002
42 #define	FCR_MSR		0x004
43 #define	FCR_DSR		0x004	/* only enhanced controllers */
44 #define	FCR_DATA	0x005
45 #define	FCR_DIR		0x007
46 #define	FCR_CCR		0x007	/* 82077AA term; == DSR on PC/AT */
47 
48 /*  SRA : values for Configuration Select Register for SMC FDC37C66xGT */
49 #define	FSA_ENA5	0x55	/*  enable config mode, issue twice */
50 #define	FSA_ENA6	0x44	/*  enable config mode, issue twice */
51 #define	FSA_DISB	0xAA	/*  disable config mode */
52 #define	FSA_CR5		0x05	/*  select config register 5 */
53 
54 /*  SRB : Configuration Data Register for SMC FDC37C66xGT */
55 #define	FSB_DSDEF	0xE7	/*  bit mask for density select in reg 5 */
56 #define	FSB_DSLO	0x10	/*  density select = LOW (300 rpm) */
57 #define	FSB_DSHI	0x18	/*  density select = HIGH (360 rpm) */
58 
59 /*  DOR : Digital Output Register */
60 #define	FD_DMTREN	0xF0
61 #define	FD_D3MTR	0x80
62 #define	FD_D2MTR	0x40
63 #define	FD_DBMTR	0x20
64 #define	FD_DAMTR	0x10
65 #define	FD_ENABLE	0x08	/* DMA gate */
66 #define	FD_RSETZ	0x04
67 #define	FD_DRSEL	0x03
68 #define	FD_DBSEL	0x01
69 #define	FD_DASEL	0x00
70 
71 #define	ENAB_MCA_INT	0x00
72 
73 
74 /* MSR - Main Status Register */
75 #define	MS_RQM		0x80	/* request for master - chip needs attention */
76 #define	MS_DIO		0x40	/* data in/out, 1 = remove bytes from fifo */
77 #define	MS_NDM		0x20	/* non-dma mode - 1 during execution phase */
78 #define	MS_CB		0x10	/* controller busy, command in progress */
79 #define	MS_D3B		0x08	/* drive 3 busy */
80 #define	MS_D2B		0x04	/* drive 2 busy */
81 #define	MS_DBB		0x02	/* drive B busy */
82 #define	MS_DAB		0x01	/* drive A busy */
83 
84 #define	FDC_RQM_RETRY	300
85 
86 
87 /*  DIR : Digital Input Register */
88 #define	FDI_DKCHG	0x80	/* this is inverted in Model 30 mode */
89 #define	FDI_DMAGAT	0x08	/* Model 30: DMA gate */
90 #define	FDI_NOPREC	0x04	/* Model 30 only */
91 #define	FDI_DRATE	0x03	/* Model 30: selected datarate mask */
92 
93 
94 /*  DSR : Datarate Select Register on 82072 and 82077AA */
95 #define	FSR_SWR		0x80	/* software reset */
96 #define	FSR_PD		0x40	/* power down */
97 #define	FSR_PRECP	0x1C	/* precomp mask */
98 #define	FSR_DRATE	0x3	/* datarate select mask */
99 
100 
101 /*  CCR : Configuration Control Register, aka Datarate Select Register */
102 #define	FCC_NOPREC	0x4	/* Model 30 only */
103 #define	FCC_DRATE	0x3	/* datarate select mask */
104 
105 
106 /*
107  * Floppy controller command opcodes
108  */
109 #define	FO_MODE		0x01	/* National PC8477 types only */
110 #define	FO_RDTRK	0x02
111 #define	FO_SPEC		0x03
112 #define	FO_SDRV		0x04	/* read status register 3 */
113 #define	FO_WRDAT	0x05
114 #define	FO_RDDAT	0x06
115 #define	FO_RECAL	0x07
116 #define	FO_SINT		0x08
117 #define	FO_WRDEL	0x09
118 #define	FO_RDID		0x0A
119 #define	FO_RDDEL	0x0C
120 #define	FO_FRMT		0x0D
121 #define	FO_SEEK		0x0F
122 #define	FO_VRSN		0x10	/* get version */
123 #define	FO_PERP		0x12	/* perpendicular mode */
124 #define	FO_CNFG		0x13	/* configure */
125 #define	FO_NSC		0x18	/* identify National chip */
126 
127 				/* option bits */
128 #define	FO_MT		0x80	/* multi-track operation */
129 #define	FO_MFM		0x40	/* double & high density disks */
130 #define	FO_FM		0x00	/* single density disks */
131 #define	FO_SK		0x20	/* skip deleted adr mark */
132 
133 
134 #define	S0_ICMASK	0xC0	/* status register 0 */
135 #define	S0_XRDY		0xC0
136 #define	S0_IVCMD	0x80
137 #define	S0_ABTERM	0x40
138 #define	S0_SEKEND	0x20
139 #define	S0_ECHK		0x10
140 #define	S0_NOTRDY	0x08
141 
142 #define	S1_EOCYL	0x80	/* status register 1 */
143 #define	S1_CRCER	0x20
144 #define	S1_OVRUN	0x10
145 #define	S1_NODATA	0x04
146 #define	S1_MADMK	0x01
147 
148 #define	S3_FAULT	0x80	/* status register 3 */
149 #define	S3_WPROT	0x40
150 #define	S3_DRRDY	0x20
151 #define	S3_TRK0		0x10
152 #define	S3_2SIDE	0x08
153 #define	S3_HEAD		0x04
154 #define	S3_UNIT		0x03
155 
156 
157 /*
158  * controller chip values
159  */
160 #define	i8272A		0x8272
161 #define	uPD72064	0x72064		/* NEC */
162 /* enhanced floppy controllers */
163 #define	i82077		0x82077
164 #define	PC87322		0x87322		/* National Semiconducter */
165 #define	FDC37C665	0x37c665	/* SMC */
166 #define	FDC37C666	0x37c666	/* SMC */
167 
168 #ifdef	__cplusplus
169 }
170 #endif
171 
172 #endif	/* !_SYS_I8272A_H */
173