xref: /illumos-gate/usr/src/uts/common/io/bge/bge_hw.h (revision a2876d03ca2556102e024ae4a50bb4db8fe562b0)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2010-2013, by Broadcom, Inc.
24  * All Rights Reserved.
25  */
26 
27 /*
28  * Copyright (c) 2002, 2010, Oracle and/or its affiliates.
29  * All rights reserved.
30  */
31 
32 #ifndef _BGE_HW_H
33 #define	_BGE_HW_H
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39 #include <sys/types.h>
40 
41 
42 /*
43  * First section:
44  *	Identification of the various Broadcom chips
45  *
46  * Note: the various ID values are *not* all unique ;-(
47  *
48  * Note: the presence of an ID here does *not* imply that the chip is
49  * supported.  At this time, only the 5703C, 5704C, and 5704S devices
50  * used on the motherboards of certain Sun products are supported.
51  *
52  * Note: the revision-id values in the PCI revision ID register are
53  * *NOT* guaranteed correct.  Use the chip ID from the MHCR instead.
54  */
55 
56 #define	VENDOR_ID_BROADCOM		0x14e4
57 #define	VENDOR_ID_SUN			0x108e
58 
59 #define	DEVICE_ID_5700			0x1644
60 #define	DEVICE_ID_5700x			0x0003
61 #define	DEVICE_ID_5701			0x1645
62 #define	DEVICE_ID_5702			0x16a6
63 #define	DEVICE_ID_5702fe		0x164d
64 #define	DEVICE_ID_5703C			0x16a7
65 #define	DEVICE_ID_5703S			0x1647
66 #define	DEVICE_ID_5703			0x16c7
67 #define	DEVICE_ID_5704C			0x1648
68 #define	DEVICE_ID_5704S			0x16a8
69 #define	DEVICE_ID_5704			0x1649
70 #define	DEVICE_ID_5705C			0x1653
71 #define	DEVICE_ID_5705_2		0x1654
72 #define	DEVICE_ID_5717			0x1655
73 #define	DEVICE_ID_5717_C0		0x1665
74 #define	DEVICE_ID_5718			0x1656
75 #define	DEVICE_ID_5719			0x1657
76 #define	DEVICE_ID_5720			0x165f
77 #define	DEVICE_ID_5724			0x165c
78 #define	DEVICE_ID_5725			0x1643
79 #define	DEVICE_ID_5727			0x16f3
80 #define	DEVICE_ID_5705M			0x165d
81 #define	DEVICE_ID_5705MA3		0x165e
82 #define	DEVICE_ID_5705F			0x166e
83 #define	DEVICE_ID_5780			0x166a
84 #define	DEVICE_ID_5782			0x1696
85 #define	DEVICE_ID_5785			0x1699
86 #define	DEVICE_ID_5787			0x169b
87 #define	DEVICE_ID_5787M			0x1693
88 #define	DEVICE_ID_5788			0x169c
89 #define	DEVICE_ID_5789			0x169d
90 #define	DEVICE_ID_5751			0x1677
91 #define	DEVICE_ID_5751M			0x167d
92 #define	DEVICE_ID_5752			0x1600
93 #define	DEVICE_ID_5752M			0x1601
94 #define	DEVICE_ID_5753			0x16fd
95 #define	DEVICE_ID_5754			0x167a
96 #define	DEVICE_ID_5755			0x167b
97 #define	DEVICE_ID_5755M			0x1673
98 #define	DEVICE_ID_5756M			0x1674
99 #define	DEVICE_ID_5721			0x1659
100 #define	DEVICE_ID_5722			0x165a
101 #define	DEVICE_ID_5723			0x165b
102 #define	DEVICE_ID_5714C			0x1668
103 #define	DEVICE_ID_5714S			0x1669
104 #define	DEVICE_ID_5715C			0x1678
105 #define	DEVICE_ID_5715S			0x1679
106 #define	DEVICE_ID_5761E			0x1680
107 #define	DEVICE_ID_5761			0x1681
108 #define	DEVICE_ID_5764			0x1684
109 #define	DEVICE_ID_5906			0x1712
110 #define	DEVICE_ID_5906M			0x1713
111 #define	DEVICE_ID_57780			0x1692
112 #define	DEVICE_ID_57761			0x16b0
113 #define	DEVICE_ID_57762			0x1682
114 #define	DEVICE_ID_57765			0x16b4
115 #define	DEVICE_ID_57766			0x1686
116 #define	DEVICE_ID_57781			0x16b1
117 #define	DEVICE_ID_57782			0x16b7
118 #define	DEVICE_ID_57785			0x16b5
119 #define	DEVICE_ID_57786			0x16b3
120 #define	DEVICE_ID_57791			0x16b2
121 #define	DEVICE_ID_57795			0x16b6
122 
123 #define	REVISION_ID_5700_B0		0x10
124 #define	REVISION_ID_5700_B2		0x12
125 #define	REVISION_ID_5700_B3		0x13
126 #define	REVISION_ID_5700_C0		0x20
127 #define	REVISION_ID_5700_C1		0x21
128 #define	REVISION_ID_5700_C2		0x22
129 
130 #define	REVISION_ID_5701_A0		0x08
131 #define	REVISION_ID_5701_A2		0x12
132 #define	REVISION_ID_5701_A3		0x15
133 
134 #define	REVISION_ID_5702_A0		0x00
135 
136 #define	REVISION_ID_5703_A0		0x00
137 #define	REVISION_ID_5703_A1		0x01
138 #define	REVISION_ID_5703_A2		0x02
139 
140 #define	REVISION_ID_5704_A0		0x00
141 #define	REVISION_ID_5704_A1		0x01
142 #define	REVISION_ID_5704_A2		0x02
143 #define	REVISION_ID_5704_A3		0x03
144 #define	REVISION_ID_5704_B0		0x10
145 
146 #define	REVISION_ID_5705_A0		0x00
147 #define	REVISION_ID_5705_A1		0x01
148 #define	REVISION_ID_5705_A2		0x02
149 #define	REVISION_ID_5705_A3		0x03
150 
151 #define	REVISION_ID_5721_A0		0x00
152 #define	REVISION_ID_5721_A1		0x01
153 
154 #define	REVISION_ID_5751_A0		0x00
155 #define	REVISION_ID_5751_A1		0x01
156 
157 #define	REVISION_ID_5714_A0		0x00
158 #define	REVISION_ID_5714_A1		0x01
159 #define	REVISION_ID_5714_A2		0xA2
160 #define	REVISION_ID_5714_A3		0xA3
161 
162 #define	REVISION_ID_5715_A0		0x00
163 #define	REVISION_ID_5715_A1		0x01
164 #define	REVISION_ID_5715_A2		0xA2
165 
166 #define	REVISION_ID_5715S_A0		0x00
167 #define	REVISION_ID_5715S_A1		0x01
168 
169 #define	REVISION_ID_5754_A0		0x00
170 #define	REVISION_ID_5754_A1		0x01
171 
172 #define	DEVICE_5704_SERIES_CHIPSETS(bgep)\
173 		((bgep->chipid.device == DEVICE_ID_5700) ||\
174 		(bgep->chipid.device == DEVICE_ID_5701) ||\
175 		(bgep->chipid.device == DEVICE_ID_5702) ||\
176 		(bgep->chipid.device == DEVICE_ID_5702fe)||\
177 		(bgep->chipid.device == DEVICE_ID_5703C) ||\
178 		(bgep->chipid.device == DEVICE_ID_5703S) ||\
179 		(bgep->chipid.device == DEVICE_ID_5703) ||\
180 		(bgep->chipid.device == DEVICE_ID_5704C) ||\
181 		(bgep->chipid.device == DEVICE_ID_5704S) ||\
182 		(bgep->chipid.device == DEVICE_ID_5704))
183 
184 #define	DEVICE_5702_SERIES_CHIPSETS(bgep) \
185 		((bgep->chipid.device == DEVICE_ID_5702) ||\
186 		(bgep->chipid.device == DEVICE_ID_5702fe))
187 
188 #define	DEVICE_5705_SERIES_CHIPSETS(bgep) \
189 		((bgep->chipid.device == DEVICE_ID_5705C) ||\
190 		(bgep->chipid.device == DEVICE_ID_5705M) ||\
191 		(bgep->chipid.device == DEVICE_ID_5705MA3) ||\
192 		(bgep->chipid.device == DEVICE_ID_5705F) ||\
193 		(bgep->chipid.device == DEVICE_ID_5780) ||\
194 		(bgep->chipid.device == DEVICE_ID_5782) ||\
195 		(bgep->chipid.device == DEVICE_ID_5788) ||\
196 		(bgep->chipid.device == DEVICE_ID_5705_2) ||\
197 		(bgep->chipid.device == DEVICE_ID_5754) ||\
198 		(bgep->chipid.device == DEVICE_ID_5755) ||\
199 		(bgep->chipid.device == DEVICE_ID_5756M) ||\
200 		(bgep->chipid.device == DEVICE_ID_5753))
201 
202 #define	DEVICE_5721_SERIES_CHIPSETS(bgep) \
203 		((bgep->chipid.device == DEVICE_ID_5721) ||\
204 		(bgep->chipid.device == DEVICE_ID_5751) ||\
205 		(bgep->chipid.device == DEVICE_ID_5751M) ||\
206 		(bgep->chipid.device == DEVICE_ID_5752) ||\
207 		(bgep->chipid.device == DEVICE_ID_5752M) ||\
208 		(bgep->chipid.device == DEVICE_ID_5789))
209 
210 #define	DEVICE_5717_SERIES_CHIPSETS(bgep) \
211 		((bgep->chipid.device == DEVICE_ID_5717) ||\
212 		(bgep->chipid.device == DEVICE_ID_5718) ||\
213 		(bgep->chipid.device == DEVICE_ID_5719) ||\
214 		(bgep->chipid.device == DEVICE_ID_5720) ||\
215 		(bgep->chipid.device == DEVICE_ID_5724))
216 
217 #define	DEVICE_5725_SERIES_CHIPSETS(bgep) \
218 		((bgep->chipid.device == DEVICE_ID_5725) ||\
219 		(bgep->chipid.device == DEVICE_ID_5727))
220 
221 #define	DEVICE_5723_SERIES_CHIPSETS(bgep) \
222 		((bgep->chipid.device == DEVICE_ID_5723) ||\
223 		(bgep->chipid.device == DEVICE_ID_5761) ||\
224 		(bgep->chipid.device == DEVICE_ID_5761E) ||\
225 		(bgep->chipid.device == DEVICE_ID_5764) ||\
226 		(bgep->chipid.device == DEVICE_ID_5785) ||\
227 		(bgep->chipid.device == DEVICE_ID_57780))
228 
229 #define	DEVICE_5714_SERIES_CHIPSETS(bgep) \
230 		((bgep->chipid.device == DEVICE_ID_5714C) ||\
231 		(bgep->chipid.device == DEVICE_ID_5714S) ||\
232 		(bgep->chipid.device == DEVICE_ID_5715C) ||\
233 		(bgep->chipid.device == DEVICE_ID_5715S))
234 
235 #define	DEVICE_5906_SERIES_CHIPSETS(bgep) \
236 		((bgep->chipid.device == DEVICE_ID_5906) ||\
237 		(bgep->chipid.device == DEVICE_ID_5906M))
238 
239 /*
240  * Even though the hardware register calls this the 57785 family, all of the
241  * BSDs call this the 57765 series, so we call it that way to make it more
242  * similar.
243  */
244 #define	DEVICE_57765_SERIES_CHIPSETS(bgep) \
245 		((bgep->chipid.device == DEVICE_ID_57761) || \
246 		(bgep->chipid.device == DEVICE_ID_57762) || \
247 		(bgep->chipid.device == DEVICE_ID_57765) || \
248 		(bgep->chipid.device == DEVICE_ID_57766) || \
249 		(bgep->chipid.device == DEVICE_ID_57781) || \
250 		(bgep->chipid.device == DEVICE_ID_57782) || \
251 		(bgep->chipid.device == DEVICE_ID_57785) || \
252 		(bgep->chipid.device == DEVICE_ID_57786) || \
253 		(bgep->chipid.device == DEVICE_ID_57791) || \
254 		(bgep->chipid.device == DEVICE_ID_57795))
255 
256 /*
257  * Second section:
258  *	Offsets of important registers & definitions for bits therein
259  */
260 
261 /*
262  * PCI-X registers & bits
263  */
264 #define	PCIX_CONF_COMM			0x42
265 #define	PCIX_COMM_RELAXED		0x0002
266 
267 /*
268  * Miscellaneous Host Control Register, in PCI config space
269  */
270 #define	PCI_CONF_BGE_MHCR		0x68
271 #define	MHCR_CHIP_REV_MASK		0xffff0000
272 #define	MHCR_ENABLE_TAGGED_STATUS_MODE	0x00000200
273 #define	MHCR_MASK_INTERRUPT_MODE	0x00000100
274 #define	MHCR_ENABLE_INDIRECT_ACCESS	0x00000080
275 #define	MHCR_ENABLE_REGISTER_WORD_SWAP	0x00000040
276 #define	MHCR_ENABLE_CLOCK_CONTROL_WRITE	0x00000020
277 #define	MHCR_ENABLE_PCI_STATE_RW	0x00000010
278 #define	MHCR_ENABLE_ENDIAN_WORD_SWAP	0x00000008
279 #define	MHCR_ENABLE_ENDIAN_BYTE_SWAP	0x00000004
280 #define	MHCR_MASK_PCI_INT_OUTPUT	0x00000002
281 #define	MHCR_CLEAR_INTERRUPT_INTA	0x00000001
282 #define	MHCR_BOUNDARY_CHECK		0x00002000
283 #define	MHCR_TLP_MINOR_ERR_TOLERANCE	0x00008000
284 
285 #define	MHCR_CHIP_REV_5700_B0		0x71000000
286 #define	MHCR_CHIP_REV_5700_B2		0x71020000
287 #define	MHCR_CHIP_REV_5700_B3		0x71030000
288 #define	MHCR_CHIP_REV_5700_C0		0x72000000
289 #define	MHCR_CHIP_REV_5700_C1		0x72010000
290 #define	MHCR_CHIP_REV_5700_C2		0x72020000
291 
292 #define	MHCR_CHIP_REV_5701_A0		0x00000000
293 #define	MHCR_CHIP_REV_5701_A2		0x00020000
294 #define	MHCR_CHIP_REV_5701_A3		0x00030000
295 #define	MHCR_CHIP_REV_5701_A5		0x01050000
296 
297 #define	MHCR_CHIP_REV_5702_A0		0x10000000
298 #define	MHCR_CHIP_REV_5702_A1		0x10010000
299 #define	MHCR_CHIP_REV_5702_A2		0x10020000
300 
301 #define	MHCR_CHIP_REV_5703_A0		0x10000000
302 #define	MHCR_CHIP_REV_5703_A1		0x10010000
303 #define	MHCR_CHIP_REV_5703_A2		0x10020000
304 #define	MHCR_CHIP_REV_5703_B0		0x11000000
305 #define	MHCR_CHIP_REV_5703_B1		0x11010000
306 
307 #define	MHCR_CHIP_REV_5704_A0		0x20000000
308 #define	MHCR_CHIP_REV_5704_A1		0x20010000
309 #define	MHCR_CHIP_REV_5704_A2		0x20020000
310 #define	MHCR_CHIP_REV_5704_A3		0x20030000
311 #define	MHCR_CHIP_REV_5704_B0		0x21000000
312 
313 #define	MHCR_CHIP_REV_5705_A0		0x30000000
314 #define	MHCR_CHIP_REV_5705_A1		0x30010000
315 #define	MHCR_CHIP_REV_5705_A2		0x30020000
316 #define	MHCR_CHIP_REV_5705_A3		0x30030000
317 #define	MHCR_CHIP_REV_5705_A5		0x30050000
318 
319 #define	MHCR_CHIP_REV_5782_A0		0x30030000
320 #define	MHCR_CHIP_REV_5782_A1		0x30030088
321 
322 #define	MHCR_CHIP_REV_5788_A1		0x30050000
323 
324 #define	MHCR_CHIP_REV_5751_A0		0x40000000
325 #define	MHCR_CHIP_REV_5751_A1		0x40010000
326 
327 #define	MHCR_CHIP_REV_5721_A0		0x41000000
328 #define	MHCR_CHIP_REV_5721_A1		0x41010000
329 
330 #define	MHCR_CHIP_REV_5714_A0		0x50000000
331 #define	MHCR_CHIP_REV_5714_A1		0x90010000
332 
333 #define	MHCR_CHIP_REV_5715_A0		0x50000000
334 #define	MHCR_CHIP_REV_5715_A1		0x90010000
335 
336 #define	MHCR_CHIP_REV_5715S_A0		0x50000000
337 #define	MHCR_CHIP_REV_5715S_A1		0x90010000
338 
339 #define	MHCR_CHIP_REV_5754_A0		0xb0000000
340 #define	MHCR_CHIP_REV_5754_A1		0xb0010000
341 
342 #define	MHCR_CHIP_REV_5787_A0		0xb0000000
343 #define	MHCR_CHIP_REV_5787_A1		0xb0010000
344 #define	MHCR_CHIP_REV_5787_A2		0xb0020000
345 
346 #define	MHCR_CHIP_REV_5755_A0		0xa0000000
347 #define	MHCR_CHIP_REV_5755_A1		0xa0010000
348 
349 #define	MHCR_CHIP_REV_5906_A0		0xc0000000
350 #define	MHCR_CHIP_REV_5906_A1		0xc0010000
351 #define	MHCR_CHIP_REV_5906_A2		0xc0020000
352 
353 #define	CHIP_ASIC_REV_USE_PROD_ID_REG	0xf0000000
354 #define	MHCR_CHIP_ASIC_REV(bgep) ((bgep)->chipid.asic_rev & 0xf0000000)
355 #define	CHIP_ASIC_REV_PROD_ID(bgep) ((bgep)->chipid.asic_rev_prod_id)
356 #define	CHIP_ASIC_REV(bgep) ((bgep)->chipid.asic_rev_prod_id >> 12)
357 
358 #define	MHCR_CHIP_ASIC_REV_5700		(0x7 << 28)
359 #define	MHCR_CHIP_ASIC_REV_5701		(0x0 << 28)
360 #define	MHCR_CHIP_ASIC_REV_5703		(0x1 << 28)
361 #define	MHCR_CHIP_ASIC_REV_5704		(0x2 << 28)
362 #define	MHCR_CHIP_ASIC_REV_5705		(0x3 << 28)
363 #define	MHCR_CHIP_ASIC_REV_5721_5751	(0x4 << 28)
364 #define	MHCR_CHIP_ASIC_REV_5714		(0x5 << 28)
365 #define	MHCR_CHIP_ASIC_REV_5752		(0x6 << 28)
366 #define	MHCR_CHIP_ASIC_REV_5754		(0xb << 28)
367 #define	MHCR_CHIP_ASIC_REV_5787		((uint32_t)0xb << 28)
368 #define	MHCR_CHIP_ASIC_REV_5755		((uint32_t)0xa << 28)
369 #define	MHCR_CHIP_ASIC_REV_5715		((uint32_t)0x9 << 28)
370 #define	MHCR_CHIP_ASIC_REV_5906		((uint32_t)0xc << 28)
371 /* (0xf << 28) touches all 5717 and 5725 series as well (OK) */
372 #define	MHCR_CHIP_ASIC_REV_5723		((uint32_t)0xf << 28)
373 
374 #define	CHIP_ASIC_REV_5723		0x5784
375 #define	CHIP_ASIC_REV_5761		0x5761
376 #define	CHIP_ASIC_REV_5785		0x5785
377 #define	CHIP_ASIC_REV_57780		0x57780
378 #define	CHIP_ASIC_REV_57785		0x57785
379 
380 #define	CHIP_ASIC_REV_5717		0x5717
381 #define	CHIP_ASIC_REV_5719		0x5719
382 #define	CHIP_ASIC_REV_5720		0x5720
383 #define	CHIP_ASIC_REV_5762		0x5762 /* 5725/5727 */
384 
385 #define	CHIP_ASIC_REV_PROD_ID_REG	0x000000bc
386 #define	CHIP_ASIC_REV_PROD_ID_GEN2_REG	0x000000f4
387 #define	CHIP_ASIC_REV_PROD_ID_GEN15_REG	0x000000fc
388 
389 #define	CHIP_ASIC_REV_5717_B0		0x05717100
390 #define	CHIP_ASIC_REV_5717_C0		0x05717200
391 #define	CHIP_ASIC_REV_5718_B0		0x05717100
392 #define	CHIP_ASIC_REV_5719_A0		0x05719000
393 #define	CHIP_ASIC_REV_5719_A1		0x05719001
394 #define	CHIP_ASIC_REV_5720_A0		0x05720000
395 #define	CHIP_ASIC_REV_5725_A0		0x05762000
396 #define	CHIP_ASIC_REV_5727_B0		0x05762100
397 
398 /*
399  * Match any Metal Layer Revision.
400  */
401 #define	CHIP_ASIC_REV_57765_AX		0x577850
402 
403 /*
404  * PCI DMA read/write Control Register, in PCI config space
405  *
406  * Note that several fields previously defined here have been deleted
407  * as they are not implemented in the 5703/4.
408  *
409  * Note: the value of this register is critical.  It is possible to
410  * cause various unpleasant effects (DTOs, transaction deadlock, etc)
411  * by programming the wrong value.  The value #defined below has been
412  * tested and shown to avoid all known problems.  If it is to be changed,
413  * correct operation must be reverified on all supported platforms.
414  *
415  * In particular, we set both watermark fields to 2xCacheLineSize (128)
416  * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions
417  * with Tomatillo's internal pipelines, that otherwise result in stalls,
418  * repeated retries, and DTOs.
419  */
420 #define	PCI_CONF_BGE_PDRWCR		0x6c
421 #define	PDRWCR_RWCMD_MASK		0xFF000000
422 #define	PDRWCR_PCIX32_BUGFIX_MASK	0x00800000
423 #define	PDRWCR_WRITE_WATERMARK_MASK	0x00380000
424 #define	PDRWCR_READ_WATERMARK_MASK	0x00070000
425 #define	PDRWCR_CONCURRENCY_MASK		0x0000c000
426 #define	PDRWCR_5704_FLOP_ON_RETRY	0x00008000
427 #define	PDRWCR_ONE_DMA_AT_ONCE		0x00004000
428 #define	PDRWCR_MIN_BEAT_MASK		0x000000ff
429 
430 /*
431  * These are the actual values to be put into the fields shown above
432  */
433 #define	PDRWCR_RWCMDS			0x76000000	/* MW and MR	*/
434 #define	PDRWCR_DMA_WRITE_WATERMARK	0x00180000	/* 011 => 128	*/
435 #define	PDRWCR_DMA_READ_WATERMARK	0x00030000	/* 011 => 128	*/
436 #define	PDRWCR_MIN_BEATS		0x00000000
437 
438 #define	PDRWCR_VAR_DEFAULT		0x761b0000
439 #define	PDRWCR_VAR_5721			0x76180000
440 #define	PDRWCR_VAR_5714			0x76148000	/* OR of above	*/
441 #define	PDRWCR_VAR_5715			0x76144000	/* OR of above	*/
442 #define	PDRWCR_VAR_5717			0x00380000
443 
444 /*
445  * PCI State Register, in PCI config space
446  *
447  * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit
448  * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW
449  */
450 #define	PCI_CONF_BGE_PCISTATE		0x70
451 #define	PCISTATE_ALLOW_APE_CTLSPC_WR	0x00010000
452 #define	PCISTATE_ALLOW_APE_SHMEM_WR	0x00020000
453 #define	PCISTATE_ALLOW_APE_PSPACE_WR	0x00040000
454 #define	PCISTATE_RETRY_SAME_DMA		0x00002000
455 #define	PCISTATE_FLAT_VIEW		0x00000100
456 #define	PCISTATE_EXT_ROM_RETRY		0x00000040
457 #define	PCISTATE_EXT_ROM_ENABLE		0x00000020
458 #define	PCISTATE_BUS_IS_32_BIT		0x00000010
459 #define	PCISTATE_BUS_IS_FAST		0x00000008
460 #define	PCISTATE_BUS_IS_PCI		0x00000004
461 #define	PCISTATE_INTA_STATE		0x00000002
462 #define	PCISTATE_FORCE_RESET		0x00000001
463 
464 /*
465  * PCI Clock Control Register, in PCI config space
466  */
467 #define	PCI_CONF_BGE_CLKCTL		0x74
468 #define	CLKCTL_PCIE_PLP_DISABLE		0x80000000
469 #define	CLKCTL_PCIE_DLP_DISABLE		0x40000000
470 #define	CLKCTL_PCIE_TLP_DISABLE		0x20000000
471 #define	CLKCTL_PCI_READ_TOO_LONG_FIX	0x04000000
472 #define	CLKCTL_PCI_WRITE_TOO_LONG_FIX	0x02000000
473 #define	CLKCTL_PCIE_A0_FIX		0x00101000
474 
475 /*
476  * Dual MAC Control Register, in PCI config space
477  */
478 #define	PCI_CONF_BGE_DUAL_MAC_CONTROL	0xB8
479 #define	DUALMAC_CHANNEL_CONTROL_MASK	0x00000003	/* RW	*/
480 #define	DUALMAC_CHANNEL_ID_MASK		0x00000004	/* RO	*/
481 
482 /*
483  * Register Indirect Access Address Register, 0x78 in PCI config
484  * space.  Once this is set, accesses to the Register Indirect
485  * Access Data Register (0x80) refer to the register whose address
486  * is given by *this* register.  This allows access to all the
487  * operating registers, while using only config space accesses.
488  *
489  * Note that the address written to the RIIAR should lie in one
490  * of the following ranges:
491  *	0x00000000 <= address < 0x00008000 (regular registers)
492  *	0x00030000 <= address < 0x00034000 (RxRISC scratchpad)
493  *	0x00034000 <= address < 0x00038000 (TxRISC scratchpad)
494  *	0x00038000 <= address < 0x00038800 (RxRISC ROM)
495  */
496 #define	PCI_CONF_BGE_RIAAR		0x78
497 #define	PCI_CONF_BGE_RIADR		0x80
498 
499 #define	RIAAR_REGISTER_MIN		0x00000000
500 #define	RIAAR_REGISTER_MAX		0x00008000
501 #define	RIAAR_RX_SCRATCH_MIN		0x00030000
502 #define	RIAAR_RX_SCRATCH_MAX		0x00034000
503 #define	RIAAR_TX_SCRATCH_MIN		0x00034000
504 #define	RIAAR_TX_SCRATCH_MAX		0x00038000
505 #define	RIAAR_RXROM_MIN			0x00038000
506 #define	RIAAR_RXROM_MAX			0x00038800
507 
508 /*
509  * Memory Window Base Address Register, 0x7c in PCI config space
510  * Once this is set, accesses to the Memory Window Data Access Register
511  * (0x84) refer to the word of NIC-local memory whose address is given
512  * by this register.  When used in this way, the whole of the address
513  * written to this register is significant.
514  *
515  * This register also provides the 32K-aligned base address for a 32K
516  * region of NIC-local memory that the host can directly address in
517  * the upper 32K of the 64K of PCI memory space allocated to the chip.
518  * In this case, the bottom 15 bits of the register are ignored.
519  *
520  * Note that the address written to the MWBAR should lie in the range
521  * 0x00000000 <= address < 0x00020000.  The rest of the range up to 1M
522  * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external
523  * memory were present, but it's only supported on the 5700, not the
524  * 5701/5703/5704.
525  */
526 #define	PCI_CONF_BGE_MWBAR		0x7c
527 #define	PCI_CONF_BGE_MWDAR		0x84
528 #define	MWBAR_GRANULARITY		0x00008000	/* 32k	*/
529 #define	MWBAR_GRANULE_MASK		(MWBAR_GRANULARITY-1)
530 #define	MWBAR_ONCHIP_MAX		0x00020000	/* 128k */
531 
532 /*
533  * The PCI express device control register and device status register
534  * which are only applicable on BCM5751 and BCM5721.
535  */
536 #define	PCI_CONF_DEV_CTRL		0xd8
537 #define	PCI_CONF_DEV_CTRL_5723		0xd4
538 #define	PCI_CONF_DEV_CTRL_5717		0xb4
539 #define	READ_REQ_SIZE_MASK		0x7000
540 #define	READ_REQ_SIZE_MAX		0x5000
541 #define	READ_REQ_SIZE_2K		0x4000
542 #define	DEV_CTRL_NO_SNOOP		0x0800
543 #define	DEV_CTRL_RELAXED		0x0010
544 
545 #define	PCI_CONF_DEV_STUS		0xda
546 #define	PCI_CONF_DEV_STUS_5723		0xd6
547 #define	DEVICE_ERROR_STUS		0xf
548 
549 #define	NIC_MEM_WINDOW_OFFSET		0x00008000	/* 32k	*/
550 
551 /*
552  * Where to find things in NIC-local (on-chip) memory
553  */
554 #define	NIC_MEM_SEND_RINGS		0x0100
555 #define	NIC_MEM_SEND_RING(ring)		(0x0100+16*(ring))
556 #define	NIC_MEM_RECV_RINGS		0x0200
557 #define	NIC_MEM_RECV_RING(ring)		(0x0200+16*(ring))
558 #define	NIC_MEM_STATISTICS		0x0300
559 #define	NIC_MEM_STATISTICS_SIZE		0x0800
560 #define	NIC_MEM_STATUS_BLOCK		0x0b00
561 #define	NIC_MEM_STATUS_SIZE		0x0050
562 #define	NIC_MEM_GENCOMM			0x0b50
563 
564 
565 /*
566  * Note: the (non-bogus) values below are appropriate for systems
567  * without external memory.  They would be different on a 5700 with
568  * external memory.
569  *
570  * Note: The higher send ring addresses and the mini ring shadow
571  * buffer address are dummies - systems without external memory
572  * are limited to 4 send rings and no mini receive ring.
573  */
574 #define	NIC_MEM_SHADOW_DMA		0x2000
575 #define	NIC_MEM_SHADOW_SEND_1_4		0x4000
576 #define	NIC_MEM_SHADOW_SEND_5_6		0x6000		/* bogus	*/
577 #define	NIC_MEM_SHADOW_SEND_7_8		0x7000		/* bogus	*/
578 #define	NIC_MEM_SHADOW_SEND_9_16	0x8000		/* bogus	*/
579 #define	NIC_MEM_SHADOW_BUFF_STD		0x6000
580 #define	NIC_MEM_SHADOW_BUFF_STD_5717	0x40000
581 #define	NIC_MEM_SHADOW_BUFF_JUMBO	0x7000
582 #define	NIC_MEM_SHADOW_BUFF_MINI	0x8000		/* bogus	*/
583 #define	NIC_MEM_SHADOW_SEND_RING(ring, nslots)	(0x4000 + 4*(ring)*(nslots))
584 
585 /*
586  * Put this in the GENCOMM port to tell the firmware not to run PXE
587  */
588 #define	T3_MAGIC_NUMBER			0x4b657654u
589 
590 /*
591  * The remaining registers appear in the low 32K of regular
592  * PCI Memory Address Space
593  */
594 
595 /*
596  * All the state machine control registers below have at least a
597  * <RESET> bit and an <ENABLE> bit as defined below.  Some also
598  * have an <ATTN_ENABLE> bit.
599  */
600 #define	STATE_MACHINE_ATTN_ENABLE_BIT	0x00000004
601 #define	STATE_MACHINE_ENABLE_BIT	0x00000002
602 #define	STATE_MACHINE_RESET_BIT		0x00000001
603 
604 #define	TRANSMIT_MAC_MODE_REG		0x045c
605 #define	SEND_DATA_INITIATOR_MODE_REG	0x0c00
606 #define	SEND_DATA_COMPLETION_MODE_REG	0x1000
607 #define	SEND_BD_SELECTOR_MODE_REG	0x1400
608 #define	SEND_BD_INITIATOR_MODE_REG	0x1800
609 #define	SEND_BD_COMPLETION_MODE_REG	0x1c00
610 
611 #define	RECEIVE_MAC_MODE_REG		0x0468
612 #define	RCV_LIST_PLACEMENT_MODE_REG	0x2000
613 #define	RCV_DATA_BD_INITIATOR_MODE_REG	0x2400
614 #define	RCV_DATA_COMPLETION_MODE_REG	0x2800
615 #define	RCV_BD_INITIATOR_MODE_REG	0x2c00
616 #define	RCV_BD_COMPLETION_MODE_REG	0x3000
617 #define	RCV_LIST_SELECTOR_MODE_REG	0x3400
618 
619 #define	MBUF_CLUSTER_FREE_MODE_REG	0x3800
620 #define	HOST_COALESCE_MODE_REG		0x3c00
621 #define	MEMORY_ARBITER_MODE_REG		0x4000
622 #define	BUFFER_MANAGER_MODE_REG		0x4400
623 #define	BUFFER_MANAGER_MODE_NO_TX_UNDERRUN	0x80000000
624 #define	BUFFER_MANAGER_MODE_MBLOW_ATTN_ENABLE	0x00000010
625 #define	READ_DMA_MODE_REG		0x4800
626 #define	WRITE_DMA_MODE_REG		0x4c00
627 #define	DMA_COMPLETION_MODE_REG		0x6400
628 #define	FAST_BOOT_PC			0x6894
629 
630 #define	RDMA_RSRV_CTRL_REG		0x4900
631 #define	RDMA_RSRV_CTRL_REG2		0x4890
632 #define	RDMA_RSRV_CTRL_FIFO_OFLW_FIX	0x00000004
633 #define	RDMA_RSRV_CTRL_FIFO_LWM_1_5K	0x00000c00
634 #define	RDMA_RSRV_CTRL_FIFO_LWM_MASK	0x00000ff0
635 #define	RDMA_RSRV_CTRL_FIFO_HWM_1_5K	0x000c0000
636 #define	RDMA_RSRV_CTRL_FIFO_HWM_MASK	0x000ff000
637 #define	RDMA_RSRV_CTRL_TXMRGN_320B	0x28000000
638 #define	RDMA_RSRV_CTRL_TXMRGN_MASK	0xffe00000
639 
640 #define	RDMA_CORR_CTRL_REG		0x4910
641 #define	RDMA_CORR_CTRL_REG2		0x48a0
642 #define	RDMA_CORR_CTRL_BLEN_BD_4K	0x00030000
643 #define	RDMA_CORR_CTRL_BLEN_LSO_4K	0x000c0000
644 #define	RDMA_CORR_CTRL_TX_LENGTH_WA	0x02000000
645 
646 #define	BGE_NUM_RDMA_CHANNELS		4
647 #define	BGE_RDMA_LENGTH			0x4be0
648 
649 /*
650  * Other bits in some of the above state machine control registers
651  */
652 
653 /*
654  * Transmit MAC Mode Register
655  * (TRANSMIT_MAC_MODE_REG, 0x045c)
656  */
657 #define	TRANSMIT_MODE_MBUF_LOCKUP_FIX	0x00000100
658 #define	TRANSMIT_MODE_LONG_PAUSE	0x00000040
659 #define	TRANSMIT_MODE_BIG_BACKOFF	0x00000020
660 #define	TRANSMIT_MODE_FLOW_CONTROL	0x00000010
661 
662 /*
663  * Receive MAC Mode Register
664  * (RECEIVE_MAC_MODE_REG, 0x0468)
665  */
666 #define	RECEIVE_MODE_KEEP_VLAN_TAG	0x00000400
667 #define	RECEIVE_MODE_NO_CRC_CHECK	0x00000200
668 #define	RECEIVE_MODE_PROMISCUOUS	0x00000100
669 #define	RECEIVE_MODE_LENGTH_CHECK	0x00000080
670 #define	RECEIVE_MODE_ACCEPT_RUNTS	0x00000040
671 #define	RECEIVE_MODE_ACCEPT_OVERSIZE	0x00000020
672 #define	RECEIVE_MODE_KEEP_PAUSE		0x00000010
673 #define	RECEIVE_MODE_FLOW_CONTROL	0x00000004
674 
675 /*
676  * Receive BD Initiator Mode Register
677  * (RCV_BD_INITIATOR_MODE_REG, 0x2c00)
678  *
679  * Each of these bits controls whether ATTN is asserted
680  * on a particular condition
681  */
682 #define	RCV_BD_DISABLED_RING_ATTN	0x00000004
683 
684 /*
685  * Receive Data & Receive BD Initiator Mode Register
686  * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400)
687  *
688  * Each of these bits controls whether ATTN is asserted
689  * on a particular condition
690  */
691 #define	RCV_DATA_BD_ILL_RING_ATTN	0x00000010
692 #define	RCV_DATA_BD_FRAME_SIZE_ATTN	0x00000008
693 #define	RCV_DATA_BD_NEED_JUMBO_ATTN	0x00000004
694 
695 #define	RCV_DATA_BD_ALL_ATTN_BITS	0x0000001c
696 
697 /*
698  * Host Coalescing Mode Control Register
699  * (HOST_COALESCE_MODE_REG, 0x3c00)
700  */
701 #define	COALESCE_64_BYTE_RINGS		12
702 #define	COALESCE_NO_INT_ON_COAL_FORCE	0x00001000
703 #define	COALESCE_NO_INT_ON_DMAD_FORCE	0x00000800
704 #define	COALESCE_CLR_TICKS_TX		0x00000400
705 #define	COALESCE_CLR_TICKS_RX		0x00000200
706 #define	COALESCE_32_BYTE_STATUS		0x00000100
707 #define	COALESCE_64_BYTE_STATUS		0x00000080
708 #define	COALESCE_NOW			0x00000008
709 
710 /*
711  * Memory Arbiter Mode Register
712  * (MEMORY_ARBITER_MODE_REG, 0x4000)
713  */
714 #define	MEMORY_ARBITER_ENABLE		0x00000002
715 
716 /*
717  * Buffer Manager Mode Register
718  * (BUFFER_MANAGER_MODE_REG, 0x4400)
719  *
720  * In addition to the usual error-attn common to most state machines
721  * this register has a separate bit for attn on running-low-on-mbufs
722  */
723 #define	BUFF_MGR_TEST_MODE		0x00000008
724 #define	BUFF_MGR_MBUF_LOW_ATTN_ENABLE	0x00000010
725 
726 #define	BUFF_MGR_ALL_ATTN_BITS		0x00000014
727 
728 /*
729  * Read and Write DMA Mode Registers (READ_DMA_MODE_REG,
730  * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00)
731  *
732  * These registers each contain a 2-bit priority field, which controls
733  * the relative priority of that type of DMA (read vs. write vs. MSI),
734  * and a set of bits that control whether ATTN is asserted on each
735  * particular condition
736  */
737 #define	DMA_PRIORITY_MASK		0xc0000000
738 #define	DMA_PRIORITY_SHIFT		30
739 #define	ALL_DMA_ATTN_BITS		0x000003fc
740 
741 /*
742  * BCM5755, 5755M, 5906, 5906M only
743  * 1 - Enable Fix. Device will send out the status block before
744  *     the interrupt message
745  * 0 - Disable fix. Device will send out the interrupt message
746  *     before the status block
747  */
748 #define	DMA_STATUS_TAG_FIX_CQ12384	0x20000000
749 
750 /*
751  * End of state machine control register definitions
752  */
753 
754 
755 /*
756  * High priority mailbox registers.
757  * Mailbox Registers (8 bytes each, but high half unused)
758  */
759 #define	INTERRUPT_MBOX_0_REG		0x0200
760 #define	INTERRUPT_MBOX_1_REG		0x0208
761 #define	INTERRUPT_MBOX_2_REG		0x0210
762 #define	INTERRUPT_MBOX_3_REG		0x0218
763 #define	INTERRUPT_MBOX_REG(n)		(0x0200+8*(n))
764 
765 /*
766  * Low priority mailbox registers, for BCM5906, BCM5906M.
767  */
768 #define	INTERRUPT_LP_MBOX_0_REG		0x5800
769 
770 /*
771  * Ring Producer/Consumer Index (Mailbox) Registers
772  */
773 #define	RECV_STD_PROD_INDEX_REG		0x0268
774 #define	RECV_JUMBO_PROD_INDEX_REG	0x0270
775 #define	RECV_MINI_PROD_INDEX_REG	0x0278
776 #define	RECV_RING_CONS_INDEX_REGS	0x0280
777 #define	SEND_RING_HOST_PROD_INDEX_REGS	0x0300
778 #define	SEND_RING_NIC_PROD_INDEX_REGS	0x0380
779 
780 #define	RECV_RING_CONS_INDEX_REG(ring)	(0x0280+8*(ring))
781 #define	SEND_RING_HOST_INDEX_REG(ring)	(0x0300+8*(ring))
782 #define	SEND_RING_NIC_INDEX_REG(ring)	(0x0380+8*(ring))
783 
784 /*
785  * Ethernet MAC Mode Register
786  */
787 #define	ETHERNET_MAC_MODE_REG		0x0400
788 #define	ETHERNET_MODE_APE_TX_EN		0x10000000
789 #define	ETHERNET_MODE_APE_RX_EN		0x08000000
790 #define	ETHERNET_MODE_ENABLE_FHDE	0x00800000
791 #define	ETHERNET_MODE_ENABLE_RDE	0x00400000
792 #define	ETHERNET_MODE_ENABLE_TDE	0x00200000
793 #define	ETHERNET_MODE_ENABLE_MIP	0x00100000
794 #define	ETHERNET_MODE_ENABLE_ACPI	0x00080000
795 #define	ETHERNET_MODE_ENABLE_MAGIC_PKT	0x00040000
796 #define	ETHERNET_MODE_SEND_CFGS		0x00020000
797 #define	ETHERNET_MODE_FLUSH_TX_STATS	0x00010000
798 #define	ETHERNET_MODE_CLEAR_TX_STATS	0x00008000
799 #define	ETHERNET_MODE_ENABLE_TX_STATS	0x00004000
800 #define	ETHERNET_MODE_FLUSH_RX_STATS	0x00002000
801 #define	ETHERNET_MODE_CLEAR_RX_STATS	0x00001000
802 #define	ETHERNET_MODE_ENABLE_RX_STATS	0x00000800
803 #define	ETHERNET_MODE_LINK_POLARITY	0x00000400
804 #define	ETHERNET_MODE_MAX_DEFER		0x00000200
805 #define	ETHERNET_MODE_ENABLE_TX_BURST	0x00000100
806 #define	ETHERNET_MODE_TAGGED_MODE	0x00000080
807 #define	ETHERNET_MODE_MAC_LOOPBACK	0x00000010
808 #define	ETHERNET_MODE_PORTMODE_MASK	0x0000000c
809 #define	ETHERNET_MODE_PORTMODE_TBI	0x0000000c
810 #define	ETHERNET_MODE_PORTMODE_GMII	0x00000008
811 #define	ETHERNET_MODE_PORTMODE_MII	0x00000004
812 #define	ETHERNET_MODE_PORTMODE_NONE	0x00000000
813 #define	ETHERNET_MODE_HALF_DUPLEX	0x00000002
814 #define	ETHERNET_MODE_GLOBAL_RESET	0x00000001
815 
816 /*
817  * Ethernet MAC Status & Event Registers
818  */
819 #define	ETHERNET_MAC_STATUS_REG		0x0404
820 #define	ETHERNET_STATUS_MI_INT		0x00800000
821 #define	ETHERNET_STATUS_MI_COMPLETE	0x00400000
822 #define	ETHERNET_STATUS_LINK_CHANGED	0x00001000
823 #define	ETHERNET_STATUS_PCS_ERROR	0x00000400
824 #define	ETHERNET_STATUS_SYNC_CHANGED	0x00000010
825 #define	ETHERNET_STATUS_CFG_CHANGED	0x00000008
826 #define	ETHERNET_STATUS_RECEIVING_CFG	0x00000004
827 #define	ETHERNET_STATUS_SIGNAL_DETECT	0x00000002
828 #define	ETHERNET_STATUS_PCS_SYNCHED	0x00000001
829 
830 #define	ETHERNET_MAC_EVENT_ENABLE_REG	0x0408
831 #define	ETHERNET_EVENT_MI_INT		0x00800000
832 #define	ETHERNET_EVENT_LINK_INT		0x00001000
833 #define	ETHERNET_STATUS_PCS_ERROR_INT	0x00000400
834 
835 /*
836  * Ethernet MAC LED Control Register
837  *
838  * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and
839  * the external LED driver circuitry is wired up to assume that this mode
840  * will always be selected.  Software must not change it!
841  */
842 #define	ETHERNET_MAC_LED_CONTROL_REG	0x040c
843 #define	LED_CONTROL_OVERRIDE_BLINK	0x80000000
844 #define	LED_CONTROL_BLINK_PERIOD_MASK	0x7ff80000
845 #define	LED_CONTROL_LED_MODE_MASK	0x00001800
846 #define	LED_CONTROL_LED_MODE_5700	0x00000000
847 #define	LED_CONTROL_LED_MODE_PHY_1	0x00000800	/* mandatory	*/
848 #define	LED_CONTROL_LED_MODE_PHY_2	0x00001000
849 #define	LED_CONTROL_LED_MODE_RESERVED	0x00001800
850 #define	LED_CONTROL_TRAFFIC_LED_STATUS	0x00000400
851 #define	LED_CONTROL_10MBPS_LED_STATUS	0x00000200
852 #define	LED_CONTROL_100MBPS_LED_STATUS	0x00000100
853 #define	LED_CONTROL_1000MBPS_LED_STATUS	0x00000080
854 #define	LED_CONTROL_BLINK_TRAFFIC	0x00000040
855 #define	LED_CONTROL_TRAFFIC_LED		0x00000020
856 #define	LED_CONTROL_OVERRIDE_TRAFFIC	0x00000010
857 #define	LED_CONTROL_10MBPS_LED		0x00000008
858 #define	LED_CONTROL_100MBPS_LED		0x00000004
859 #define	LED_CONTROL_1000MBPS_LED	0x00000002
860 #define	LED_CONTROL_OVERRIDE_LINK	0x00000001
861 #define	LED_CONTROL_DEFAULT		0x02000800
862 
863 /*
864  * MAC Address registers
865  *
866  * These four eight-byte registers each hold one unicast address
867  * (six bytes), right justified & zero-filled on the left.
868  * They will normally all be set to the same value, as a station
869  * usually only has one h/w address.  The value in register 0 is
870  * used for pause packets; any of the four can be specified for
871  * substitution into other transmitted packets if required.
872  */
873 #define	MAC_ADDRESS_0_REG		0x0410
874 #define	MAC_ADDRESS_1_REG		0x0418
875 #define	MAC_ADDRESS_2_REG		0x0420
876 #define	MAC_ADDRESS_3_REG		0x0428
877 
878 #define	MAC_ADDRESS_REG(n)		(0x0410+8*(n))
879 #define	MAC_ADDRESS_REGS_MAX		4
880 
881 /*
882  * More MAC Registers ...
883  */
884 #define	MAC_TX_RANDOM_BACKOFF_REG	0x0438
885 #define	MAC_RX_MTU_SIZE_REG		0x043c
886 #define	MAC_RX_MTU_DEFAULT		0x000005f2	/* 1522	*/
887 #define	MAC_TX_LENGTHS_REG		0x0464
888 #define	MAC_TX_LENGTHS_DEFAULT		0x00002620
889 
890 /*
891  * MII access registers
892  */
893 #define	MI_COMMS_REG			0x044c
894 #define	MI_COMMS_START			0x20000000
895 #define	MI_COMMS_READ_FAILED		0x10000000
896 #define	MI_COMMS_COMMAND_MASK		0x0c000000
897 #define	MI_COMMS_COMMAND_READ		0x08000000
898 #define	MI_COMMS_COMMAND_WRITE		0x04000000
899 #define	MI_COMMS_ADDRESS_MASK		0x03e00000
900 #define	MI_COMMS_ADDRESS_SHIFT		21
901 #define	MI_COMMS_REGISTER_MASK		0x001f0000
902 #define	MI_COMMS_REGISTER_SHIFT		16
903 #define	MI_COMMS_DATA_MASK		0x0000ffff
904 #define	MI_COMMS_DATA_SHIFT		0
905 
906 #define	MI_STATUS_REG			0x0450
907 #define	MI_STATUS_10MBPS		0x00000002
908 #define	MI_STATUS_LINK			0x00000001
909 
910 #define	MI_MODE_REG			0x0454
911 #define	MI_MODE_CLOCK_MASK		0x001f0000
912 #define	MI_MODE_AUTOPOLL		0x00000010
913 #define	MI_MODE_POLL_SHORT_PREAMBLE	0x00000002
914 #define	MI_MODE_DEFAULT			0x000c0000
915 
916 #define	MI_AUTOPOLL_STATUS_REG		0x0458
917 #define	MI_AUTOPOLL_ERROR		0x00000001
918 
919 #define	TRANSMIT_MAC_STATUS_REG		0x0460
920 #define	TRANSMIT_STATUS_ODI_OVERRUN	0x00000020
921 #define	TRANSMIT_STATUS_ODI_UNDERRUN	0x00000010
922 #define	TRANSMIT_STATUS_LINK_UP		0x00000008
923 #define	TRANSMIT_STATUS_SENT_XON	0x00000004
924 #define	TRANSMIT_STATUS_SENT_XOFF	0x00000002
925 #define	TRANSMIT_STATUS_RCVD_XOFF	0x00000001
926 
927 #define	RECEIVE_MAC_STATUS_REG		0x046c
928 #define	RECEIVE_STATUS_RCVD_XON		0x00000004
929 #define	RECEIVE_STATUS_RCVD_XOFF	0x00000002
930 #define	RECEIVE_STATUS_SENT_XOFF	0x00000001
931 
932 /*
933  * These four-byte registers constitute a hash table for deciding
934  * whether to accept incoming multicast packets.  The bits are
935  * numbered in big-endian fashion, from hash 0 => the MSB of
936  * register 0 to hash 127 => the LSB of the highest-numbered
937  * register.
938  *
939  * NOTE: the 5704 can use a 256-bit table (registers 0-7) if
940  * enabled by setting the appropriate bit in the Rx MAC mode
941  * register.  Otherwise, and on all earlier chips, the table
942  * is only 128 bits (registers 0-3).
943  */
944 #define	MAC_HASH_0_REG			0x0470
945 #define	MAC_HASH_1_REG			0x0474
946 #define	MAC_HASH_2_REG			0x0478
947 #define	MAC_HASH_3_REG			0x047c
948 #define	MAC_HASH_4_REG			0x????
949 #define	MAC_HASH_5_REG			0x????
950 #define	MAC_HASH_6_REG			0x????
951 #define	MAC_HASH_7_REG			0x????
952 #define	MAC_HASH_REG(n)			(0x470+4*(n))
953 
954 /*
955  * Receive Rules Registers: 16 pairs of control+mask/value pairs
956  */
957 #define	RCV_RULES_CONTROL_0_REG		0x0480
958 #define	RCV_RULES_MASK_0_REG		0x0484
959 #define	RCV_RULES_CONTROL_15_REG	0x04f8
960 #define	RCV_RULES_MASK_15_REG		0x04fc
961 #define	RCV_RULES_CONFIG_REG		0x0500
962 #define	RCV_RULES_CONFIG_DEFAULT	0x00000008
963 
964 #define	RECV_RULES_NUM_MAX		16
965 #define	RECV_RULE_CONTROL_REG(rule)	(RCV_RULES_CONTROL_0_REG+8*(rule))
966 #define	RECV_RULE_MASK_REG(rule)	(RCV_RULES_MASK_0_REG+8*(rule))
967 
968 #define	RECV_RULE_CTL_ENABLE		0x80000000
969 #define	RECV_RULE_CTL_AND		0x40000000
970 #define	RECV_RULE_CTL_P1		0x20000000
971 #define	RECV_RULE_CTL_P2		0x10000000
972 #define	RECV_RULE_CTL_P3		0x08000000
973 #define	RECV_RULE_CTL_MASK		0x04000000
974 #define	RECV_RULE_CTL_DISCARD		0x02000000
975 #define	RECV_RULE_CTL_MAP		0x01000000
976 #define	RECV_RULE_CTL_RESV_BITS		0x00fc0000
977 #define	RECV_RULE_CTL_OP		0x00030000
978 #define	RECV_RULE_CTL_OP_EQ		0x00000000
979 #define	RECV_RULE_CTL_OP_NEQ		0x00010000
980 #define	RECV_RULE_CTL_OP_GREAT		0x00020000
981 #define	RECV_RULE_CTL_OP_LESS		0x00030000
982 #define	RECV_RULE_CTL_HEADER		0x0000e000
983 #define	RECV_RULE_CTL_HEADER_FRAME	0x00000000
984 #define	RECV_RULE_CTL_HEADER_IP		0x00002000
985 #define	RECV_RULE_CTL_HEADER_TCP	0x00004000
986 #define	RECV_RULE_CTL_HEADER_UDP	0x00006000
987 #define	RECV_RULE_CTL_HEADER_DATA	0x00008000
988 #define	RECV_RULE_CTL_CLASS_BITS	0x00001f00
989 #define	RECV_RULE_CTL_CLASS(ring)	(((ring) << 8) & \
990 					    RECV_RULE_CTL_CLASS_BITS)
991 #define	RECV_RULE_CTL_OFFSET		0x000000ff
992 
993 /*
994  * Receive Rules definition
995  */
996 #define	ETHERHEADER_DEST_OFFSET		0x00
997 #define	IPHEADER_PROTO_OFFSET		0x08
998 #define	IPHEADER_SIP_OFFSET		0x0c
999 #define	IPHEADER_DIP_OFFSET		0x10
1000 #define	TCPHEADER_SPORT_OFFSET		0x00
1001 #define	TCPHEADER_DPORT_OFFSET		0x02
1002 #define	UDPHEADER_SPORT_OFFSET		0x00
1003 #define	UDPHEADER_DPORT_OFFSET		0x02
1004 
1005 #define	RULE_MATCH(ring)	(RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \
1006 				    RECV_RULE_CTL_CLASS((ring)))
1007 
1008 #define	RULE_MATCH_MASK(ring)	(RULE_MATCH(ring) | RECV_RULE_CTL_MASK)
1009 
1010 #define	RULE_DEST_MAC_1(ring)	(RULE_MATCH(ring) | \
1011 				    RECV_RULE_CTL_HEADER_FRAME | \
1012 				    ETHERHEADER_DEST_OFFSET)
1013 
1014 #define	RULE_DEST_MAC_2(ring)	(RULE_MATCH_MASK(ring) | \
1015 				    RECV_RULE_CTL_HEADER_FRAME | \
1016 				    ETHERHEADER_DEST_OFFSET + 4)
1017 
1018 #define	RULE_LOCAL_IP(ring)	(RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \
1019 				    IPHEADER_DIP_OFFSET)
1020 
1021 #define	RULE_REMOTE_IP(ring)	(RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \
1022 				    IPHEADER_SIP_OFFSET)
1023 
1024 #define	RULE_IP_PROTO(ring)	(RULE_MATCH_MASK(ring) | \
1025 				    RECV_RULE_CTL_HEADER_IP | \
1026 				    IPHEADER_PROTO_OFFSET)
1027 
1028 #define	RULE_TCP_SPORT(ring)	(RULE_MATCH_MASK(ring) | \
1029 				    RECV_RULE_CTL_HEADER_TCP | \
1030 				    TCPHEADER_SPORT_OFFSET)
1031 
1032 #define	RULE_TCP_DPORT(ring)	(RULE_MATCH_MASK(ring) | \
1033 				    RECV_RULE_CTL_HEADER_TCP | \
1034 				    TCPHEADER_DPORT_OFFSET)
1035 
1036 #define	RULE_UDP_SPORT(ring)	(RULE_MATCH_MASK(ring) | \
1037 				    RECV_RULE_CTL_HEADER_UDP | \
1038 				    UDPHEADER_SPORT_OFFSET)
1039 
1040 #define	RULE_UDP_DPORT(ring)	(RULE_MATCH_MASK(ring) | \
1041 				    RECV_RULE_CTL_HEADER_UDP | \
1042 				    UDPHEADER_DPORT_OFFSET)
1043 
1044 /*
1045  * 1000BaseX low-level access registers
1046  */
1047 #define	MAC_GIGABIT_PCS_TEST_REG	0x0440
1048 #define	MAC_GIGABIT_PCS_TEST_ENABLE	0x00100000
1049 #define	MAC_GIGABIT_PCS_TEST_PATTERN	0x000fffff
1050 #define	TX_1000BASEX_AUTONEG_REG	0x0444
1051 #define	RX_1000BASEX_AUTONEG_REG	0x0448
1052 
1053 /*
1054  * Autoneg code bits for the 1000BASE-X AUTONEG registers
1055  */
1056 #define	AUTONEG_CODE_PAUSE		0x00008000
1057 #define	AUTONEG_CODE_HALF_DUPLEX	0x00004000
1058 #define	AUTONEG_CODE_FULL_DUPLEX	0x00002000
1059 #define	AUTONEG_CODE_NEXT_PAGE		0x00000080
1060 #define	AUTONEG_CODE_ACKNOWLEDGE	0x00000040
1061 #define	AUTONEG_CODE_FAULT_MASK		0x00000030
1062 #define	AUTONEG_CODE_FAULT_ANEG_ERR	0x00000030
1063 #define	AUTONEG_CODE_FAULT_LINK_FAIL	0x00000020
1064 #define	AUTONEG_CODE_FAULT_OFFLINE	0x00000010
1065 #define	AUTONEG_CODE_ASYM_PAUSE		0x00000001
1066 
1067 /*
1068  * SerDes Registers (5703S/5704S only)
1069  */
1070 #define	SERDES_CONTROL_REG		0x0590
1071 #define	SERDES_CONTROL_TBI_LOOPBACK	0x00020000
1072 #define	SERDES_CONTROL_COMMA_DETECT	0x00010000
1073 #define	SERDES_CONTROL_TX_DISABLE	0x00004000
1074 #define	SERDES_STATUS_REG		0x0594
1075 #define	SERDES_STATUS_COMMA_DETECTED	0x00000100
1076 #define	SERDES_STATUS_RXSTAT		0x000000ff
1077 
1078 /* 5780/5714 only */
1079 #define SERDES_RX_CONTROL		0x000005b0
1080 #define SERDES_RX_CONTROL_SIG_DETECT	0x00000400
1081 
1082 /*
1083  * SGMII Status Register (5717/18/19/20 only)
1084  */
1085 #define	SGMII_STATUS_REG	0x5B4
1086 #define	MEDIA_SELECTION_MODE	0x00000100
1087 
1088 /*
1089  * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only)
1090  */
1091 #define	STAT_IFHCOUT_OCTETS_REG		0x0800
1092 #define	STAT_ETHER_COLLIS_REG		0x0808
1093 #define	STAT_OUTXON_SENT_REG		0x080c
1094 #define	STAT_OUTXOFF_SENT_REG		0x0810
1095 #define	STAT_DOT3_INTMACTX_ERR_REG		0x0818
1096 #define	STAT_DOT3_SCOLLI_FRAME_REG		0x081c
1097 #define	STAT_DOT3_MCOLLI_FRAME_REG		0x0820
1098 #define	STAT_DOT3_DEFERED_TX_REG		0x0824
1099 #define	STAT_DOT3_EXCE_COLLI_REG		0x082c
1100 #define	STAT_DOT3_LATE_COLLI_REG		0x0830
1101 #define	STAT_IFHCOUT_UPKGS_REG		0x086c
1102 #define	STAT_IFHCOUT_MPKGS_REG		0x0870
1103 #define	STAT_IFHCOUT_BPKGS_REG		0x0874
1104 
1105 #define	STAT_IFHCIN_OCTETS_REG		0x0880
1106 #define	STAT_ETHER_FRAGMENT_REG		0x0888
1107 #define	STAT_IFHCIN_UPKGS_REG		0x088c
1108 #define	STAT_IFHCIN_MPKGS_REG		0x0890
1109 #define	STAT_IFHCIN_BPKGS_REG		0x0894
1110 
1111 #define	STAT_DOT3_FCS_ERR_REG		0x0898
1112 #define	STAT_DOT3_ALIGN_ERR_REG		0x089c
1113 #define	STAT_XON_PAUSE_RX_REG		0x08a0
1114 #define	STAT_XOFF_PAUSE_RX_REG		0x08a4
1115 #define	STAT_MAC_CTRL_RX_REG		0x08a8
1116 #define	STAT_XOFF_STATE_ENTER_REG		0x08ac
1117 #define	STAT_DOT3_FRAME_TOOLONG_REG		0x08b0
1118 #define	STAT_ETHER_JABBERS_REG		0x08b4
1119 #define	STAT_ETHER_UNDERSIZE_REG		0x08b8
1120 #define	SIZE_OF_STATISTIC_REG		0x1B
1121 /*
1122  * Send Data Initiator Registers
1123  */
1124 #define	SEND_INIT_STATS_CONTROL_REG	0x0c08
1125 #define	SEND_INIT_STATS_ZERO		0x00000010
1126 #define	SEND_INIT_STATS_FLUSH		0x00000008
1127 #define	SEND_INIT_STATS_CLEAR		0x00000004
1128 #define	SEND_INIT_STATS_FASTER		0x00000002
1129 #define	SEND_INIT_STATS_ENABLE		0x00000001
1130 
1131 #define	SEND_INIT_STATS_ENABLE_MASK_REG	0x0c0c
1132 
1133 /*
1134  * Send Buffer Descriptor Selector Control Registers
1135  */
1136 #define	SEND_BD_SELECTOR_STATUS_REG	0x1404
1137 #define	SEND_BD_SELECTOR_HWDIAG_REG	0x1408
1138 #define	SEND_BD_SELECTOR_INDEX_REG(n)	(0x1440+4*(n))
1139 
1140 /*
1141  * Receive List Placement Registers
1142  */
1143 #define	RCV_LP_CONFIG_REG		0x2010
1144 #define	RCV_LP_CONFIG_DEFAULT		0x00000009
1145 #define	RCV_LP_CONFIG(rings)		(((rings) << 3) | 0x1)
1146 
1147 #define	RCV_LP_STATS_CONTROL_REG	0x2014
1148 #define	RCV_LP_STATS_ZERO		0x00000010
1149 #define	RCV_LP_STATS_FLUSH		0x00000008
1150 #define	RCV_LP_STATS_CLEAR		0x00000004
1151 #define	RCV_LP_STATS_FASTER		0x00000002
1152 #define	RCV_LP_STATS_ENABLE		0x00000001
1153 
1154 #define	RCV_LP_STATS_ENABLE_MASK_REG	0x2018
1155 #define	RCV_LP_STATS_DISABLE_MACTQ	0x040000
1156 
1157 /*
1158  * Receive Data & BD Initiator Registers
1159  */
1160 #define	RCV_INITIATOR_STATUS_REG	0x2404
1161 
1162 /*
1163  * Receive Buffer Descriptor Ring Control Block Registers
1164  * NB: sixteen bytes (128 bits) each
1165  */
1166 #define	JUMBO_RCV_BD_RING_RCB_REG	0x2440
1167 #define	STD_RCV_BD_RING_RCB_REG		0x2450
1168 #define	MINI_RCV_BD_RING_RCB_REG	0x2460
1169 
1170 /*
1171  * Receive Buffer Descriptor Ring Replenish Threshold Registers
1172  */
1173 #define	MINI_RCV_BD_REPLENISH_REG	0x2c14
1174 #define	MINI_RCV_BD_REPLENISH_DEFAULT	0x00000080	/* 128	*/
1175 #define	STD_RCV_BD_REPLENISH_REG	0x2c18
1176 #define	STD_RCV_BD_REPLENISH_DEFAULT	0x00000002	/* 2	*/
1177 #define	JUMBO_RCV_BD_REPLENISH_REG	0x2c1c
1178 #define	JUMBO_RCV_BD_REPLENISH_DEFAULT	0x00000020	/* 32	*/
1179 
1180 /*
1181  * CPMU registers (5717/18/19/20/57765 only)
1182  */
1183 #define	CPMU_CLCK_ORIDE_REG		0x3624
1184 #define	CPMU_CLCK_ORIDE_MAC_ORIDE_EN	0x80000000
1185 #define	CPMU_STATUS_REG			0x362c
1186 #define	CPMU_STATUS_FUNC_NUM		0x20000000
1187 #define	CPMU_STATUS_FUNC_NUM_SHIFT	29
1188 #define	CPMU_STATUS_FUNC_NUM_5719	0xc0000000
1189 #define	CPMU_STATUS_FUNC_NUM_5719_SHIFT	30
1190 #define	CPMU_PADRNG_CTL_REG		0x3668
1191 #define	CPMU_PADRNG_CTL_RDIV2		0x00040000
1192 
1193 /*
1194  * EEE registers (5718/19/20 only)
1195  */
1196 #define	EEE_MODE_REG			0x36b0
1197 #define	EEE_MODE_APE_TX_DET_EN		0x00000004
1198 #define	EEE_MODE_ERLY_L1_XIT_DET	0x00000008
1199 #define	EEE_MODE_SND_IDX_DET_EN		0x00000040
1200 #define	EEE_MODE_LPI_ENABLE		0x00000080
1201 #define	EEE_MODE_LPI_IN_TX		0x00000100
1202 #define	EEE_MODE_LPI_IN_RX		0x00000200
1203 #define	EEE_MODE_EEE_ENABLE		0x00100000
1204 
1205 #define	EEE_DEBOUNCE_T1_CONTROL_REG	0x36b4
1206 #define	EEE_DEBOUNCE_T1_PCIEXIT_2047US	0x07ff0000
1207 #define	EEE_DEBOUNCE_T1_LNKIDLE_2047US	0x000007ff
1208 
1209 #define	EEE_DEBOUNCE_T2_CONTROL_REG	0x36b8
1210 #define	EEE_DEBOUNCE_T2_APE_TX_2047US	0x07ff0000
1211 #define	EEE_DEBOUNCE_T2_TXIDXEQ_2047US	0x000007ff
1212 
1213 #define	EEE_LINK_IDLE_CONTROL_REG	0x36bc
1214 #define	EEE_LINK_IDLE_PCIE_NL0		0x01000000
1215 #define	EEE_LINK_IDLE_UART_IDL		0x00000004
1216 #define	EEE_LINK_IDLE_APE_TX_MT		0x00000002
1217 
1218 #define	EEE_CONTROL_REG			0x36d0
1219 #define	EEE_CONTROL_EXIT_16_5_US	0x0000019d
1220 #define	EEE_CONTROL_EXIT_36_US		0x00000384
1221 #define	EEE_CONTROL_EXIT_20_1_US	0x000001f8
1222 
1223 /* Clause 45 expansion registers */
1224 #define	EEE_CL45_D7_RESULT_STAT			0x803e
1225 #define	EEE_CL45_D7_RESULT_STAT_LP_100TX	0x0002
1226 #define	EEE_CL45_D7_RESULT_STAT_LP_1000T	0x0004
1227 
1228 #define MDIO_MMD_AN			0x0007
1229 #define MDIO_AN_EEE_ADV			0x003c
1230 
1231 /*
1232  * Host Coalescing Engine Control Registers
1233  */
1234 #define	RCV_COALESCE_TICKS_REG		0x3c08
1235 #define	RCV_COALESCE_TICKS_DEFAULT	0x00000096	/* 150	*/
1236 #define	SEND_COALESCE_TICKS_REG		0x3c0c
1237 #define	SEND_COALESCE_TICKS_DEFAULT	0x00000096	/* 150	*/
1238 #define	RCV_COALESCE_MAX_BD_REG		0x3c10
1239 #define	RCV_COALESCE_MAX_BD_DEFAULT	0x0000000a	/* 10	*/
1240 #define	SEND_COALESCE_MAX_BD_REG	0x3c14
1241 #define	SEND_COALESCE_MAX_BD_DEFAULT	0x0000000a	/* 10	*/
1242 #define	RCV_COALESCE_INT_TICKS_REG	0x3c18
1243 #define	RCV_COALESCE_INT_TICKS_DEFAULT	0x00000000	/* 0	*/
1244 #define	SEND_COALESCE_INT_TICKS_REG	0x3c1c
1245 #define	SEND_COALESCE_INT_TICKS_DEFAULT	0x00000000	/* 0	*/
1246 #define	RCV_COALESCE_INT_BD_REG		0x3c20
1247 #define	RCV_COALESCE_INT_BD_DEFAULT	0x00000000	/* 0	*/
1248 #define	SEND_COALESCE_INT_BD_REG	0x3c24
1249 #define	SEND_COALESCE_INT_BD_DEFAULT	0x00000000	/* 0	*/
1250 #define	STATISTICS_TICKS_REG		0x3c28
1251 #define	STATISTICS_TICKS_DEFAULT	0x000f4240	/* 1000000 */
1252 #define	STATISTICS_HOST_ADDR_REG	0x3c30
1253 #define	STATUS_BLOCK_HOST_ADDR_REG	0x3c38
1254 #define	STATISTICS_BASE_ADDR_REG	0x3c40
1255 #define	STATUS_BLOCK_BASE_ADDR_REG	0x3c44
1256 #define	FLOW_ATTN_REG			0x3c48
1257 
1258 #define	NIC_JUMBO_RECV_INDEX_REG	0x3c50
1259 #define	NIC_STD_RECV_INDEX_REG		0x3c54
1260 #define	NIC_MINI_RECV_INDEX_REG		0x3c58
1261 #define	NIC_DIAG_RETURN_INDEX_REG(n)	(0x3c80+4*(n))
1262 #define	NIC_DIAG_SEND_INDEX_REG(n)	(0x3cc0+4*(n))
1263 
1264 /*
1265  * Mbuf Pool Initialisation & Watermark Registers
1266  *
1267  * There are some conflicts in the PRM; compare the recommendations
1268  * on pp. 115, 236, and 339.  The values here were recommended by
1269  * dkim@broadcom.com (and the PRM should be corrected soon ;-)
1270  */
1271 #define	BUFFER_MANAGER_STATUS_REG	0x4404
1272 #define	MBUF_POOL_BASE_REG		0x4408
1273 #define	MBUF_POOL_BASE_DEFAULT		0x00008000
1274 #define	MBUF_POOL_BASE_5721		0x00010000
1275 #define	MBUF_POOL_BASE_5704		0x00010000
1276 #define	MBUF_POOL_BASE_5705		0x00010000
1277 #define	MBUF_POOL_LENGTH_REG		0x440c
1278 #define	MBUF_POOL_LENGTH_DEFAULT	0x00018000
1279 #define	MBUF_POOL_LENGTH_5704		0x00010000
1280 #define	MBUF_POOL_LENGTH_5705		0x00008000
1281 #define	MBUF_POOL_LENGTH_5721		0x00008000
1282 #define	RDMA_MBUF_LOWAT_REG		0x4410
1283 #define	RDMA_MBUF_LOWAT_DEFAULT		0x00000050
1284 #define	RDMA_MBUF_LOWAT_5705		0x00000000
1285 #define	RDMA_MBUF_LOWAT_5906		0x00000000
1286 #define	RDMA_MBUF_LOWAT_JUMBO		0x00000130
1287 #define	RDMA_MBUF_LOWAT_5714_JUMBO	0x00000000
1288 #define	MAC_RX_MBUF_LOWAT_REG		0x4414
1289 #define	MAC_RX_MBUF_LOWAT_DEFAULT	0x00000020
1290 #define	MAC_RX_MBUF_LOWAT_5705		0x00000010
1291 #define	MAC_RX_MBUF_LOWAT_5906		0x00000004
1292 #define	MAC_RX_MBUF_LOWAT_5717		0x0000002a
1293 #define	MAC_RX_MBUF_LOWAT_JUMBO		0x00000098
1294 #define	MAC_RX_MBUF_LOWAT_5714_JUMBO	0x0000004b
1295 #define	MBUF_HIWAT_REG			0x4418
1296 #define	MBUF_HIWAT_DEFAULT		0x00000060
1297 #define	MBUF_HIWAT_5705			0x00000060
1298 #define	MBUF_HIWAT_5906			0x00000010
1299 #define	MBUF_HIWAT_5717			0x000000a0
1300 #define	MBUF_HIWAT_JUMBO		0x0000017c
1301 #define	MBUF_HIWAT_5714_JUMBO		0x00000096
1302 
1303 /*
1304  * DMA Descriptor Pool Initialisation & Watermark Registers
1305  */
1306 #define	DMAD_POOL_BASE_REG		0x442c
1307 #define	DMAD_POOL_BASE_DEFAULT		0x00002000
1308 #define	DMAD_POOL_LENGTH_REG		0x4430
1309 #define	DMAD_POOL_LENGTH_DEFAULT	0x00002000
1310 #define	DMAD_POOL_LOWAT_REG		0x4434
1311 #define	DMAD_POOL_LOWAT_DEFAULT		0x00000005	/* 5	*/
1312 #define	DMAD_POOL_HIWAT_REG		0x4438
1313 #define	DMAD_POOL_HIWAT_DEFAULT		0x0000000a	/* 10	*/
1314 
1315 /*
1316  * More threshold/watermark registers ...
1317  */
1318 #define	RECV_FLOW_THRESHOLD_REG		0x4458
1319 #define	LOWAT_MAX_RECV_FRAMES_REG	0x0504
1320 #define	LOWAT_MAX_RECV_FRAMES_DEFAULT	0x00000002
1321 
1322 /*
1323  * Read/Write DMA Status Registers
1324  */
1325 #define	READ_DMA_STATUS_REG		0x4804
1326 #define	WRITE_DMA_STATUS_REG		0x4c04
1327 
1328 /*
1329  * RX/TX RISC Registers
1330  */
1331 #define	RX_RISC_MODE_REG		0x5000
1332 #define	RX_RISC_STATE_REG		0x5004
1333 #define	RX_RISC_PC_REG			0x501c
1334 #define	TX_RISC_MODE_REG		0x5400
1335 #define	TX_RISC_STATE_REG		0x5404
1336 #define	TX_RISC_PC_REG			0x541c
1337 
1338 /*
1339  * V? RISC Registerss
1340  */
1341 #define	VCPU_STATUS_REG			0x5100
1342 #define	VCPU_INIT_DONE			0x04000000
1343 #define	VCPU_DRV_RESET			0x08000000
1344 
1345 #define	VCPU_EXT_CTL			0x6890
1346 #define	VCPU_EXT_CTL_HALF		0x00400000
1347 
1348 #define	FTQ_RESET_REG			0x5c00
1349 
1350 #define	MSI_MODE_REG			0x6000
1351 #define	MSI_PRI_HIGHEST			0xc0000000
1352 #define	MSI_MSI_ENABLE			0x00000002
1353 #define	MSI_ERROR_ATTENTION		0x0000001c
1354 
1355 #define	MSI_STATUS_REG			0x6004
1356 
1357 #define	MODE_CONTROL_REG		0x6800
1358 #define	MODE_ROUTE_MCAST_TO_RX_RISC	0x40000000
1359 #define	MODE_4X_NIC_SEND_RINGS		0x20000000
1360 #define	MODE_INT_ON_FLOW_ATTN		0x10000000
1361 #define	MODE_INT_ON_DMA_ATTN		0x08000000
1362 #define	MODE_INT_ON_MAC_ATTN		0x04000000
1363 #define	MODE_INT_ON_RXRISC_ATTN		0x02000000
1364 #define	MODE_INT_ON_TXRISC_ATTN		0x01000000
1365 #define	MODE_RECV_NO_PSEUDO_HDR_CSUM	0x00800000
1366 #define	MODE_SEND_NO_PSEUDO_HDR_CSUM	0x00100000
1367 #define	MODE_HOST_SEND_BDS		0x00020000
1368 #define	MODE_HOST_STACK_UP		0x00010000
1369 #define	MODE_FORCE_32_BIT_PCI		0x00008000
1370 #define	MODE_NO_INT_ON_RECV		0x00004000
1371 #define	MODE_NO_INT_ON_SEND		0x00002000
1372 #define	MODE_ALLOW_BAD_FRAMES		0x00000800
1373 #define	MODE_NO_CRC			0x00000400
1374 #define	MODE_NO_FRAME_CRACKING		0x00000200
1375 #define	MODE_WORD_SWAP_FRAME		0x00000020
1376 #define	MODE_BYTE_SWAP_FRAME		0x00000010
1377 #define	MODE_WORD_SWAP_NONFRAME		0x00000004
1378 #define	MODE_BYTE_SWAP_NONFRAME		0x00000002
1379 #define	MODE_UPDATE_ON_COAL_ONLY	0x00000001
1380 
1381 /*
1382  * Miscellaneous Configuration Register
1383  *
1384  * This contains various bits relating to power control (which differ
1385  * among different members of the chip family), but the important bits
1386  * for our purposes are the RESET bit and the Timer Prescaler field.
1387  *
1388  * The RESET bit in this register serves to reset the whole chip, even
1389  * including the PCI interface(!)  Once it's set, the chip will not
1390  * respond to ANY accesses -- not even CONFIG space -- until the reset
1391  * completes internally.  According to the PRM, this should take less
1392  * than 100us.  Any access during this period will get a bus error.
1393  *
1394  * The Timer Prescaler field must be programmed so that the timer period
1395  * is as near as possible to 1us.  The value in this field should be
1396  * the Core Clock frequency in MHz minus 1.  From my reading of the PRM,
1397  * the Core Clock should always be 66MHz (independently of the bus speed,
1398  * at least for PCI rather than PCI-X), so this register must be set to
1399  * the value 0x82 ((66-1) << 1).
1400  */
1401 #define	CORE_CLOCK_MHZ			66
1402 #define	MISC_CONFIG_REG			0x6804
1403 #define	MISC_CONFIG_GRC_RESET_DISABLE   0x20000000
1404 #define	MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000
1405 #define	MISC_CONFIG_POWERDOWN		0x00100000
1406 #define	MISC_CONFIG_POWER_STATE		0x00060000
1407 #define	MISC_CONFIG_PRESCALE_MASK	0x000000fe
1408 #define	MISC_CONFIG_RESET_BIT		0x00000001
1409 #define	MISC_CONFIG_DEFAULT		(((CORE_CLOCK_MHZ)-1) << 1)
1410 #define	MISC_CONFIG_EPHY_IDDQ		0x00200000
1411 
1412 /*
1413  * Miscellaneous Local Control Register (MLCR)
1414  */
1415 #define	MISC_LOCAL_CONTROL_REG		0x6808
1416 
1417 #define	MLCR_PCI_CTRL_SELECT		0x10000000
1418 #define	MLCR_LEGACY_PCI_MODE		0x08000000
1419 #define	MLCR_AUTO_SEEPROM_ACCESS	0x01000000
1420 #define	MLCR_SSRAM_CYCLE_DESELECT	0x00800000
1421 #define	MLCR_SSRAM_TYPE			0x00400000
1422 #define	MLCR_BANK_SELECT		0x00200000
1423 
1424 #define	MLCR_SRAM_SIZE_16M		0x00180000
1425 #define	MLCR_SRAM_SIZE_8M		0x00140000
1426 #define	MLCR_SRAM_SIZE_4M		0x00100000
1427 #define	MLCR_SRAM_SIZE_2M		0x000c0000
1428 #define	MLCR_SRAM_SIZE_1M		0x00080000
1429 #define	MLCR_SRAM_SIZE_512K		0x00040000
1430 #define	MLCR_SRAM_SIZE_256K		0x00000000
1431 #define	MLCR_SRAM_SIZE_MASK		0x001c0000
1432 
1433 #define	MLCR_ENABLE_EXTERNAL_MEMORY	0x00020000
1434 #define	MLCR_MISC_PINS_OUTPUT_2		0x00010000
1435 
1436 #define	MLCR_MISC_PINS_OUTPUT_1		0x00008000
1437 #define	MLCR_MISC_PINS_OUTPUT_0		0x00004000
1438 #define	MLCR_MISC_PINS_OUTPUT_ENABLE_2	0x00002000
1439 #define	MLCR_MISC_PINS_OUTPUT_ENABLE_1	0x00001000
1440 
1441 #define	MLCR_MISC_PINS_OUTPUT_ENABLE_0	0x00000800
1442 #define	MLCR_MISC_PINS_INPUT_2		0x00000400	/* R/O	*/
1443 #define	MLCR_MISC_PINS_INPUT_1		0x00000200	/* R/O	*/
1444 #define	MLCR_MISC_PINS_INPUT_0		0x00000100	/* R/O	*/
1445 
1446 #define	MLCR_GPIO_OUTPUT3		0x00000080
1447 #define	MLCR_GPIO_OE3			0x00000040
1448 #define	MLCR_USE_EXT_SIG_DETECT		0x00000020	/* 5714/5780 only */
1449 #define	MLCR_GPIO_INPUT3		0x00000020
1450 #define	MLCR_GPIO_UART_SEL		0x00000010	/* 5755 only */
1451 #define	MLCR_USE_SIG_DETECT		0x00000010	/* 5714/5780 only */
1452 
1453 #define	MLCR_INT_ON_ATTN		0x00000008	/* R/W	*/
1454 #define	MLCR_SET_INT			0x00000004	/* W/O	*/
1455 #define	MLCR_CLR_INT			0x00000002	/* W/O	*/
1456 #define	MLCR_INTA_STATE			0x00000001	/* R/O	*/
1457 
1458 /*
1459  * This value defines all GPIO bits as INPUTS, but sets their default
1460  * values as outputs to HIGH, on the assumption that external circuits
1461  * (if any) will probably be active-LOW with passive pullups.
1462  *
1463  * The Claymore blade uses GPIO1 to control writing to the SEEPROM in
1464  * just this fashion.  It has to be set as an OUTPUT and driven LOW to
1465  * enable writing.  Otherwise, the SEEPROM is protected.
1466  */
1467 #define	MLCR_DEFAULT			(MLCR_AUTO_SEEPROM_ACCESS | \
1468 					 MLCR_MISC_PINS_OUTPUT_2  | \
1469 					 MLCR_MISC_PINS_OUTPUT_1  | \
1470 					 MLCR_MISC_PINS_OUTPUT_0)
1471 
1472 #define	MLCR_DEFAULT_5714		(MLCR_PCI_CTRL_SELECT     | \
1473 					 MLCR_LEGACY_PCI_MODE     | \
1474 					 MLCR_AUTO_SEEPROM_ACCESS | \
1475 					 MLCR_MISC_PINS_OUTPUT_2  | \
1476 					 MLCR_MISC_PINS_OUTPUT_1  | \
1477 					 MLCR_MISC_PINS_OUTPUT_0  | \
1478 					 MLCR_USE_SIG_DETECT)
1479 
1480 #define	MLCR_DEFAULT_5717		(MLCR_AUTO_SEEPROM_ACCESS)
1481 
1482 /*
1483  * MLCR_AUTO_SEEPROM_ACCESS is marked reserved in the 57765 family, so we don't
1484  * try to enable it like on the 5717.
1485  */
1486 #define	MLCR_DEFAULT_57765		0
1487 
1488 /*
1489  * Serial EEPROM Data/Address Registers (auto-access mode)
1490  */
1491 #define	SERIAL_EEPROM_DATA_REG		0x683c
1492 #define	SERIAL_EEPROM_ADDRESS_REG	0x6838
1493 #define	SEEPROM_ACCESS_READ		0x80000000
1494 #define	SEEPROM_ACCESS_WRITE		0x00000000
1495 #define	SEEPROM_ACCESS_COMPLETE		0x40000000
1496 #define	SEEPROM_ACCESS_RESET		0x20000000
1497 #define	SEEPROM_ACCESS_DEVID_MASK	0x1c000000
1498 #define	SEEPROM_ACCESS_START		0x02000000
1499 #define	SEEPROM_ACCESS_HALFCLOCK_MASK	0x01ff0000
1500 #define	SEEPROM_ACCESS_ADDRESS_MASK	0x0000fffc
1501 
1502 #define	SEEPROM_ACCESS_DEVID_SHIFT	26		/* bits	*/
1503 #define	SEEPROM_ACCESS_HALFCLOCK_SHIFT	16		/* bits */
1504 #define	SEEPROM_ACCESS_ADDRESS_SIZE	16		/* bits	*/
1505 
1506 #define	SEEPROM_ACCESS_HALFCLOCK_340KHZ	0x0060		/* 340kHz */
1507 #define	SEEPROM_ACCESS_INIT		0x20600000	/* reset+clock	*/
1508 
1509 /*
1510  * "Linearised" address mask, treating multiple devices as consecutive
1511  */
1512 #define	SEEPROM_DEV_AND_ADDR_MASK	0x0007fffc	/* 8x64k devices */
1513 
1514 /*
1515  * Non-Volatile Memory Interface Registers
1516  * Note: on chips that support the flash interface (5702+), flash is the
1517  * default and the legacy seeprom interface must be explicitly enabled
1518  * if required. On older chips (5700/01), SEEPROM is the default (and
1519  * only) non-volatile memory available, and these registers don't exist!
1520  */
1521 #define	NVM_FLASH_CMD_REG		0x7000
1522 #define	NVM_FLASH_CMD_LAST		0x00000100
1523 #define	NVM_FLASH_CMD_FIRST		0x00000080
1524 #define	NVM_FLASH_CMD_RD		0x00000000
1525 #define	NVM_FLASH_CMD_WR		0x00000020
1526 #define	NVM_FLASH_CMD_DOIT		0x00000010
1527 #define	NVM_FLASH_CMD_DONE		0x00000008
1528 
1529 #define	NVM_FLASH_WRITE_REG		0x7008
1530 #define	NVM_FLASH_READ_REG		0x7010
1531 
1532 #define	NVM_FLASH_ADDR_REG		0x700c
1533 #define	NVM_FLASH_ADDR_MASK		0x00fffffc
1534 
1535 #define	NVM_CONFIG1_REG			0x7014
1536 #define	NVM_CFG1_LEGACY_SEEPROM_MODE	0x80000000
1537 #define	NVM_CFG1_SEE_CLK_DIV_MASK	0x003ff800
1538 #define	NVM_CFG1_SPI_CLK_DIV_MASK	0x00000780
1539 #define	NVM_CFG1_BUFFERED_MODE		0x00000002
1540 #define	NVM_CFG1_FLASH_MODE		0x00000001
1541 
1542 #define	NVM_SW_ARBITRATION_REG		0x7020
1543 #define	NVM_READ_REQ3			0x00008000
1544 #define	NVM_READ_REQ2			0x00004000
1545 #define	NVM_READ_REQ1			0x00002000
1546 #define	NVM_READ_REQ0			0x00001000
1547 #define	NVM_WON_REQ3			0x00000800
1548 #define	NVM_WON_REQ2			0x00000400
1549 #define	NVM_WON_REQ1			0x00000200
1550 #define	NVM_WON_REQ0			0x00000100
1551 #define	NVM_RESET_REQ3			0x00000080
1552 #define	NVM_RESET_REQ2			0x00000040
1553 #define	NVM_RESET_REQ1			0x00000020
1554 #define	NVM_RESET_REQ0			0x00000010
1555 #define	NVM_SET_REQ3			0x00000008
1556 #define	NVM_SET_REQ2			0x00000004
1557 #define	NVM_SET_REQ1			0x00000002
1558 #define	NVM_SET_REQ0			0x00000001
1559 
1560 #define	EEPROM_MAGIC			0x669955aa
1561 #define	EEPROM_MAGIC_FW			0xa5000000
1562 #define	EEPROM_MAGIC_FW_MSK		0xff000000
1563 #define	EEPROM_SB_FORMAT_MASK		0x00e00000
1564 #define	EEPROM_SB_FORMAT_1		0x00200000
1565 #define	EEPROM_SB_REVISION_MASK		0x001f0000
1566 #define	EEPROM_SB_REVISION_0		0x00000000
1567 #define	EEPROM_SB_REVISION_2		0x00020000
1568 #define	EEPROM_SB_REVISION_3		0x00030000
1569 #define	EEPROM_SB_REVISION_4		0x00040000
1570 #define	EEPROM_SB_REVISION_5		0x00050000
1571 #define	EEPROM_SB_REVISION_6		0x00060000
1572 #define	EEPROM_MAGIC_HW			0xabcd
1573 #define	EEPROM_MAGIC_HW_MSK		0xffff
1574 
1575 #define	NVM_DIR_START		0x18
1576 #define	NVM_DIR_END		0x78
1577 #define	NVM_DIRENT_SIZE		0xc
1578 #define	NVM_DIRTYPE_SHIFT	24
1579 #define	NVM_DIRTYPE_LENMSK	0x003fffff
1580 #define	NVM_DIRTYPE_ASFINI	1
1581 #define	NVM_DIRTYPE_EXTVPD	20
1582 #define	NVM_PTREV_BCVER		0x94
1583 #define	NVM_BCVER_MAJMSK	0x0000ff00
1584 #define	NVM_BCVER_MAJSFT	8
1585 #define	NVM_BCVER_MINMSK	0x000000ff
1586 
1587 /*
1588  * NVM access register
1589  * Applicable to BCM5721,BCM5751,BCM5752,BCM5714,BCM57725
1590  * and BCM5715 only.
1591  */
1592 #define	NVM_ACCESS_REG			0x7024
1593 #define	NVM_WRITE_ENABLE		0x00000002
1594 #define	NVM_ACCESS_ENABLE		0x00000001
1595 
1596 /*
1597  * TLP Control Register
1598  * Applicable to BCM5721 and BCM5751 only
1599  */
1600 #define	TLP_CONTROL_REG			0x7c00
1601 #define	TLP_DATA_FIFO_PROTECT		0x02000000
1602 
1603 /*
1604  * PHY Test Control Register
1605  * Applicable to BCM5721 and BCM5751 only
1606  */
1607 #define	PHY_TEST_CTRL_REG		0x7e2c
1608 #define	PHY_PCIE_SCRAM_MODE		0x20
1609 #define	PHY_PCIE_LTASS_MODE		0x40
1610 
1611 /*
1612  * The internal firmware expects a certain layout of the non-volatile
1613  * memory (if fitted), and will check for it during startup, and use the
1614  * contents to initialise various internal parameters if it looks good.
1615  *
1616  * The offsets and field definitions below refer to where to find some
1617  * important values, and how to interpret them ...
1618  */
1619 #define	NVMEM_DATA_MAC_ADDRESS		0x007c		/* 8 bytes	*/
1620 #define	NVMEM_DATA_MAC_ADDRESS_5906	0x0010		/* 8 bytes	*/
1621 
1622 /*
1623  * Vendor-specific MII registers
1624  */
1625 
1626 #define	MII_MMD_CTRL			0x0d /* MMD Access Control register */
1627 #define	MII_MMD_CTRL_DATA_NOINC		0x4000
1628 #define	MII_MMD_ADDRESS_DATA		0x0e /* MMD Address Data register */
1629 
1630 #define	MII_RXR_COUNTERS		0x14 /* Local/Remote Rx Counts */
1631 #define	MII_DSP_RW_PORT			0x15 /* DSP read/write port */
1632 #define	MII_DSP_CONTROL			0x16 /* DSP control register */
1633 #define	MII_DSP_ADDRESS			0x17 /* DSP address register */
1634 
1635 #define	MII_DSP_TAP26			0x001a
1636 #define	MII_DSP_TAP26_ALNOKO		0x0001
1637 #define	MII_DSP_TAP26_RMRXSTO		0x0002
1638 #define	MII_DSP_TAP26_OPCSINPT		0x0004
1639 
1640 #define	MII_DSP_CH34TP2			0x4022
1641 #define	MII_DSP_CH34TP2_HIBW01		0x017b
1642 
1643 #define	MII_EXT_CONTROL			MII_VENDOR(0)
1644 #define	MII_EXT_STATUS			MII_VENDOR(1)
1645 #define	MII_RCV_ERR_COUNT		MII_VENDOR(2)
1646 #define	MII_FALSE_CARR_COUNT		MII_VENDOR(3)
1647 #define	MII_RCV_NOT_OK_COUNT		MII_VENDOR(4)
1648 #define	MII_AUX_CONTROL			MII_VENDOR(8)
1649 #define	MII_AUX_STATUS			MII_VENDOR(9)
1650 #define	MII_INTR_STATUS			MII_VENDOR(10)
1651 #define	MII_INTR_MASK			MII_VENDOR(11)
1652 #define	MII_HCD_STATUS			MII_VENDOR(13)
1653 
1654 #define	MII_MAXREG			MII_VENDOR(15)	/* 31, 0x1f	*/
1655 
1656 /*
1657  * Bits in the MII_EXT_CONTROL register
1658  */
1659 #define	MII_EXT_CTRL_INTERFACE_TBI	0x8000
1660 #define	MII_EXT_CTRL_DISABLE_AUTO_MDIX	0x4000
1661 #define	MII_EXT_CTRL_DISABLE_TRANSMIT	0x2000
1662 #define	MII_EXT_CTRL_DISABLE_INTERRUPT	0x1000
1663 #define	MII_EXT_CTRL_FORCE_INTERRUPT	0x0800
1664 #define	MII_EXT_CTRL_BYPASS_4B5B	0x0400
1665 #define	MII_EXT_CTRL_BYPASS_SCRAMBLER	0x0200
1666 #define	MII_EXT_CTRL_BYPASS_MLT3	0x0100
1667 #define	MII_EXT_CTRL_BYPASS_RX_ALIGN	0x0080
1668 #define	MII_EXT_CTRL_RESET_SCRAMBLER	0x0040
1669 #define	MII_EXT_CTRL_LED_TRAFFIC_MODE	0x0020
1670 #define	MII_EXT_CTRL_FORCE_LEDS_ON	0x0010
1671 #define	MII_EXT_CTRL_FORCE_LEDS_OFF	0x0008
1672 #define	MII_EXT_CTRL_EXTEND_TX_IPG	0x0004
1673 #define	MII_EXT_CTRL_3LINK_LED_MODE	0x0002
1674 #define	MII_EXT_CTRL_FIFO_ELASTICITY	0x0001
1675 
1676 /*
1677  * Bits in the MII_EXT_STATUS register
1678  */
1679 #define	MII_EXT_STAT_S3MII_FIFO_ERROR	0x8000
1680 #define	MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000
1681 #define	MII_EXT_STAT_MDIX_STATE		0x2000
1682 #define	MII_EXT_STAT_INTERRUPT_STATUS	0x1000
1683 #define	MII_EXT_STAT_REMOTE_RCVR_STATUS	0x0800
1684 #define	MII_EXT_STAT_LOCAL_RDVR_STATUS	0x0400
1685 #define	MII_EXT_STAT_DESCRAMBLER_LOCKED	0x0200
1686 #define	MII_EXT_STAT_LINK_STATUS	0x0100
1687 #define	MII_EXT_STAT_CRC_ERROR		0x0080
1688 #define	MII_EXT_STAT_CARR_EXT_ERROR	0x0040
1689 #define	MII_EXT_STAT_BAD_SSD_ERROR	0x0020
1690 #define	MII_EXT_STAT_BAD_ESD_ERROR	0x0010
1691 #define	MII_EXT_STAT_RECEIVE_ERROR	0x0008
1692 #define	MII_EXT_STAT_TRANSMIT_ERROR	0x0004
1693 #define	MII_EXT_STAT_LOCK_ERROR		0x0002
1694 #define	MII_EXT_STAT_MLT3_CODE_ERROR	0x0001
1695 
1696 /*
1697  * The AUX CONTROL register is seriously weird!
1698  *
1699  * It hides (up to) eight 'shadow' registers.  When writing, which one
1700  * of them is written is determined by the low-order bits of the data
1701  * written(!), but when reading, which one is read is determined by the
1702  * value previously written to (part of) one of the shadow registers!!!
1703  */
1704 
1705 /*
1706  * Shadow register numbers
1707  */
1708 #define	MII_AUX_CTRL_NORMAL		0
1709 #define	MII_AUX_CTRL_10BASE_T		1
1710 #define	MII_AUX_CTRL_POWER		2
1711 #define	MII_AUX_CTRL_TEST_1		4
1712 #define	MII_AUX_CTRL_MISC		7
1713 
1714 /*
1715  * Selected bits in some of the shadow registers ...
1716  */
1717 #define	MII_AUX_CTRL_NORM_EXT_LOOPBACK	0x8000
1718 #define	MII_AUX_CTRL_NORM_LONG_PKTS	0x4000
1719 #define	MII_AUX_CTRL_NORM_EDGE_CTRL	0x3000
1720 #define	MII_AUX_CTRL_NORM_TX_MODE	0x0400
1721 #define	MII_AUX_CTRL_NORM_CABLE_TEST	0x0008
1722 
1723 #define	MII_AUX_CTRL_TEST_TX_HALF	0x0008
1724 
1725 #define	MII_AUX_CTRL_MISC_WRITE_ENABLE	0x8000
1726 #define	MII_AUX_CTRL_MISC_WIRE_SPEED	0x0010
1727 
1728 #define	MII_AUX_CTRL_TX_6DB		0x0400
1729 #define	MII_AUX_CTRL_SMDSP_ENA		0x0800
1730 
1731 /*
1732  * Write this value to the AUX control register
1733  * to select which shadow register will be read
1734  */
1735 #define	MII_AUX_CTRL_SHADOW_READ(x)	(((x) << 12) | MII_AUX_CTRL_MISC)
1736 
1737 /*
1738  * Bits in the MII_AUX_STATUS register
1739  */
1740 #define	MII_AUX_STATUS_MODE_MASK	0x0700
1741 #define	MII_AUX_STATUS_MODE_1000_F	0x0700
1742 #define	MII_AUX_STATUS_MODE_1000_H	0x0600
1743 #define	MII_AUX_STATUS_MODE_100_F	0x0500
1744 #define	MII_AUX_STATUS_MODE_100_4	0x0400
1745 #define	MII_AUX_STATUS_MODE_100_H	0x0300
1746 #define	MII_AUX_STATUS_MODE_10_F	0x0200
1747 #define	MII_AUX_STATUS_MODE_10_H	0x0100
1748 #define	MII_AUX_STATUS_MODE_NONE	0x0000
1749 #define	MII_AUX_STATUS_MODE_SHIFT	8
1750 
1751 #define	MII_AUX_STATUS_PAR_FAULT	0x0080
1752 #define	MII_AUX_STATUS_REM_FAULT	0x0040
1753 #define	MII_AUX_STATUS_LP_ANEG_ABLE	0x0010
1754 #define	MII_AUX_STATUS_LP_NP_ABLE	0x0008
1755 
1756 #define	MII_AUX_STATUS_LINKUP		0x0004
1757 #define	MII_AUX_STATUS_RX_PAUSE		0x0002
1758 #define	MII_AUX_STATUS_TX_PAUSE		0x0001
1759 
1760 #define	MII_AUX_STATUS_SPEED_IND_5906	0x0008
1761 #define	MII_AUX_STATUS_NEG_ENABLED_5906		0x0002
1762 #define	MII_AUX_STATUS_DUPLEX_IND_5906		0x0001
1763 
1764 /*
1765  * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers
1766  */
1767 #define	MII_INTR_RMT_RX_STATUS_CHANGE	0x0020
1768 #define	MII_INTR_LCL_RX_STATUS_CHANGE	0x0010
1769 #define	MII_INTR_LINK_DUPLEX_CHANGE	0x0008
1770 #define	MII_INTR_LINK_SPEED_CHANGE	0x0004
1771 #define	MII_INTR_LINK_STATUS_CHANGE	0x0002
1772 
1773 
1774 /*
1775  * Third section:
1776  *	Hardware-defined data structures
1777  *
1778  * Note that the chip is naturally BIG-endian, so, for a big-endian
1779  * host, the structures defined below match those described in the PRM.
1780  * For little-endian hosts, some structures have to be swapped around.
1781  */
1782 
1783 #if	!defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN)
1784 #error	Host endianness not defined
1785 #endif
1786 
1787 /*
1788  * Architectural constants: absolute maximum numbers of each type of ring
1789  */
1790 #ifdef BGE_EXT_MEM
1791 #define	BGE_SEND_RINGS_MAX		16	/* only with ext mem	*/
1792 #else
1793 #define	BGE_SEND_RINGS_MAX		4
1794 #endif
1795 #define	BGE_SEND_RINGS_MAX_5705		1
1796 #define	BGE_RECV_RINGS_MAX		16
1797 #define	BGE_RECV_RINGS_MAX_5705		1
1798 #define	BGE_BUFF_RINGS_MAX		3	/* jumbo/std/mini (mini	*/
1799 						/* only with ext mem)	*/
1800 
1801 #define	BGE_SEND_SLOTS_MAX		512
1802 #define	BGE_STD_SLOTS_MAX		512
1803 #define	BGE_JUMBO_SLOTS_MAX		256
1804 #define	BGE_MINI_SLOTS_MAX		1024
1805 #define	BGE_RECV_SLOTS_MAX		2048
1806 #define	BGE_RECV_SLOTS_5705		512
1807 #define	BGE_RECV_SLOTS_5782		512
1808 #define	BGE_RECV_SLOTS_5721		512
1809 
1810 /*
1811  * Hardware-defined Ring Control Block
1812  */
1813 typedef struct {
1814 	uint64_t	host_ring_addr;
1815 #ifdef	_BIG_ENDIAN
1816 	uint16_t	max_len;
1817 	uint16_t	flags;
1818 	uint32_t	nic_ring_addr;
1819 #else
1820 	uint32_t	nic_ring_addr;
1821 	uint16_t	flags;
1822 	uint16_t	max_len;
1823 #endif	/* _BIG_ENDIAN */
1824 } bge_rcb_t;
1825 
1826 #define	RCB_FLAG_USE_EXT_RCV_BD		0x0001
1827 #define	RCB_FLAG_RING_DISABLED		0x0002
1828 
1829 /*
1830  * Hardware-defined Send Buffer Descriptor
1831  */
1832 typedef struct {
1833 	uint64_t	host_buf_addr;
1834 #ifdef	_BIG_ENDIAN
1835 	uint16_t	len;
1836 	uint16_t	flags;
1837 	uint16_t	reserved;
1838 	uint16_t	vlan_tci;
1839 #else
1840 	uint16_t	vlan_tci;
1841 	uint16_t	reserved;
1842 	uint16_t	flags;
1843 	uint16_t	len;
1844 #endif	/* _BIG_ENDIAN */
1845 } bge_sbd_t;
1846 
1847 #define	SBD_FLAG_TCP_UDP_CKSUM		0x0001
1848 #define	SBD_FLAG_IP_CKSUM		0x0002
1849 #define	SBD_FLAG_PACKET_END		0x0004
1850 #define	SBD_FLAG_IP_FRAG		0x0008
1851 #define	SBD_FLAG_JMB_PKT		0x0008
1852 #define	SBD_FLAG_IP_FRAG_END		0x0010
1853 
1854 #define	SBD_FLAG_VLAN_TAG		0x0040
1855 #define	SBD_FLAG_COAL_NOW		0x0080
1856 #define	SBD_FLAG_CPU_PRE_DMA		0x0100
1857 #define	SBD_FLAG_CPU_POST_DMA		0x0200
1858 
1859 #define	SBD_FLAG_INSERT_SRC_ADDR	0x1000
1860 #define	SBD_FLAG_CHOOSE_SRC_ADDR	0x6000
1861 #define	SBD_FLAG_DONT_GEN_CRC		0x8000
1862 
1863 /*
1864  * Hardware-defined Receive Buffer Descriptor
1865  */
1866 typedef struct {
1867 	uint64_t	host_buf_addr;
1868 #ifdef	_BIG_ENDIAN
1869 	uint16_t	index;
1870 	uint16_t	len;
1871 	uint16_t	type;
1872 	uint16_t	flags;
1873 	uint16_t	ip_cksum;
1874 	uint16_t	tcp_udp_cksum;
1875 	uint16_t	error_flag;
1876 	uint16_t	vlan_tci;
1877 	uint32_t	reserved;
1878 	uint32_t	opaque;
1879 #else
1880 	uint16_t	flags;
1881 	uint16_t	type;
1882 	uint16_t	len;
1883 	uint16_t	index;
1884 	uint16_t	vlan_tci;
1885 	uint16_t	error_flag;
1886 	uint16_t	tcp_udp_cksum;
1887 	uint16_t	ip_cksum;
1888 	uint32_t	opaque;
1889 	uint32_t	reserved;
1890 #endif	/* _BIG_ENDIAN */
1891 } bge_rbd_t;
1892 
1893 #define	RBD_FLAG_STD_RING		0x0000
1894 #define	RBD_FLAG_PACKET_END		0x0004
1895 
1896 #define	RBD_FLAG_JUMBO_RING		0x0020
1897 #define	RBD_FLAG_VLAN_TAG		0x0040
1898 
1899 #define	RBD_FLAG_FRAME_HAS_ERROR	0x0400
1900 #define	RBD_FLAG_MINI_RING		0x0800
1901 #define	RBD_FLAG_IP_CHECKSUM		0x1000
1902 #define	RBD_FLAG_TCP_UDP_CHECKSUM	0x2000
1903 #define	RBD_FLAG_TCP_UDP_IS_TCP		0x4000
1904 
1905 #define	RBD_FLAG_DEFAULT		0x0000
1906 
1907 #define	RBD_ERROR_BAD_CRC		0x00010000
1908 #define	RBD_ERROR_COLL_DETECT		0x00020000
1909 #define	RBD_ERROR_LINK_LOST		0x00040000
1910 #define	RBD_ERROR_PHY_DECODE_ERR	0x00080000
1911 #define	RBD_ERROR_ODD_NIBBLE_RX_MII	0x00100000
1912 #define	RBD_ERROR_MAC_ABORT		0x00200000
1913 #define	RBD_ERROR_LEN_LESS_64		0x00400000
1914 #define	RBD_ERROR_TRUNC_NO_RES		0x00800000
1915 #define	RBD_ERROR_GIANT_PKT_RCVD	0x01000000
1916 
1917 /*
1918  * Hardware-defined Status Block,Size of status block
1919  * is actually 0x50 bytes.Use 0x80 bytes for cache line
1920  * alignment.For BCM5705/5788/5721/5751/5752/5714
1921  * and 5715,there is only 1 recv and send ring index,but
1922  * driver defined 16 indexs here,please pay attention only
1923  * one ring is enabled in these chipsets.
1924  */
1925 typedef struct {
1926 	uint64_t	flags_n_tag;
1927 	uint16_t	buff_cons_index[4];
1928 	struct {
1929 #ifdef	_BIG_ENDIAN
1930 		uint16_t	send_cons_index;
1931 		uint16_t	recv_prod_index;
1932 #else
1933 		uint16_t	recv_prod_index;
1934 		uint16_t	send_cons_index;
1935 #endif	/* _BIG_ENDIAN */
1936 	} index[16];
1937 } bge_status_t;
1938 
1939 /*
1940  * Hardware-defined Receive BD Rule
1941  */
1942 typedef struct {
1943 	uint32_t	control;
1944 	uint32_t	mask_value;
1945 } bge_recv_rule_t;
1946 
1947 /*
1948  * This describes which sub-rule slots are used by a particular rule.
1949  */
1950 typedef struct {
1951 	int		start;
1952 	int		count;
1953 } bge_rule_info_t;
1954 
1955 /*
1956  * Indexes into the <buff_cons_index> array
1957  */
1958 #ifdef	_BIG_ENDIAN
1959 #define	STATUS_STD_BUFF_CONS_INDEX	0
1960 #define	STATUS_JUMBO_BUFF_CONS_INDEX	1
1961 #define	STATUS_MINI_BUFF_CONS_INDEX	3
1962 #define	SEND_INDEX_P(bsp, ring)	(&(bsp)->index[(ring)^0].send_cons_index)
1963 #define	RECV_INDEX_P(bsp, ring)	(&(bsp)->index[(ring)^0].recv_prod_index)
1964 #else
1965 #define	STATUS_STD_BUFF_CONS_INDEX	3
1966 #define	STATUS_JUMBO_BUFF_CONS_INDEX	2
1967 #define	STATUS_MINI_BUFF_CONS_INDEX	0
1968 #define	SEND_INDEX_P(bsp, ring)	(&(bsp)->index[(ring)^1].send_cons_index)
1969 #define	RECV_INDEX_P(bsp, ring)	(&(bsp)->index[(ring)^1].recv_prod_index)
1970 #endif	/* _BIG_ENDIAN */
1971 
1972 /*
1973  * Bits in the <flags_n_tag> word
1974  */
1975 #define	STATUS_FLAG_UPDATED		0x0000000100000000ull
1976 #define	STATUS_FLAG_LINK_CHANGED	0x0000000200000000ull
1977 #define	STATUS_FLAG_ERROR		0x0000000400000000ull
1978 #define	STATUS_TAG_MASK			0x00000000000000FFull
1979 
1980 /*
1981  * The tag from the status block is fed back to Interrupt Mailbox 0
1982  * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt.  This
1983  * lets the chip know what updates have been processed, so it can
1984  * reassert its interrupt if more updates have occurred since.
1985  *
1986  * These macros extract the tag from the <flags_n_tag> word, shift
1987  * it to the proper position in the Mailbox register, and provide
1988  * the complete values to write to INTERRUPT_MBOX_0_REG to disable
1989  * or enable interrupts
1990  */
1991 #define	STATUS_TAG(fnt)			((fnt) & STATUS_TAG_MASK)
1992 #define	INTERRUPT_TAG(fnt)		(STATUS_TAG(fnt) << 24)
1993 #define	INTERRUPT_MBOX_DISABLE(fnt)	(INTERRUPT_TAG(fnt) | 1)
1994 #define	INTERRUPT_MBOX_ENABLE(fnt)	(INTERRUPT_TAG(fnt) | 0)
1995 
1996 /*
1997  * Hardware-defined Statistics Block Offsets
1998  *
1999  * These are given in the manual as addresses in NIC memory, starting
2000  * from the NIC statistics area base address of 0x300; but here we
2001  * convert them into indexes into an array of (uint64_t)s, so we can
2002  * use them directly for accessing the copy of the statistics block
2003  * that the chip DMAs into main memory ...
2004  */
2005 
2006 #define	KS_BASE				0x300
2007 #define	KS_ADDR(x)			(((x)-KS_BASE)/sizeof (uint64_t))
2008 
2009 typedef enum {
2010 	KS_ifHCInOctets = KS_ADDR(0x400),
2011 	KS_etherStatsFragments = KS_ADDR(0x410),
2012 	KS_ifHCInUcastPkts,
2013 	KS_ifHCInMulticastPkts,
2014 	KS_ifHCInBroadcastPkts,
2015 	KS_dot3StatsFCSErrors,
2016 	KS_dot3StatsAlignmentErrors,
2017 	KS_xonPauseFramesReceived,
2018 	KS_xoffPauseFramesReceived,
2019 	KS_macControlFramesReceived,
2020 	KS_xoffStateEntered,
2021 	KS_dot3StatsFrameTooLongs,
2022 	KS_etherStatsJabbers,
2023 	KS_etherStatsUndersizePkts,
2024 	KS_inRangeLengthError,
2025 	KS_outRangeLengthError,
2026 	KS_etherStatsPkts64Octets,
2027 	KS_etherStatsPkts65to127Octets,
2028 	KS_etherStatsPkts128to255Octets,
2029 	KS_etherStatsPkts256to511Octets,
2030 	KS_etherStatsPkts512to1023Octets,
2031 	KS_etherStatsPkts1024to1518Octets,
2032 	KS_etherStatsPkts1519to2047Octets,
2033 	KS_etherStatsPkts2048to4095Octets,
2034 	KS_etherStatsPkts4096to8191Octets,
2035 	KS_etherStatsPkts8192to9022Octets,
2036 
2037 	KS_ifHCOutOctets = KS_ADDR(0x600),
2038 	KS_etherStatsCollisions = KS_ADDR(0x610),
2039 	KS_outXonSent,
2040 	KS_outXoffSent,
2041 	KS_flowControlDone,
2042 	KS_dot3StatsInternalMacTransmitErrors,
2043 	KS_dot3StatsSingleCollisionFrames,
2044 	KS_dot3StatsMultipleCollisionFrames,
2045 	KS_dot3StatsDeferredTransmissions,
2046 	KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658),
2047 	KS_dot3StatsLateCollisions,
2048 	KS_dot3Collided2Times,
2049 	KS_dot3Collided3Times,
2050 	KS_dot3Collided4Times,
2051 	KS_dot3Collided5Times,
2052 	KS_dot3Collided6Times,
2053 	KS_dot3Collided7Times,
2054 	KS_dot3Collided8Times,
2055 	KS_dot3Collided9Times,
2056 	KS_dot3Collided10Times,
2057 	KS_dot3Collided11Times,
2058 	KS_dot3Collided12Times,
2059 	KS_dot3Collided13Times,
2060 	KS_dot3Collided14Times,
2061 	KS_dot3Collided15Times,
2062 	KS_ifHCOutUcastPkts,
2063 	KS_ifHCOutMulticastPkts,
2064 	KS_ifHCOutBroadcastPkts,
2065 	KS_dot3StatsCarrierSenseErrors,
2066 	KS_ifOutDiscards,
2067 	KS_ifOutErrors,
2068 
2069 	KS_COSIfHCInPkts_1 = KS_ADDR(0x800),		/* [16]	*/
2070 	KS_COSIfHCInPkts_2,
2071 	KS_COSIfHCInPkts_3,
2072 	KS_COSIfHCInPkts_4,
2073 	KS_COSIfHCInPkts_5,
2074 	KS_COSIfHCInPkts_6,
2075 	KS_COSIfHCInPkts_7,
2076 	KS_COSIfHCInPkts_8,
2077 	KS_COSIfHCInPkts_9,
2078 	KS_COSIfHCInPkts_10,
2079 	KS_COSIfHCInPkts_11,
2080 	KS_COSIfHCInPkts_12,
2081 	KS_COSIfHCInPkts_13,
2082 	KS_COSIfHCInPkts_14,
2083 	KS_COSIfHCInPkts_15,
2084 	KS_COSIfHCInPkts_16,
2085 	KS_COSFramesDroppedDueToFilters,
2086 	KS_nicDmaWriteQueueFull,
2087 	KS_nicDmaWriteHighPriQueueFull,
2088 	KS_nicNoMoreRxBDs,
2089 	KS_ifInDiscards,
2090 	KS_ifInErrors,
2091 	KS_nicRecvThresholdHit,
2092 
2093 	KS_COSIfHCOutPkts_1 = KS_ADDR(0x900),		/* [16]	*/
2094 	KS_COSIfHCOutPkts_2,
2095 	KS_COSIfHCOutPkts_3,
2096 	KS_COSIfHCOutPkts_4,
2097 	KS_COSIfHCOutPkts_5,
2098 	KS_COSIfHCOutPkts_6,
2099 	KS_COSIfHCOutPkts_7,
2100 	KS_COSIfHCOutPkts_8,
2101 	KS_COSIfHCOutPkts_9,
2102 	KS_COSIfHCOutPkts_10,
2103 	KS_COSIfHCOutPkts_11,
2104 	KS_COSIfHCOutPkts_12,
2105 	KS_COSIfHCOutPkts_13,
2106 	KS_COSIfHCOutPkts_14,
2107 	KS_COSIfHCOutPkts_15,
2108 	KS_COSIfHCOutPkts_16,
2109 	KS_nicDmaReadQueueFull,
2110 	KS_nicDmaReadHighPriQueueFull,
2111 	KS_nicSendDataCompQueueFull,
2112 	KS_nicRingSetSendProdIndex,
2113 	KS_nicRingStatusUpdate,
2114 	KS_nicInterrupts,
2115 	KS_nicAvoidedInterrupts,
2116 	KS_nicSendThresholdHit,
2117 
2118 	KS_STATS_SIZE = KS_ADDR(0xb00)
2119 } bge_stats_offset_t;
2120 
2121 /*
2122  * Hardware-defined Statistics Block
2123  *
2124  * Another view of the statistic block, as a array and a structure ...
2125  */
2126 
2127 typedef union {
2128 	uint64_t		a[KS_STATS_SIZE];
2129 	struct {
2130 		uint64_t	spare1[(0x400-0x300)/sizeof (uint64_t)];
2131 
2132 		uint64_t	ifHCInOctets;		/* 0x0400	*/
2133 		uint64_t	spare2[1];
2134 		uint64_t	etherStatsFragments;
2135 		uint64_t	ifHCInUcastPkts;
2136 		uint64_t	ifHCInMulticastPkts;
2137 		uint64_t	ifHCInBroadcastPkts;
2138 		uint64_t	dot3StatsFCSErrors;
2139 		uint64_t	dot3StatsAlignmentErrors;
2140 		uint64_t	xonPauseFramesReceived;
2141 		uint64_t	xoffPauseFramesReceived;
2142 		uint64_t	macControlFramesReceived;
2143 		uint64_t	xoffStateEntered;
2144 		uint64_t	dot3StatsFrameTooLongs;
2145 		uint64_t	etherStatsJabbers;
2146 		uint64_t	etherStatsUndersizePkts;
2147 		uint64_t	inRangeLengthError;
2148 		uint64_t	outRangeLengthError;
2149 		uint64_t	etherStatsPkts64Octets;
2150 		uint64_t	etherStatsPkts65to127Octets;
2151 		uint64_t	etherStatsPkts128to255Octets;
2152 		uint64_t	etherStatsPkts256to511Octets;
2153 		uint64_t	etherStatsPkts512to1023Octets;
2154 		uint64_t	etherStatsPkts1024to1518Octets;
2155 		uint64_t	etherStatsPkts1519to2047Octets;
2156 		uint64_t	etherStatsPkts2048to4095Octets;
2157 		uint64_t	etherStatsPkts4096to8191Octets;
2158 		uint64_t	etherStatsPkts8192to9022Octets;
2159 		uint64_t	spare3[(0x600-0x4d8)/sizeof (uint64_t)];
2160 
2161 		uint64_t	ifHCOutOctets;		/* 0x0600	*/
2162 		uint64_t	spare4[1];
2163 		uint64_t	etherStatsCollisions;
2164 		uint64_t	outXonSent;
2165 		uint64_t	outXoffSent;
2166 		uint64_t	flowControlDone;
2167 		uint64_t	dot3StatsInternalMacTransmitErrors;
2168 		uint64_t	dot3StatsSingleCollisionFrames;
2169 		uint64_t	dot3StatsMultipleCollisionFrames;
2170 		uint64_t	dot3StatsDeferredTransmissions;
2171 		uint64_t	spare5[1];
2172 		uint64_t	dot3StatsExcessiveCollisions;
2173 		uint64_t	dot3StatsLateCollisions;
2174 		uint64_t	dot3Collided2Times;
2175 		uint64_t	dot3Collided3Times;
2176 		uint64_t	dot3Collided4Times;
2177 		uint64_t	dot3Collided5Times;
2178 		uint64_t	dot3Collided6Times;
2179 		uint64_t	dot3Collided7Times;
2180 		uint64_t	dot3Collided8Times;
2181 		uint64_t	dot3Collided9Times;
2182 		uint64_t	dot3Collided10Times;
2183 		uint64_t	dot3Collided11Times;
2184 		uint64_t	dot3Collided12Times;
2185 		uint64_t	dot3Collided13Times;
2186 		uint64_t	dot3Collided14Times;
2187 		uint64_t	dot3Collided15Times;
2188 		uint64_t	ifHCOutUcastPkts;
2189 		uint64_t	ifHCOutMulticastPkts;
2190 		uint64_t	ifHCOutBroadcastPkts;
2191 		uint64_t	dot3StatsCarrierSenseErrors;
2192 		uint64_t	ifOutDiscards;
2193 		uint64_t	ifOutErrors;
2194 		uint64_t	spare6[(0x800-0x708)/sizeof (uint64_t)];
2195 
2196 		uint64_t	COSIfHCInPkts[16];	/* 0x0800	*/
2197 		uint64_t	COSFramesDroppedDueToFilters;
2198 		uint64_t	nicDmaWriteQueueFull;
2199 		uint64_t	nicDmaWriteHighPriQueueFull;
2200 		uint64_t	nicNoMoreRxBDs;
2201 		uint64_t	ifInDiscards;
2202 		uint64_t	ifInErrors;
2203 		uint64_t	nicRecvThresholdHit;
2204 		uint64_t	spare7[(0x900-0x8b8)/sizeof (uint64_t)];
2205 
2206 		uint64_t	COSIfHCOutPkts[16];	/* 0x0900	*/
2207 		uint64_t	nicDmaReadQueueFull;
2208 		uint64_t	nicDmaReadHighPriQueueFull;
2209 		uint64_t	nicSendDataCompQueueFull;
2210 		uint64_t	nicRingSetSendProdIndex;
2211 		uint64_t	nicRingStatusUpdate;
2212 		uint64_t	nicInterrupts;
2213 		uint64_t	nicAvoidedInterrupts;
2214 		uint64_t	nicSendThresholdHit;
2215 		uint64_t	spare8[(0xb00-0x9c0)/sizeof (uint64_t)];
2216 	} s;
2217 } bge_statistics_t;
2218 
2219 #define	KS_STAT_REG_SIZE	(0x1B)
2220 #define	KS_STAT_REG_BASE	(0x800)
2221 
2222 typedef struct {
2223 	uint32_t	ifHCOutOctets;
2224 	uint32_t	etherStatsCollisions;
2225 	uint32_t	outXonSent;
2226 	uint32_t	outXoffSent;
2227 	uint32_t	dot3StatsInternalMacTransmitErrors;
2228 	uint32_t	dot3StatsSingleCollisionFrames;
2229 	uint32_t	dot3StatsMultipleCollisionFrames;
2230 	uint32_t	dot3StatsDeferredTransmissions;
2231 	uint32_t	dot3StatsExcessiveCollisions;
2232 	uint32_t	dot3StatsLateCollisions;
2233 	uint32_t	ifHCOutUcastPkts;
2234 	uint32_t	ifHCOutMulticastPkts;
2235 	uint32_t	ifHCOutBroadcastPkts;
2236 	uint32_t	ifHCInOctets;
2237 	uint32_t	etherStatsFragments;
2238 	uint32_t	ifHCInUcastPkts;
2239 	uint32_t	ifHCInMulticastPkts;
2240 	uint32_t	ifHCInBroadcastPkts;
2241 	uint32_t	dot3StatsFCSErrors;
2242 	uint32_t	dot3StatsAlignmentErrors;
2243 	uint32_t	xonPauseFramesReceived;
2244 	uint32_t	xoffPauseFramesReceived;
2245 	uint32_t	macControlFramesReceived;
2246 	uint32_t	xoffStateEntered;
2247 	uint32_t	dot3StatsFrameTooLongs;
2248 	uint32_t	etherStatsJabbers;
2249 	uint32_t	etherStatsUndersizePkts;
2250 } bge_statistics_reg_t;
2251 
2252 
2253 #ifdef BGE_IPMI_ASF
2254 
2255 /*
2256  * Device internal memory entries
2257  */
2258 
2259 #define	BGE_FIRMWARE_MAILBOX				0x0b50
2260 #define	BGE_MAGIC_NUM_FIRMWARE_INIT_DONE		0x4b657654
2261 #define	BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE	0x4861764b
2262 
2263 
2264 #define	BGE_NIC_DATA_SIG_ADDR			0x0b54
2265 #define	BGE_NIC_DATA_SIG			0x4b657654
2266 
2267 
2268 #define	BGE_NIC_DATA_NIC_CFG_ADDR		0x0b58
2269 
2270 #define	BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED	0x000004
2271 #define	BGE_NIC_CFG_LED_MODE_LINK_SPEED		0x000008
2272 #define	BGE_NIC_CFG_LED_MODE_OPEN_DRAIN		0x000004
2273 #define	BGE_NIC_CFG_LED_MODE_OUTPUT		0x000008
2274 #define	BGE_NIC_CFG_LED_MODE_MASK		0x00000c
2275 
2276 #define	BGE_NIC_CFG_PHY_TYPE_UNKNOWN		0x000000
2277 #define	BGE_NIC_CFG_PHY_TYPE_COPPER		0x000010
2278 #define	BGE_NIC_CFG_PHY_TYPE_FIBER		0x000020
2279 #define	BGE_NIC_CFG_PHY_TYPE_MASK		0x000030
2280 
2281 #define	BGE_NIC_CFG_ENABLE_WOL			0x000040
2282 #define	BGE_NIC_CFG_ENABLE_ASF			0x000080
2283 #define	BGE_NIC_CFG_EEPROM_WP			0x000100
2284 #define	BGE_NIC_CFG_POWER_SAVING		0x000200
2285 #define	BGE_NIC_CFG_SWAP_PORT			0x000800
2286 #define	BGE_NIC_CFG_MINI_PCI			0x001000
2287 #define	BGE_NIC_CFG_FIBER_WOL_CAPABLE		0x004000
2288 #define	BGE_NIC_CFG_5753_12x12			0x100000
2289 
2290 
2291 #define	BGE_NIC_DATA_FIRMWARE_VERSION		0x0b5c
2292 
2293 
2294 #define	BGE_NIC_DATA_PHY_ID_ADDR		0x0b74
2295 #define	BGE_NIC_PHY_ID1_MASK			0xffff0000
2296 #define	BGE_NIC_PHY_ID2_MASK			0x0000ffff
2297 
2298 
2299 #define	BGE_CMD_MAILBOX				0x0b78
2300 #define	BGE_CMD_NICDRV_ALIVE			0x00000001
2301 #define	BGE_CMD_NICDRV_PAUSE_FW			0x00000002
2302 #define	BGE_CMD_NICDRV_IPV4ADDR_CHANGE		0x00000003
2303 #define	BGE_CMD_NICDRV_IPV6ADDR_CHANGE		0x00000004
2304 
2305 
2306 #define	BGE_CMD_LENGTH_MAILBOX			0x0b7c
2307 #define	BGE_CMD_DATA_MAILBOX			0x0b80
2308 #define	BGE_ASF_FW_STATUS_MAILBOX		0x0c00
2309 
2310 #define	BGE_DRV_STATE_MAILBOX			0x0c04
2311 #define	BGE_DRV_STATE_START			0x00000001
2312 #define	BGE_DRV_STATE_START_DONE		0x80000001
2313 #define	BGE_DRV_STATE_UNLOAD			0x00000002
2314 #define	BGE_DRV_STATE_UNLOAD_DONE		0x80000002
2315 #define	BGE_DRV_STATE_WOL			0x00000003
2316 #define	BGE_DRV_STATE_SUSPEND			0x00000004
2317 
2318 
2319 #define	BGE_FW_LAST_RESET_TYPE_MAILBOX		0x0c08
2320 #define	BGE_FW_LAST_RESET_TYPE_WARM		0x0001
2321 #define	BGE_FW_LAST_RESET_TYPE_COLD		0x0002
2322 
2323 
2324 #define	BGE_MAC_ADDR_HIGH_MAILBOX		0x0c14
2325 #define	BGE_MAC_ADDR_LOW_MAILBOX		0x0c18
2326 
2327 
2328 /*
2329  * RX-RISC event register
2330  */
2331 #define	RX_RISC_EVENT_REG			0x6810
2332 #define	RRER_ASF_EVENT				0x4000
2333 
2334 #endif /* BGE_IPMI_ASF */
2335 
2336 /* APE registers.  Accessible through BAR1 */
2337 #define	BGE_APE_GPIO_MSG		0x0008
2338 #define	BGE_APE_GPIO_MSG_SHIFT		4
2339 #define	BGE_APE_EVENT			0x000c
2340 #define	 APE_EVENT_1			 0x00000001
2341 #define	BGE_APE_LOCK_REQ		0x002c
2342 #define	 APE_LOCK_REQ_DRIVER		 0x00001000
2343 #define	BGE_APE_LOCK_GRANT		0x004c
2344 #define	 APE_LOCK_GRANT_DRIVER		 0x00001000
2345 #define	BGE_APE_STICKY_TMR		0x00b0
2346 
2347 /* APE shared memory.  Accessible through BAR1 */
2348 #define	BGE_APE_SHMEM_BASE		0x4000
2349 #define	BGE_APE_SEG_SIG			0x4000
2350 #define	 APE_SEG_SIG_MAGIC		 0x41504521
2351 #define	BGE_APE_FW_STATUS		0x400c
2352 #define	 APE_FW_STATUS_READY		 0x00000100
2353 #define	BGE_APE_FW_FEATURES		0x4010
2354 #define	 BGE_APE_FW_FEATURE_NCSI	 0x00000002
2355 #define	BGE_APE_FW_VERSION		0x4018
2356 #define	 APE_FW_VERSION_MAJMSK		 0xff000000
2357 #define	 APE_FW_VERSION_MAJSFT		 24
2358 #define	 APE_FW_VERSION_MINMSK		 0x00ff0000
2359 #define	 APE_FW_VERSION_MINSFT		 16
2360 #define	 APE_FW_VERSION_REVMSK		 0x0000ff00
2361 #define	 APE_FW_VERSION_REVSFT		 8
2362 #define	 APE_FW_VERSION_BLDMSK		 0x000000ff
2363 #define	BGE_APE_SEG_MSG_BUF_OFF		0x401c
2364 #define	BGE_APE_SEG_MSG_BUF_LEN		0x4020
2365 #define	BGE_APE_HOST_SEG_SIG		0x4200
2366 #define	 APE_HOST_SEG_SIG_MAGIC		 0x484f5354
2367 #define	BGE_APE_HOST_SEG_LEN		0x4204
2368 #define	 APE_HOST_SEG_LEN_MAGIC		 0x00000020
2369 #define	BGE_APE_HOST_INIT_COUNT		0x4208
2370 #define	BGE_APE_HOST_DRIVER_ID		0x420c
2371 #define	 APE_HOST_DRIVER_ID_SOLARIS	0xf4000000
2372 #define	 APE_HOST_DRIVER_ID_MAGIC(maj, min) \
2373 	(APE_HOST_DRIVER_ID_SOLARIS | (maj & 0xff) << 16 | (min & 0xff) << 8)
2374 #define	BGE_APE_HOST_BEHAVIOR		0x4210
2375 #define	 APE_HOST_BEHAV_NO_PHYLOCK	 0x00000001
2376 #define	BGE_APE_HOST_HEARTBEAT_INT_MS	0x4214
2377 #define	 APE_HOST_HEARTBEAT_INT_DISABLE	 0
2378 #define	 APE_HOST_HEARTBEAT_INT_5SEC	 5000
2379 #define	BGE_APE_HOST_HEARTBEAT_COUNT	0x4218
2380 #define	BGE_APE_HOST_DRVR_STATE		0x421c
2381 #define	BGE_APE_HOST_DRVR_STATE_START	 0x00000001
2382 #define	BGE_APE_HOST_DRVR_STATE_UNLOAD	 0x00000002
2383 #define	BGE_APE_HOST_DRVR_STATE_WOL	 0x00000003
2384 #define	BGE_APE_HOST_WOL_SPEED		0x4224
2385 #define	BGE_APE_HOST_WOL_SPEED_AUTO	 0x00008000
2386 
2387 #define	BGE_APE_EVENT_STATUS		0x4300
2388 
2389 #define	 APE_EVENT_STATUS_DRIVER_EVNT	 0x00000010
2390 #define	 APE_EVENT_STATUS_STATE_CHNGE	 0x00000500
2391 #define	 APE_EVENT_STATUS_SCRTCHPD_READ	 0x00001600
2392 #define	 APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700
2393 #define	 APE_EVENT_STATUS_STATE_START	 0x00010000
2394 #define	 APE_EVENT_STATUS_STATE_UNLOAD	 0x00020000
2395 #define	 APE_EVENT_STATUS_STATE_WOL	 0x00030000
2396 #define	 APE_EVENT_STATUS_STATE_SUSPEND	 0x00040000
2397 #define	 APE_EVENT_STATUS_EVENT_PENDING	 0x80000000
2398 
2399 #define	BGE_APE_PER_LOCK_REQ		0x8400
2400 #define	 APE_LOCK_PER_REQ_DRIVER	 0x00001000
2401 #define	BGE_APE_PER_LOCK_GRANT		0x8420
2402 #define	 APE_PER_LOCK_GRANT_DRIVER	 0x00001000
2403 
2404 /* APE convenience enumerations. */
2405 #define	BGE_APE_LOCK_PHY0		0
2406 #define	BGE_APE_LOCK_GRC		1
2407 #define	BGE_APE_LOCK_PHY1		2
2408 #define	BGE_APE_LOCK_PHY2		3
2409 #define	BGE_APE_LOCK_MEM		4
2410 #define	BGE_APE_LOCK_PHY3		5
2411 #define	BGE_APE_LOCK_GPIO		7
2412 
2413 #ifdef __cplusplus
2414 }
2415 #endif
2416 
2417 #endif	/* _BGE_HW_H */
2418