xref: /illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/l5/include/lm_l5st.h (revision d14abf155341d55053c76eeec58b787a456b753b)
1 /*******************************************************************************
2  * lm_l5st.h - L5 lm data structures
3  ******************************************************************************/
4 #ifndef _LM_L5ST_H
5 #define _LM_L5ST_H
6 
7 
8 #include "everest_iscsi_constants.h"
9 #include "57xx_fcoe_constants.h"
10 #include "57xx_iscsi_constants.h"
11 #include "57xx_iscsi_rfc_constants.h"
12 
13 #include "lm_l4st.h"
14 
15 
16 /* utility macros */
17 #define SET_FIELD(fieldName, mask, newVal) ((fieldName) = (((fieldName) & ~mask) | (((newVal) << mask ## _SHIFT) & mask)))
18 #define GET_FIELD(fieldName, mask) (((fieldName) & mask) >> mask ## _SHIFT)
19 
20 
21 #define ISCSI_LICENSE_CONNECTION_LIMIT (0xffff)     /* TODO: add iSCSI licensing support */
22 
23 /*This is needed because the BD chain has not been set yet*/
24 /* The number of bds (EQEs) per page including the last bd which is used as
25  * a pointer to the next bd page. */
26 #define ISCSI_EQES_PER_PAGE(_is_next_ptr_needed)    (USABLE_BDS_PER_PAGE(sizeof(struct iscsi_kcqe),_is_next_ptr_needed))
27 #define FCOE_EQES_PER_PAGE(_is_next_ptr_needed)     (USABLE_BDS_PER_PAGE(sizeof(struct fcoe_kcqe),_is_next_ptr_needed))
28 
29 
30 /* offset within a EQ page of the next page address */
31 #define NEXT_EQ_PAGE_ADDRESS_OFFSET	(LM_PAGE_SIZE - sizeof(struct iscsi_kcqe))
32 
33 /* max number of eq chains, everst convention */
34 #define MAX_EQ_CHAIN                (ISCSI_NUM_OF_CQS*8) /* per function */
35 
36 /* max EQ pages limitation */
37 #define MAX_EQ_PAGES                (256)
38 
39 
40 /* The number of useable bds per page.  This number does not include
41  * the last bd at the end of the page. */
42 //#define MAX_EQ_BD_PER_PAGE          ((u32_t) (ISCSI_EQES_PER_PAGE - 1))
43 
44 #define MAX_EQ_SIZE_FCOE(_is_next_ptr_needed)		            (MAX_EQ_PAGES * (FCOE_EQES_PER_PAGE(_is_next_ptr_needed) -1))
45 #define MAX_EQ_SIZE_ISCSI(_is_next_ptr_needed)		            (MAX_EQ_PAGES * (ISCSI_EQES_PER_PAGE(_is_next_ptr_needed) -1))
46 /* number of bits to shift to edjeust the page_size from the kwqe_init2 to 0 */
47 #define ISCSI_PAGE_BITS_SHIFT       (8)
48 
49 /* layer mask value in the KCQEs */
50 #define KCQE_FLAGS_LAYER_MASK_L6    (ISCSI_KWQE_LAYER_CODE<<4)
51 
52 /* pbl data */
53 typedef struct _lm_iscsi_pbl_t
54 {
55 	void            *base_virt;
56     lm_address_t	base_phy;
57 	u32_t			base_size;	/* size allocated in bytes */
58 
59     lm_address_t	*pbl_phys_table_virt;
60     lm_address_t	pbl_phys_table_phys;
61     void            *pbl_virt_table;
62 	u32_t			pbl_size;	/* size allocated in bytes */
63 	u32_t			pbl_entries;/* number of entries in PBL */
64 } lm_iscsi_pbl_t;
65 
66 
67 
68 typedef struct _lm_eq_addr_t
69 {
70     u8_t          b_allocated;
71     u32_t         prev_mem_size;
72     void          *bd_chain_virt;      /* virt addr of first page of the chain */
73     lm_address_t  bd_chain_phy;        /* phys addr of first page of the chain */
74 }lm_eq_addr_t;
75 
76 typedef struct _lm_eq_addr_save_t
77 {
78     lm_eq_addr_t    eq_addr[MAX_EQ_CHAIN];
79 }lm_eq_addr_save_t;
80 
81 /*******************************************************************************
82  * iSCSI info that will be allocated in the bind phase.
83  * This is the only parameters that stays valid when iscsi goes to hibernate.
84  ******************************************************************************/
85 typedef struct _lm_iscsi_info_bind_alloc_t
86 {
87     u8_t	    *global_buff_base_virt;
88     lm_address_t    global_buff_base_phy;
89 }lm_iscsi_info_bind_alloc_t;
90 
91 typedef struct _lm_iscsi_statistics_t
92 {
93     u32_t  total_ofld; /* cyclic counter of number of offloaded tcp states */
94     u32_t  total_upld; /* cyclic counter of number of uploaded tcp states */
95 }lm_iscsi_statistics_t;
96 
97 /*******************************************************************************
98  * iSCSI info that will be allocated in the bind phase.
99  * These parameters become not valid when iscsi goes to hibernate.
100  ******************************************************************************/
101 typedef struct _lm_iscsi_info_real_time_t
102 {
103     lm_state_block_t    state_blk;
104     d_list_t            iscsi_list;
105 
106 	u32_t			num_of_tasks;
107     u8_t			num_of_cqs;
108     u32_t			cq_size;
109     u16_t			hq_size;
110 
111     lm_eq_chain_t	eq_chain[MAX_EQ_CHAIN];
112     #define LM_SC_EQ(_pdev, _idx)             (_pdev)->iscsi_info.run_time.eq_chain[_idx]
113 
114     /* L5 eq */
115     u8_t l5_eq_chain_cnt;         /* number of L5 eq chains. currently equals num_of_cqs equals 1 */
116     u8_t l5_eq_base_chain_idx;    /* L5 eq base chain Where do the L5 status block start */
117     u16_t _pad_l5_eq;
118     u32_t l5_eq_max_chain_cnt; /* registry param --> 32 bit */
119     #define LM_SC_EQ_BASE_CHAIN_INDEX(pdev)           ((pdev)->iscsi_info.run_time.l5_eq_base_chain_idx)    /* that is first L5 SB */
120     #define LM_SC_EQ_CHAIN_CNT(pdev)                  ((pdev)->iscsi_info.run_time.l5_eq_chain_cnt)
121     #define LM_SC_MAX_CHAIN_CNT(pdev)                  ((pdev)->iscsi_info.run_time.l5_eq_max_chain_cnt)
122 
123 
124     /* 'for loop' macros on L5 eq chains  */
125     #define LM_SC_FOREACH_EQ_IDX(pdev, eq_idx)  \
126         for ((eq_idx) = (pdev)->iscsi_info.run_time.l5_eq_base_chain_idx; (eq_idx) < (u32_t)((pdev)->iscsi_info.run_time.l5_eq_base_chain_idx + (pdev)->iscsi_info.run_time.l5_eq_chain_cnt); (eq_idx)++)
127 
128     lm_iscsi_statistics_t stats;
129 }lm_iscsi_info_run_time_t;
130 /*******************************************************************************
131  * iSCSI info.
132  ******************************************************************************/
133 typedef struct _lm_iscsi_info_t
134 {
135     struct _lm_device_t *pdev;
136     // Paramters that stay valid in D3 and are allocated in bind time.
137     lm_iscsi_info_bind_alloc_t  bind;
138     lm_eq_addr_save_t           eq_addr_save;
139     #define LM_EQ_ADDR_SAVE_SC(_pdev, _idx)             (_pdev)->iscsi_info.eq_addr_save.eq_addr[_idx]
140     // Paramters that are not valid in D3 and are allocated after bind time.
141     lm_iscsi_info_run_time_t    run_time;
142 } lm_iscsi_info_t;
143 
144 
145 struct iscsi_update_ramrod_cached_params
146 {
147 	struct iscsi_kwqe_conn_update kwqe;
148 };
149 
150 
151 typedef union _lm_iscsi_slow_path_phys_data_t
152 {
153     struct iscsi_context iscsi_ctx; /* used by query slow path request */
154     struct iscsi_update_ramrod_cached_params update_ctx; /* used by update slow path request */
155 
156 } lm_iscsi_slow_path_phys_data_t;
157 
158 
159 typedef struct _lm_iscsi_slow_path_data_t {
160     lm_iscsi_slow_path_phys_data_t  * virt_addr;
161     lm_address_t                    phys_addr;
162 }lm_iscsi_slow_path_data_t ;
163 
164 
165 typedef struct _lm_iscsi_slow_path_request_t
166 {
167     lm_sp_req_common_t           sp_req_common;
168     lm_iscsi_slow_path_data_t    sp_req_data;
169 
170     u32_t    type;
171     #define SP_REQUEST_SC_INIT                        0
172     #define SP_REQUEST_SC_ADD_NEW_CONNECTION          1
173     #define SP_REQUEST_SC_UPDATE                      2
174     #define SP_REQUEST_SC_TERMINATE_OFFLOAD           3
175     #define SP_REQUEST_SC_TERMINATE1_OFFLOAD          4
176     #define SP_REQUEST_SC_QUERY                       5
177 
178     lm_status_t status; /* request completion status */
179 } lm_iscsi_slow_path_request_t;
180 
181 
182 typedef struct _lm_iscsi_state_t
183 {
184     lm_state_header_t               hdr;
185     struct iscsi_context*           ctx_virt;
186     lm_address_t                    ctx_phys;
187     u32_t                           cid;
188     u16_t                           iscsi_conn_id;  /* Drivers connection ID. */
189     u8_t                            b_keep_resources;
190     u8_t                            b_resources_allocated;
191 
192 	lm_iscsi_slow_path_data_t       sp_req_data;
193 
194     void                            *db_data;
195     lm_address_t                    phys_db_data;
196 
197     lm_iscsi_pbl_t                  task_array;
198     lm_iscsi_pbl_t                  r2tq;
199     lm_iscsi_pbl_t                  hq;
200 
201     //iscsi_kwqe_t                    **pending_kwqes;
202     struct iscsi_kwqe_conn_offload1      pending_ofld1;
203     struct iscsi_kwqe_conn_offload2      pending_ofld2;
204     struct iscsi_kwqe_conn_offload3      pending_ofld3;
205 
206 
207 } lm_iscsi_state_t;
208 
209 
210 /* RAMRODs used for FCOE */
211 typedef union _lm_fcoe_slow_path_phys_data_t
212 {
213     struct fcoe_init_ramrod_params                  fcoe_init;
214     struct fcoe_conn_offload_ramrod_params          fcoe_ofld;
215     struct fcoe_conn_enable_disable_ramrod_params   fcoe_enable;
216     struct fcoe_stat_ramrod_params                  fcoe_stat;
217 } lm_fcoe_slow_path_phys_data_t;
218 
219 
220 
221 typedef struct _lm_fcoe_state_t
222 {
223     lm_state_header_t               hdr;
224     struct fcoe_context*            ctx_virt;
225     lm_address_t                    ctx_phys;
226 
227     u32_t                           cid;
228     u16_t                           fcoe_conn_id;  /* Drivers connection ID. */
229 
230     struct fcoe_kwqe_conn_offload1      ofld1;
231     struct fcoe_kwqe_conn_offload2      ofld2;
232     struct fcoe_kwqe_conn_offload3      ofld3;
233     struct fcoe_kwqe_conn_offload4      ofld4;
234 } lm_fcoe_state_t;
235 
236 
237 
238 
239 
240 
241 /*******************************************************************************
242  * FCoE info that will be allocated in the bind phase.
243  * This is the only parameters that stays valid when FCoE goes to hibernate.
244  ******************************************************************************/
245 
246 /* pbl data */
247 typedef struct _lm_fcoe_pbl_t
248 {
249     u8_t            allocated; /*For D3 case and better debugging*/
250     lm_address_t    *pbl_phys_table_virt;
251     lm_address_t    pbl_phys_table_phys;
252     void            *pbl_virt_table;
253     u32_t           pbl_size;	/* size allocated in bytes */
254     u32_t           pbl_entries;/* number of entries in PBL */
255 } lm_fcoe_pbl_t;
256 
257 typedef struct _lm_fcoe_info_bind_alloc_t
258 {
259     lm_fcoe_pbl_t   pbl[MAX_EQ_CHAIN];
260     #define LM_FC_PBL(_pdev, _idx)             ((_pdev)->fcoe_info.bind.pbl[_idx])
261 
262     /* FCOE Miniport guarantees that they don't post more than once KWQE at a time,
263      * so there's no need to allocate per-connection ramrod buffer, A single fcoe per-client
264      * ramrod buffer (pdev->fcoe_info.bind.ramrod_mem_phys) can be used for all KWQEs.*/
265     void            *ramrod_mem_virt;
266     lm_address_t    ramrod_mem_phys;
267 }lm_fcoe_info_bind_alloc_t;
268 
269 /*******************************************************************************
270  * FCoE info that will be allocated in the bind phase.
271  * These parameters become not valid when FCoE goes to hibernate.
272  ******************************************************************************/
273 typedef struct _lm_fcoe_info_run_time_t
274 {
275     lm_state_block_t        state_blk;
276     lm_eq_chain_t	        eq_chain[MAX_EQ_CHAIN];
277     #define LM_FC_EQ(_pdev, _idx)             (_pdev)->fcoe_info.run_time.eq_chain[_idx]
278 
279     u8_t            fc_eq_base_chain_idx;
280     u8_t			num_of_cqs;
281 
282     d_list_t            fcoe_list;
283 
284     #define LM_FC_FOREACH_EQ_IDX(pdev, eq_idx)  \
285         for ((eq_idx) = (pdev)->fcoe_info.run_time.fc_eq_base_chain_idx; (eq_idx) < (u32_t)((pdev)->fcoe_info.run_time.fc_eq_base_chain_idx + (pdev)->fcoe_info.run_time.num_of_cqs); (eq_idx)++)
286 }lm_fcoe_info_run_time_t;
287 /*******************************************************************************
288  * FCOE info.
289  ******************************************************************************/
290 typedef struct _lm_fcoe_info_t
291 {
292     struct _lm_device_t     *pdev;
293 
294     // Paramters that stay valid in D3 and are allocated in bind time.
295     lm_fcoe_info_bind_alloc_t   bind;
296     lm_eq_addr_save_t           eq_addr_save;
297     #define LM_EQ_ADDR_SAVE_FC(_pdev, _idx)             (_pdev)->fcoe_info.eq_addr_save.eq_addr[_idx]
298     // Paramters that are not valid in D3 and are allocated after bind time.
299     lm_fcoe_info_run_time_t     run_time;
300 } lm_fcoe_info_t;
301 
302 #endif
303