xref: /illumos-gate/usr/src/uts/common/sys/nxge/nxge_hw.h (revision 2d6eb4a5e0a47d30189497241345dc5466bb68ab)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_NXGE_NXGE_HW_H
27 #define	_SYS_NXGE_NXGE_HW_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #if	!defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) && \
34 		!defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN)
35 #error	Host endianness not defined
36 #endif
37 
38 #if	!defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) && \
39 		!defined(__BIT_FIELDS_HTOL) && !defined(__BIT_FIELDS_LTOH)
40 #error	Bit ordering not defined
41 #endif
42 
43 #include <nxge_fflp_hw.h>
44 #include <nxge_ipp_hw.h>
45 #include <nxge_mac_hw.h>
46 #include <nxge_rxdma_hw.h>
47 #include <nxge_txc_hw.h>
48 #include <nxge_txdma_hw.h>
49 #include <nxge_zcp_hw.h>
50 #include <nxge_espc_hw.h>
51 #include <nxge_n2_esr_hw.h>
52 #include <nxge_sr_hw.h>
53 #include <nxge_phy_hw.h>
54 
55 
56 /*
57  * The Neptune chip has 16 Receive DMA channels, but no more than
58  * 24 Transmit DMA channels.
59  */
60 typedef uint32_t dc_map_t;
61 
62 /*
63  * The logical group map is a Crossbow addition.
64  */
65 typedef uint32_t lg_map_t;
66 
67 /* Modes of NXGE core */
68 typedef	enum nxge_mode_e {
69 	NXGE_MODE_NE		= 1,
70 	NXGE_MODE_N2		= 2
71 } nxge_mode_t;
72 
73 /*
74  * Function control Register
75  * (bit 31 is reset to 0. Read back 0 then free to use it.
76  * (once done with it, bit 0:15 can be used to store SW status)
77  */
78 #define	DEV_FUNC_SR_REG			(PIO + 0x10000)
79 #define	DEV_FUNC_SR_SR_SHIFT		0
80 #define	DEV_FUNC_SR_SR_MASK		0x000000000000FFFFULL
81 #define	DEV_FUNC_SR_FUNCID_SHIFT	16
82 #define	DEV_FUNC_SR_FUNCID_MASK		0x0000000000030000ULL
83 #define	DEV_FUNC_SR_TAS_SHIFT		31
84 #define	DEV_FUNC_SR_TAS_MASK		0x0000000080000000ULL
85 
86 typedef union _dev_func_sr_t {
87 	uint64_t value;
88 	struct {
89 #if defined(_BIG_ENDIAN)
90 		uint32_t hdw;
91 #endif
92 		struct {
93 #if defined(_BIT_FIELDS_HTOL)
94 			uint32_t tas:1;
95 			uint32_t res2:13;
96 			uint32_t funcid:2;
97 			uint32_t sr:16;
98 #elif defined(_BIT_FIELDS_LTOH)
99 			uint32_t sr:16;
100 			uint32_t funcid:2;
101 			uint32_t res2:13;
102 			uint32_t tas:1;
103 #endif
104 		} ldw;
105 #if !defined(_BIG_ENDIAN)
106 		uint32_t hdw;
107 #endif
108 	} bits;
109 } dev_func_sr_t, *p_dev_func_sr_t;
110 
111 
112 /*
113  * Multi Parition Control Register (partitiion manager)
114  */
115 #define	MULTI_PART_CTL_REG	(FZC_PIO + 0x00000)
116 #define	MULTI_PART_CTL_MPC	0x0000000000000001ULL
117 
118 typedef union _multi_part_ctl_t {
119 	uint64_t value;
120 	struct {
121 #if defined(_BIG_ENDIAN)
122 		uint32_t hdw;
123 #endif
124 		struct {
125 #if defined(_BIT_FIELDS_HTOL)
126 			uint32_t res1:31;
127 			uint32_t mpc:1;
128 #elif defined(_BIT_FIELDS_LTOH)
129 			uint32_t mpc:1;
130 			uint32_t res1:31;
131 #endif
132 		} ldw;
133 #if !defined(_BIG_ENDIAN)
134 		uint32_t hdw;
135 #endif
136 	} bits;
137 } multi_part_ctl_t, *p_multi_part_ctl_t;
138 
139 /*
140  * Virtual DMA CSR Address (partition manager)
141  */
142 #define	VADDR_REG		(PIO_VADDR + 0x00000)
143 
144 /*
145  * DMA Channel Binding Register (partition manager)
146  */
147 #define	DMA_BIND_REG		(FZC_PIO + 0x10000)
148 #define	DMA_BIND_RX_SHIFT	0
149 #define	DMA_BIND_RX_MASK	0x000000000000001FULL
150 #define	DMA_BIND_RX_BIND_SHIFT	5
151 #define	DMA_BIND_RX_BIND_SET	0x0000000000000020ULL
152 #define	DMA_BIND_RX_BIND_MASK	0x0000000000000020ULL
153 #define	DMA_BIND_TX_SHIFT	8
154 #define	DMA_BIND_TX_MASK	0x0000000000001f00ULL
155 #define	DMA_BIND_TX_BIND_SHIFT	13
156 #define	DMA_BIND_TX_BIND_SET	0x0000000000002000ULL
157 #define	DMA_BIND_TX_BIND_MASK	0x0000000000002000ULL
158 
159 typedef union _dma_bind_t {
160 	uint64_t value;
161 	struct {
162 #if defined(_BIG_ENDIAN)
163 		uint32_t hdw;
164 #endif
165 		struct {
166 #if defined(_BIT_FIELDS_HTOL)
167 			uint32_t res1_1:16;
168 			uint32_t tx_bind:1;
169 			uint32_t tx:5;
170 			uint32_t res2:2;
171 			uint32_t rx_bind:1;
172 			uint32_t rx:5;
173 #elif defined(_BIT_FIELDS_LTOH)
174 			uint32_t rx:5;
175 			uint32_t rx_bind:1;
176 			uint32_t res2:2;
177 			uint32_t tx:5;
178 			uint32_t tx_bind:1;
179 			uint32_t res1_1:16;
180 #endif
181 		} ldw;
182 #if !defined(_BIG_ENDIAN)
183 		uint32_t hdw;
184 #endif
185 	} bits;
186 }  dma_bind_t, *p_dma_bind_t;
187 
188 /*
189  * System interrupts:
190  *	Logical device and group definitions.
191  */
192 #define	NXGE_INT_MAX_LDS		69
193 #define	NXGE_INT_MAX_LDGS		64
194 #define	NXGE_LDGRP_PER_NIU_PORT		(NXGE_INT_MAX_LDGS/2)
195 #define	NXGE_LDGRP_PER_NEP_PORT		(NXGE_INT_MAX_LDGS/4)
196 #define	NXGE_LDGRP_PER_2PORTS		(NXGE_INT_MAX_LDGS/2)
197 #define	NXGE_LDGRP_PER_4PORTS		(NXGE_INT_MAX_LDGS/4)
198 
199 #define	NXGE_RDMA_LD_START		0
200 #define	NXGE_TDMA_LD_START		32
201 #define	NXGE_MIF_LD			63
202 #define	NXGE_MAC_LD_START		64
203 #define	NXGE_MAC_LD_PORT0		64
204 #define	NXGE_MAC_LD_PORT1		65
205 #define	NXGE_MAC_LD_PORT2		66
206 #define	NXGE_MAC_LD_PORT3		67
207 #define	NXGE_SYS_ERROR_LD		68
208 
209 /*
210  * Logical Device Group Number
211  */
212 #define	LDG_NUM_REG		(FZC_PIO + 0x20000)
213 #define	LDG_NUM_NUM_SHIFT	0
214 #define	LDG_NUM_NUM_MASK	0x000000000000001FULL
215 
216 typedef union _ldg_num_t {
217 	uint64_t value;
218 	struct {
219 #if defined(_BIG_ENDIAN)
220 		uint32_t hdw;
221 #endif
222 		struct {
223 #if defined(_BIT_FIELDS_HTOL)
224 			uint32_t res1_1:26;
225 			uint32_t num:6;
226 #elif defined(_BIT_FIELDS_LTOH)
227 			uint32_t num:6;
228 			uint32_t res1_1:26;
229 #endif
230 		} ldw;
231 #if !defined(_BIG_ENDIAN)
232 		uint32_t hdw;
233 #endif
234 	} bits;
235 } ldg_num_t, *p_ldg_num_t;
236 
237 /*
238  * Logical Device State Vector
239  */
240 #define	LDSV0_REG		(PIO_LDSV + 0x00000)
241 #define	LDSV0_LDF_SHIFT		0
242 #define	LDSV0_LDF_MASK		0x00000000000003FFULL
243 #define	LDG_NUM_NUM_MASK	0x000000000000001FULL
244 #define	LDSV_MASK_ALL		0x0000000000000001ULL
245 
246 /*
247  * Logical Device State Vector 1
248  */
249 #define	LDSV1_REG		(PIO_LDSV + 0x00008)
250 
251 /*
252  * Logical Device State Vector 2
253  */
254 #define	LDSV2_REG		(PIO_LDSV + 0x00010)
255 
256 /* For Logical Device State Vector 0 and 1 */
257 typedef union _ldsv_t {
258 	uint64_t value;
259 	struct {
260 #if defined(_BIG_ENDIAN)
261 		uint32_t hdw;
262 #endif
263 		uint32_t ldw;
264 #if !defined(_BIG_ENDIAN)
265 		uint32_t hdw;
266 #endif
267 	} bits;
268 } ldsv_t, *p_ldsv_t;
269 
270 #define	LDSV2_LDF0_SHIFT		0
271 #define	LDSV2_LDF0_MASK			0x000000000000001FULL
272 #define	LDSV2_LDF1_SHIFT		5
273 #define	LDSV2_LDF1_MASK			0x00000000000001E0ULL
274 
275 typedef union _ldsv2_t {
276 	uint64_t value;
277 	struct {
278 #if defined(_BIG_ENDIAN)
279 		uint32_t hdw;
280 #endif
281 		struct {
282 #if defined(_BIT_FIELDS_HTOL)
283 			uint32_t res1_1:22;
284 			uint32_t ldf1:5;
285 			uint32_t ldf0:5;
286 #elif defined(_BIT_FIELDS_LTOH)
287 			uint32_t ldf0:5;
288 			uint32_t ldf1:5;
289 			uint32_t res1_1:22;
290 #endif
291 		} ldw;
292 #if !defined(_BIG_ENDIAN)
293 		uint32_t hdw;
294 #endif
295 	} bits;
296 } ldsv2_t, *p_ldsv2_t;
297 
298 /*
299  * Logical Device Interrupt Mask 0
300  */
301 #define	LD_IM0_REG		(PIO_IMASK0 + 0x00000)
302 #define	LD_IM0_SHIFT		0
303 #define	LD_IM0_MASK		0x0000000000000003ULL
304 #define	LD_IM_MASK		0x0000000000000003ULL
305 
306 /*
307  * Logical Device Interrupt Mask 1
308  */
309 #define	LD_IM1_REG		(PIO_IMASK1 + 0x00000)
310 #define	LD_IM1_SHIFT		0
311 #define	LD_IM1_MASK		0x0000000000000003ULL
312 
313 /* For Lofical Device Interrupt Mask 0 and 1 */
314 typedef union _ld_im_t {
315 	uint64_t value;
316 	struct {
317 #if defined(_BIG_ENDIAN)
318 		uint32_t hdw;
319 #endif
320 		struct {
321 
322 #if defined(_BIT_FIELDS_HTOL)
323 			uint32_t res1_1:30;
324 			uint32_t ldf_mask:2;
325 #elif defined(_BIT_FIELDS_LTOH)
326 			uint32_t ldf_mask:2;
327 			uint32_t res1_1:30;
328 #endif
329 		} ldw;
330 #if !defined(_BIG_ENDIAN)
331 		uint32_t hdw;
332 #endif
333 	} bits;
334 } ld_im_t, *p_ld_im_t;
335 
336 /*
337  * Logical Device Group Interrupt Management
338  */
339 #define	LDGIMGN_REG		(PIO_LDSV + 0x00018)
340 #define	LDGIMGN_TIMER_SHIFT	0
341 #define	LDGIMGM_TIMER_MASK	0x000000000000003FULL
342 #define	LDGIMGN_ARM_SHIFT	31
343 #define	LDGIMGM_ARM		0x0000000080000000ULL
344 #define	LDGIMGM_ARM_MASK	0x0000000080000000ULL
345 
346 typedef union _ldgimgm_t {
347 	uint64_t value;
348 	struct {
349 #if defined(_BIG_ENDIAN)
350 		uint32_t hdw;
351 #endif
352 		struct {
353 #if defined(_BIT_FIELDS_HTOL)
354 		uint32_t arm:1;
355 		uint32_t res2:25;
356 		uint32_t timer:6;
357 #elif defined(_BIT_FIELDS_LTOH)
358 		uint32_t timer:6;
359 		uint32_t res2:25;
360 		uint32_t arm:1;
361 #endif
362 		} ldw;
363 #if !defined(_BIG_ENDIAN)
364 		uint32_t hdw;
365 #endif
366 	} bits;
367 } ldgimgm_t, *p_ldgimgm_t;
368 
369 /*
370  * Logical Device Group Interrupt Timer Resolution
371  */
372 #define	LDGITMRES_REG		(FZC_PIO + 0x00008)
373 #define	LDGTITMRES_RES_SHIFT	0			/* bits 19:0 */
374 #define	LDGTITMRES_RES_MASK	0x00000000000FFFFFULL
375 typedef union _ldgitmres_t {
376 	uint64_t value;
377 	struct {
378 #if defined(_BIG_ENDIAN)
379 		uint32_t hdw;
380 #endif
381 		struct {
382 #if defined(_BIT_FIELDS_HTOL)
383 		uint32_t res1_1:12;
384 		uint32_t res:20;
385 #elif defined(_BIT_FIELDS_LTOH)
386 		uint32_t res:20;
387 		uint32_t res1_1:12;
388 #endif
389 		} ldw;
390 #if !defined(_BIG_ENDIAN)
391 		uint32_t hdw;
392 #endif
393 	} bits;
394 } ldgitmres_t, *p_ldgitmres_t;
395 
396 /*
397  * System Interrupt Data
398  */
399 #define	SID_REG			(FZC_PIO + 0x10200)
400 #define	SID_DATA_SHIFT		0			/* bits 6:0 */
401 #define	SID_DATA_MASK		0x000000000000007FULL
402 #define	SID_DATA_INTNUM_SHIFT	0			/* bits 4:0 */
403 #define	SID_DATA_INTNUM_MASK	0x000000000000001FULL
404 #define	SID_DATA_FUNCNUM_SHIFT	5			/* bits 6:5 */
405 #define	SID_DATA_FUNCNUM_MASK	0x0000000000000060ULL
406 #define	SID_PCI_FUNCTION_SHIFT	(1 << 5)
407 #define	SID_N2_INDEX		(1 << 6)
408 
409 #define	SID_DATA(f, v)		((f << SID_DATA_FUNCNUM_SHIFT) |	\
410 				((v << SID_DATA_SHIFT) & SID_DATA_INTNUM_MASK))
411 
412 #define	SID_DATA_N2(v)		(v | SID_N2_INDEX)
413 
414 typedef union _sid_t {
415 	uint64_t value;
416 	struct {
417 #if defined(_BIG_ENDIAN)
418 		uint32_t hdw;
419 #endif
420 		struct {
421 #if defined(_BIT_FIELDS_HTOL)
422 		uint32_t res1_1:25;
423 		uint32_t data:7;
424 #elif defined(_BIT_FIELDS_LTOH)
425 		uint32_t data:7;
426 		uint32_t res1_1:25;
427 #endif
428 		} ldw;
429 #if !defined(_BIG_ENDIAN)
430 		uint32_t hdw;
431 #endif
432 	} bits;
433 } sid_t, *p_sid_t;
434 
435 /*
436  * Reset Control
437  */
438 #define	RST_CTL_REG		(FZC_PIO + 0x00038)
439 #define	RST_CTL_MAC_RST3	0x0000000000400000ULL
440 #define	RST_CTL_MAC_RST3_SHIFT	22
441 #define	RST_CTL_MAC_RST2	0x0000000000200000ULL
442 #define	RST_CTL_MAC_RST2_SHIFT	21
443 #define	RST_CTL_MAC_RST1	0x0000000000100000ULL
444 #define	RST_CTL_MAC_RST1_SHIFT	20
445 #define	RST_CTL_MAC_RST0	0x0000000000080000ULL
446 #define	RST_CTL_MAC_RST0_SHIFT	19
447 #define	RST_CTL_EN_ACK_TO	0x0000000000000800ULL
448 #define	RST_CTL_EN_ACK_TO_SHIFT	11
449 #define	RST_CTL_ACK_TO_MASK	0x00000000000007FEULL
450 #define	RST_CTL_ACK_TO_SHIFT	1
451 
452 
453 typedef union _rst_ctl_t {
454 	uint64_t value;
455 	struct {
456 #if defined(_BIG_ENDIAN)
457 		uint32_t hdw;
458 #endif
459 		struct {
460 #if defined(_BIT_FIELDS_HTOL)
461 		uint32_t res1:9;
462 		uint32_t mac_rst3:1;
463 		uint32_t mac_rst2:1;
464 		uint32_t mac_rst1:1;
465 		uint32_t mac_rst0:1;
466 		uint32_t res2:7;
467 		uint32_t ack_to_en:1;
468 		uint32_t ack_to_val:10;
469 		uint32_t res3:1;
470 #elif defined(_BIT_FIELDS_LTOH)
471 		uint32_t res3:1;
472 		uint32_t ack_to_val:10;
473 		uint32_t ack_to_en:1;
474 		uint32_t res2:7;
475 		uint32_t mac_rst0:1;
476 		uint32_t mac_rst1:1;
477 		uint32_t mac_rst2:1;
478 		uint32_t mac_rst3:1;
479 		uint32_t res1:9;
480 #endif
481 		} ldw;
482 #if !defined(_BIG_ENDIAN)
483 		uint32_t hdw;
484 #endif
485 	} bits;
486 } rst_ctl_t, *p_rst_ctl_t;
487 
488 /*
489  * System Error Mask
490  */
491 #define	SYS_ERR_MASK_REG	(FZC_PIO + 0x00090)
492 
493 /*
494  * System Error Status
495  */
496 #define	SYS_ERR_STAT_REG	(FZC_PIO + 0x00098)
497 
498 
499 #define	SYS_ERR_META2_MASK	0x0000000000000400ULL
500 #define	SYS_ERR_META2_SHIFT	10
501 #define	SYS_ERR_META1_MASK	0x0000000000000200ULL
502 #define	SYS_ERR_META1_SHIFT	9
503 #define	SYS_ERR_PEU_MASK	0x0000000000000100ULL
504 #define	SYS_ERR_PEU_SHIFT	8
505 #define	SYS_ERR_TXC_MASK	0x0000000000000080ULL
506 #define	SYS_ERR_TXC_SHIFT	7
507 #define	SYS_ERR_RDMC_MASK	0x0000000000000040ULL
508 #define	SYS_ERR_RDMC_SHIFT	6
509 #define	SYS_ERR_TDMC_MASK	0x0000000000000020ULL
510 #define	SYS_ERR_TDMC_SHIFT	5
511 #define	SYS_ERR_ZCP_MASK	0x0000000000000010ULL
512 #define	SYS_ERR_ZCP_SHIFT	4
513 #define	SYS_ERR_FFLP_MASK	0x0000000000000008ULL
514 #define	SYS_ERR_FFLP_SHIFT	3
515 #define	SYS_ERR_IPP_MASK	0x0000000000000004ULL
516 #define	SYS_ERR_IPP_SHIFT	2
517 #define	SYS_ERR_MAC_MASK	0x0000000000000002ULL
518 #define	SYS_ERR_MAC_SHIFT	1
519 #define	SYS_ERR_SMX_MASK	0x0000000000000001ULL
520 #define	SYS_ERR_SMX_SHIFT	0
521 #define	SYS_ERR_MASK_ALL	(SYS_ERR_SMX_MASK | SYS_ERR_MAC_MASK | \
522 				SYS_ERR_IPP_MASK | SYS_ERR_FFLP_MASK | \
523 				SYS_ERR_ZCP_MASK | SYS_ERR_TDMC_MASK | \
524 				SYS_ERR_RDMC_MASK | SYS_ERR_TXC_MASK | \
525 				SYS_ERR_PEU_MASK | SYS_ERR_META1_MASK | \
526 				SYS_ERR_META2_MASK)
527 
528 
529 typedef union _sys_err_mask_t {
530 	uint64_t value;
531 	struct {
532 #if defined(_BIG_ENDIAN)
533 		uint32_t hdw;
534 #endif
535 		struct {
536 #if defined(_BIT_FIELDS_HTOL)
537 		uint32_t res:21;
538 		uint32_t meta2:1;
539 		uint32_t meta1:1;
540 		uint32_t peu:1;
541 		uint32_t txc:1;
542 		uint32_t rdmc:1;
543 		uint32_t tdmc:1;
544 		uint32_t zcp:1;
545 		uint32_t fflp:1;
546 		uint32_t ipp:1;
547 		uint32_t mac:1;
548 		uint32_t smx:1;
549 #elif defined(_BIT_FIELDS_LTOH)
550 		uint32_t smx:1;
551 		uint32_t mac:1;
552 		uint32_t ipp:1;
553 		uint32_t fflp:1;
554 		uint32_t zcp:1;
555 		uint32_t tdmc:1;
556 		uint32_t rdmc:1;
557 		uint32_t txc:1;
558 		uint32_t peu:1;
559 		uint32_t meta1:1;
560 		uint32_t meta2:1;
561 		uint32_t res:21;
562 #endif
563 		} ldw;
564 #if !defined(_BIG_ENDIAN)
565 		uint32_t hdw;
566 #endif
567 	} bits;
568 } sys_err_mask_t, sys_err_stat_t, *p_sys_err_mask_t, *p_sys_err_stat_t;
569 
570 
571 /*
572  * Meta Arbiter Dirty Transaction ID Control
573  */
574 
575 #define	DIRTY_TID_CTL_REG		(FZC_PIO + 0x0010)
576 #define	DIRTY_TID_CTL_WR_THRES_MASK	0x00000000003F0000ULL
577 #define	DIRTY_TID_CTL_WR_THRES_SHIFT    16
578 #define	DIRTY_TID_CTL_RD_THRES_MASK	0x00000000000003F0ULL
579 #define	DIRTY_TID_CTL_RD_THRES_SHIFT	4
580 #define	DIRTY_TID_CTL_DTID_CLR		0x0000000000000002ULL
581 #define	DIRTY_TID_CTL_DTID_CLR_SHIFT	1
582 #define	DIRTY_TID_CTL_DTID_EN		0x0000000000000001ULL
583 #define	DIRTY_TID_CTL_DTID_EN_SHIFT	0
584 
585 typedef union _dty_tid_ctl_t {
586 	uint64_t value;
587 	struct {
588 #if defined(_BIG_ENDIAN)
589 		uint32_t hdw;
590 #endif
591 		struct {
592 #if defined(_BIT_FIELDS_HTOL)
593 		uint32_t res1:10;
594 		uint32_t np_wr_thres_val:6;
595 		uint32_t res2:6;
596 		uint32_t np_rd_thres_val:6;
597 		uint32_t res3:2;
598 		uint32_t dty_tid_clr:1;
599 		uint32_t dty_tid_en:1;
600 #elif defined(_BIT_FIELDS_LTOH)
601 		uint32_t dty_tid_en:1;
602 		uint32_t dty_tid_clr:1;
603 		uint32_t res3:2;
604 		uint32_t np_rd_thres_val:6;
605 		uint32_t res2:6;
606 		uint32_t np_wr_thres_val:6;
607 		uint32_t res1:10;
608 #endif
609 		} ldw;
610 #if !defined(_BIG_ENDIAN)
611 		uint32_t hdw;
612 #endif
613 	} bits;
614 } dty_tid_ctl_t, *p_dty_tid_ctl_t;
615 
616 
617 /*
618  * Meta Arbiter Dirty Transaction ID Status
619  */
620 #define	DIRTY_TID_STAT_REG			(FZC_PIO + 0x0018)
621 #define	DIRTY_TID_STAT_WR_TID_DTY_CNT_MASK	0x0000000000003F00ULL
622 #define	DIRTY_TID_STAT_WR_TID_DTY_CNT_SHIFT	8
623 #define	DIRTY_TID_STAT_RD_TID_DTY_CNT_MASK	0x000000000000003FULL
624 #define	DIRTY_TID_STAT_RD_TID_DTY_CNT_SHIFT	0
625 
626 typedef union _dty_tid_stat_t {
627 	uint64_t value;
628 	struct {
629 #if defined(_BIG_ENDIAN)
630 		uint32_t hdw;
631 #endif
632 		struct {
633 #if defined(_BIT_FIELDS_HTOL)
634 		uint32_t res1:18;
635 		uint32_t wr_tid_dirty_cnt:6;
636 		uint32_t res2:2;
637 		uint32_t rd_tid_dirty_cnt:6;
638 #elif defined(_BIT_FIELDS_LTOH)
639 		uint32_t rd_tid_dirty_cnt:6;
640 		uint32_t res2:2;
641 		uint32_t wr_tid_dirty_cnt:6;
642 		uint32_t res1:18;
643 #endif
644 		} ldw;
645 #if !defined(_BIG_ENDIAN)
646 		uint32_t hdw;
647 #endif
648 	} bits;
649 } dty_tid_stat_t, *p_dty_tid_stat_t;
650 
651 
652 /*
653  * SMX Registers
654  */
655 #define	SMX_CFIG_DAT_REG		(FZC_PIO + 0x00040)
656 #define	SMX_CFIG_DAT_RAS_DET_EN_MASK	0x0000000080000000ULL
657 #define	SMX_CFIG_DAT_RAS_DET_EN_SHIFT	31
658 #define	SMX_CFIG_DAT_RAS_INJ_EN_MASK	0x0000000040000000ULL
659 #define	SMX_CFIG_DAT_RAS_INJ_EN_SHIFT	30
660 #define	SMX_CFIG_DAT_TRANS_TO_MASK	0x000000000FFFFFFFULL
661 #define	SMX_CFIG_DAT_TRANS_TO_SHIFT	0
662 
663 typedef union _smx_cfg_dat_t {
664 	uint64_t value;
665 	struct {
666 #if defined(_BIG_ENDIAN)
667 		uint32_t hdw;
668 #endif
669 		struct {
670 #if defined(_BIT_FIELDS_HTOL)
671 		uint32_t res_err_det:1;
672 		uint32_t ras_err_inj_en:1;
673 		uint32_t res:2;
674 		uint32_t trans_to_val:28;
675 #elif defined(_BIT_FIELDS_LTOH)
676 		uint32_t trans_to_val:28;
677 		uint32_t res:2;
678 		uint32_t ras_err_inj_en:1;
679 		uint32_t res_err_det:1;
680 #endif
681 		} ldw;
682 #if !defined(_BIG_ENDIAN)
683 		uint32_t hdw;
684 #endif
685 	} bits;
686 } smx_cfg_dat_t, *p_smx_cfg_dat_t;
687 
688 
689 #define	SMX_INT_STAT_REG	(FZC_PIO + 0x00048)
690 #define	SMX_INT_STAT_SM_MASK	0x00000000FFFFFFC0ULL
691 #define	SMX_INT_STAT_SM_SHIFT	6
692 
693 typedef union _smx_int_stat_t {
694 	uint64_t value;
695 	struct {
696 #if defined(_BIG_ENDIAN)
697 		uint32_t hdw;
698 #endif
699 		struct {
700 #if defined(_BIT_FIELDS_HTOL)
701 		uint32_t st_mc_stat:26;
702 		uint32_t res:6;
703 #elif defined(_BIT_FIELDS_LTOH)
704 		uint32_t res:6;
705 		uint32_t st_mc_stat:26;
706 #endif
707 		} ldw;
708 #if !defined(_BIG_ENDIAN)
709 		uint32_t hdw;
710 #endif
711 	} bits;
712 } smx_int_stat_t, *p_smx_int_stat_t;
713 
714 
715 #define		SMX_CTL_REG	(FZC_PIO + 0x00050)
716 
717 typedef union _smx_ctl_t {
718 	uint64_t value;
719 	struct {
720 #if defined(_BIG_ENDIAN)
721 		uint32_t hdw;
722 #endif
723 		struct {
724 #if defined(_BIT_FIELDS_HTOL)
725 		uint32_t res1:21;
726 		uint32_t resp_err_inj:3;
727 		uint32_t res2:1;
728 		uint32_t xtb_err_inj:3;
729 		uint32_t res3:1;
730 		uint32_t dbg_sel:3;
731 #elif defined(_BIT_FIELDS_LTOH)
732 		uint32_t dbg_sel:3;
733 		uint32_t res3:1;
734 		uint32_t xtb_err_inj:3;
735 		uint32_t res2:1;
736 		uint32_t resp_err_inj:3;
737 		uint32_t res1:21;
738 #endif
739 		} ldw;
740 #if !defined(_BIG_ENDIAN)
741 		uint32_t hdw;
742 #endif
743 	} bits;
744 } smx_ctl_t, *p_smx_ctl_t;
745 
746 
747 #define	SMX_DBG_VEC_REG	(FZC_PIO + 0x00058)
748 
749 typedef union _smx_dbg_vec_t {
750 	uint64_t value;
751 	struct {
752 #if defined(_BIG_ENDIAN)
753 		uint32_t hdw;
754 #endif
755 		struct {
756 		uint32_t dbg_tng_vec;
757 		} ldw;
758 #if !defined(_BIG_ENDIAN)
759 		uint32_t hdw;
760 #endif
761 	} bits;
762 } smx_dbg_vec_t, *p_smx_dbg_vec_t;
763 
764 
765 /*
766  * Debug registers
767  */
768 
769 #define	PIO_DBG_SEL_REG	(FZC_PIO + 0x00060)
770 
771 typedef union _pio_dbg_sel_t {
772 	uint64_t value;
773 	struct {
774 #if defined(_BIG_ENDIAN)
775 		uint32_t hdw;
776 #endif
777 		struct {
778 		uint32_t sel;
779 		} ldw;
780 #if !defined(_BIG_ENDIAN)
781 		uint32_t hdw;
782 #endif
783 	} bits;
784 } pio_dbg_sel_t, *p_pio_dbg_sel_t;
785 
786 
787 #define	PIO_TRAIN_VEC_REG	(FZC_PIO + 0x00068)
788 
789 typedef union _pio_tng_vec_t {
790 	uint64_t value;
791 	struct {
792 #if defined(_BIG_ENDIAN)
793 		uint32_t hdw;
794 #endif
795 		struct {
796 		uint32_t training_vec;
797 		} ldw;
798 #if !defined(_BIG_ENDIAN)
799 		uint32_t hdw;
800 #endif
801 	} bits;
802 } pio_tng_vec_t, *p_pio_tng_vec_t;
803 
804 #define	PIO_ARB_CTL_REG	(FZC_PIO + 0x00070)
805 
806 typedef union _pio_arb_ctl_t {
807 	uint64_t value;
808 	struct {
809 #if defined(_BIG_ENDIAN)
810 		uint32_t hdw;
811 #endif
812 		struct {
813 		uint32_t ctl;
814 		} ldw;
815 #if !defined(_BIG_ENDIAN)
816 		uint32_t hdw;
817 #endif
818 	} bits;
819 } pio_arb_ctl_t, *p_pio_arb_ctl_t;
820 
821 #define	PIO_ARB_DBG_VEC_REG	(FZC_PIO + 0x00078)
822 
823 typedef union _pio_arb_dbg_vec_t {
824 	uint64_t value;
825 	struct {
826 #if defined(_BIG_ENDIAN)
827 		uint32_t hdw;
828 #endif
829 		struct {
830 		uint32_t dbg_vector;
831 		} ldw;
832 #if !defined(_BIG_ENDIAN)
833 		uint32_t hdw;
834 #endif
835 	} bits;
836 } pio_arb_dbg_vec_t, *p_pio_arb_dbg_vec_t;
837 
838 
839 /*
840  * GPIO Registers
841  */
842 
843 #define	GPIO_EN_REG	(FZC_PIO + 0x00028)
844 #define	GPIO_EN_ENABLE_MASK	 0x000000000000FFFFULL
845 #define	GPIO_EN_ENABLE_SHIFT	 0
846 typedef union _gpio_en_t {
847 	uint64_t value;
848 	struct {
849 #if defined(_BIG_ENDIAN)
850 		uint32_t hdw;
851 #endif
852 		struct {
853 #if defined(_BIT_FIELDS_HTOL)
854 		uint32_t res:16;
855 		uint32_t enable:16;
856 #elif defined(_BIT_FIELDS_LTOH)
857 		uint32_t enable:16;
858 		uint32_t res:16;
859 #endif
860 		} ldw;
861 #if !defined(_BIG_ENDIAN)
862 		uint32_t hdw;
863 #endif
864 	} bits;
865 } gpio_en_t, *p_gpio_en_t;
866 
867 #define	GPIO_DATA_IN_REG	(FZC_PIO + 0x00030)
868 #define	GPIO_DATA_IN_MASK	0x000000000000FFFFULL
869 #define	GPIO_DATA_IN_SHIFT	0
870 typedef union _gpio_data_in_t {
871 	uint64_t value;
872 	struct {
873 #if defined(_BIG_ENDIAN)
874 		uint32_t hdw;
875 #endif
876 		struct {
877 #if defined(_BIT_FIELDS_HTOL)
878 		uint32_t res:16;
879 		uint32_t data_in:16;
880 #elif defined(_BIT_FIELDS_LTOH)
881 		uint32_t data_in:16;
882 		uint32_t res:16;
883 #endif
884 		} ldw;
885 #if !defined(_BIG_ENDIAN)
886 		uint32_t hdw;
887 #endif
888 	} bits;
889 } gpio_data_in_t, *p_gpio_data_in_t;
890 
891 
892 /*
893  * PCI Express Interface Module (PIM) registers
894  */
895 #define	PIM_CONTROL_REG	(FZC_PIM + 0x0)
896 #define	PIM_CONTROL_DBG_SEL_MASK 0x000000000000000FULL
897 #define	PIM_CONTROL_DBG_SEL_SHIFT	0
898 typedef union _pim_ctl_t {
899 	uint64_t value;
900 	struct {
901 #if defined(_BIG_ENDIAN)
902 		uint32_t hdw;
903 #endif
904 		struct {
905 #if defined(_BIT_FIELDS_HTOL)
906 		uint32_t res:28;
907 		uint32_t dbg_sel:4;
908 #elif defined(_BIT_FIELDS_LTOH)
909 		uint32_t dbg_sel:4;
910 		uint32_t res:28;
911 #endif
912 		} ldw;
913 #if !defined(_BIG_ENDIAN)
914 		uint32_t hdw;
915 #endif
916 	} bits;
917 } pim_ctl_t, *p_pim_ctl_t;
918 
919 #define	PIM_DBG_TRAINING_VEC_REG	(FZC_PIM + 0x00008)
920 #define	PIM_DBG_TRAINING_VEC_MASK	0x00000000FFFFFFFFULL
921 
922 #define	PIM_INTR_STATUS_REG		(FZC_PIM + 0x00010)
923 #define	PIM_INTR_STATUS_MASK		0x00000000FFFFFFFFULL
924 
925 #define	PIM_INTERNAL_STATUS_REG		(FZC_PIM + 0x00018)
926 #define	PIM_INTERNAL_STATUS_MASK	0x00000000FFFFFFFFULL
927 
928 #define	PIM_INTR_MASK_REG		(FZC_PIM + 0x00020)
929 #define	PIM_INTR_MASK_MASK		0x00000000FFFFFFFFULL
930 
931 /*
932  * Partitioning Logical pages Definition registers.
933  * (used by both receive and transmit DMA channels)
934  */
935 
936 /* Logical page definitions */
937 typedef union _log_page_vld_t {
938 	uint64_t value;
939 	struct {
940 #if defined(_BIG_ENDIAN)
941 		uint32_t hdw;
942 #endif
943 		struct {
944 #if defined(_BIT_FIELDS_HTOL)
945 			uint32_t res1_1:28;
946 			uint32_t func:2;
947 			uint32_t page1:1;
948 			uint32_t page0:1;
949 #elif defined(_BIT_FIELDS_LTOH)
950 			uint32_t page0:1;
951 			uint32_t page1:1;
952 			uint32_t func:2;
953 			uint32_t res1_1:28;
954 #endif
955 		} ldw;
956 #if !defined(_BIG_ENDIAN)
957 		uint32_t hdw;
958 #endif
959 	} bits;
960 } log_page_vld_t, *p_log_page_vld_t;
961 
962 
963 #define	DMA_LOG_PAGE_MASK_SHIFT		0
964 #define	DMA_LOG_PAGE_MASK_MASK		0x00000000ffffffffULL
965 
966 /* Receive Logical Page Mask */
967 typedef union _log_page_mask_t {
968 	uint64_t value;
969 	struct {
970 #if defined(_BIG_ENDIAN)
971 		uint32_t hdw;
972 #endif
973 		struct {
974 #if defined(_BIT_FIELDS_HTOL)
975 			uint32_t mask:32;
976 #elif defined(_BIT_FIELDS_LTOH)
977 			uint32_t mask:32;
978 #endif
979 		} ldw;
980 #if !defined(_BIG_ENDIAN)
981 		uint32_t hdw;
982 #endif
983 	} bits;
984 } log_page_mask_t, *p_log_page_mask_t;
985 
986 
987 /* Receive Logical Page Value */
988 #define	DMA_LOG_PAGE_VALUE_SHIFT	0
989 #define	DMA_LOG_PAGE_VALUE_MASK		0x00000000ffffffffULL
990 
991 /* Receive Logical Page Value */
992 typedef union _log_page_value_t {
993 	uint64_t value;
994 	struct {
995 #if defined(_BIG_ENDIAN)
996 		uint32_t hdw;
997 #endif
998 		struct {
999 #if defined(_BIT_FIELDS_HTOL)
1000 			uint32_t value:32;
1001 #elif defined(_BIT_FIELDS_LTOH)
1002 			uint32_t value:32;
1003 #endif
1004 		} ldw;
1005 #if !defined(_BIG_ENDIAN)
1006 		uint32_t hdw;
1007 #endif
1008 	} bits;
1009 } log_page_value_t, *p_log_page_value_t;
1010 
1011 /* Receive Logical Page Relocation */
1012 #define	DMA_LOG_PAGE_RELO_SHIFT		0			/* bits 31:0 */
1013 #define	DMA_LOG_PAGE_RELO_MASK		0x00000000ffffffffULL
1014 
1015 /* Receive Logical Page Relocation */
1016 typedef union _log_page_relo_t {
1017 	uint64_t value;
1018 	struct {
1019 #if defined(_BIG_ENDIAN)
1020 		uint32_t hdw;
1021 #endif
1022 		struct {
1023 #if defined(_BIT_FIELDS_HTOL)
1024 			uint32_t relo:32;
1025 #elif defined(_BIT_FIELDS_LTOH)
1026 			uint32_t relo:32;
1027 #endif
1028 		} ldw;
1029 #if !defined(_BIG_ENDIAN)
1030 		uint32_t hdw;
1031 #endif
1032 	} bits;
1033 } log_page_relo_t, *p_log_page_relo_t;
1034 
1035 
1036 /* Receive Logical Page Handle */
1037 #define	DMA_LOG_PAGE_HANDLE_SHIFT	0			/* bits 19:0 */
1038 #define	DMA_LOG_PAGE_HANDLE_MASK	0x00000000ffffffffULL
1039 
1040 /* Receive Logical Page Handle */
1041 typedef union _log_page_hdl_t {
1042 	uint64_t value;
1043 	struct {
1044 #if defined(_BIG_ENDIAN)
1045 		uint32_t hdw;
1046 #endif
1047 		struct {
1048 #if defined(_BIT_FIELDS_HTOL)
1049 			uint32_t res1_1:12;
1050 			uint32_t handle:20;
1051 #elif defined(_BIT_FIELDS_LTOH)
1052 			uint32_t handle:20;
1053 			uint32_t res1_1:12;
1054 #endif
1055 		} ldw;
1056 #if !defined(_BIG_ENDIAN)
1057 		uint32_t hdw;
1058 #endif
1059 	} bits;
1060 } log_page_hdl_t, *p_log_page_hdl_t;
1061 
1062 #ifdef	__cplusplus
1063 }
1064 #endif
1065 
1066 #endif	/* _SYS_NXGE_NXGE_HW_H */
1067