xref: /illumos-gate/usr/src/uts/common/io/ixgbe/core/ixgbe_phy.h (revision 48ed61a721b0db9229d5bad4d87f5b019867fbf1)
1 /******************************************************************************
2   SPDX-License-Identifier: BSD-3-Clause
3 
4   Copyright (c) 2001-2017, Intel Corporation
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6 
7   Redistribution and use in source and binary forms, with or without
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11       this list of conditions and the following disclaimer.
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13    2. Redistributions in binary form must reproduce the above copyright
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17    3. Neither the name of the Intel Corporation nor the names of its
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19       this software without specific prior written permission.
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21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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33 ******************************************************************************/
34 /*$FreeBSD$*/
35 
36 #ifndef _IXGBE_PHY_H_
37 #define _IXGBE_PHY_H_
38 
39 #include "ixgbe_type.h"
40 #define IXGBE_I2C_EEPROM_DEV_ADDR	0xA0
41 #define IXGBE_I2C_EEPROM_DEV_ADDR2	0xA2
42 #define IXGBE_I2C_EEPROM_BANK_LEN	0xFF
43 
44 /* EEPROM byte offsets */
45 #define IXGBE_SFF_IDENTIFIER		0x0
46 #define IXGBE_SFF_IDENTIFIER_SFP	0x3
47 #define IXGBE_SFF_VENDOR_OUI_BYTE0	0x25
48 #define IXGBE_SFF_VENDOR_OUI_BYTE1	0x26
49 #define IXGBE_SFF_VENDOR_OUI_BYTE2	0x27
50 #define IXGBE_SFF_1GBE_COMP_CODES	0x6
51 #define IXGBE_SFF_10GBE_COMP_CODES	0x3
52 #define IXGBE_SFF_CABLE_TECHNOLOGY	0x8
53 #define IXGBE_SFF_CABLE_SPEC_COMP	0x3C
54 #define IXGBE_SFF_SFF_8472_SWAP		0x5C
55 #define IXGBE_SFF_SFF_8472_COMP		0x5E
56 #define IXGBE_SFF_SFF_8472_OSCB		0x6E
57 #define IXGBE_SFF_SFF_8472_ESCB		0x76
58 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS	0xD
59 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0	0xA5
60 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1	0xA6
61 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2	0xA7
62 #define IXGBE_SFF_QSFP_CONNECTOR	0x82
63 #define IXGBE_SFF_QSFP_10GBE_COMP	0x83
64 #define IXGBE_SFF_QSFP_1GBE_COMP	0x86
65 #define IXGBE_SFF_QSFP_CABLE_LENGTH	0x92
66 #define IXGBE_SFF_QSFP_DEVICE_TECH	0x93
67 
68 /* Bitmasks */
69 #define IXGBE_SFF_DA_PASSIVE_CABLE	0x4
70 #define IXGBE_SFF_DA_ACTIVE_CABLE	0x8
71 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING	0x4
72 #define IXGBE_SFF_1GBASESX_CAPABLE	0x1
73 #define IXGBE_SFF_1GBASELX_CAPABLE	0x2
74 #define IXGBE_SFF_1GBASET_CAPABLE	0x8
75 #define IXGBE_SFF_10GBASESR_CAPABLE	0x10
76 #define IXGBE_SFF_10GBASELR_CAPABLE	0x20
77 #define IXGBE_SFF_SOFT_RS_SELECT_MASK	0x8
78 #define IXGBE_SFF_SOFT_RS_SELECT_10G	0x8
79 #define IXGBE_SFF_SOFT_RS_SELECT_1G	0x0
80 #define IXGBE_SFF_ADDRESSING_MODE	0x4
81 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE	0x1
82 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE	0x8
83 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE	0x23
84 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL	0x0
85 #define IXGBE_I2C_EEPROM_READ_MASK	0x100
86 #define IXGBE_I2C_EEPROM_STATUS_MASK	0x3
87 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION	0x0
88 #define IXGBE_I2C_EEPROM_STATUS_PASS	0x1
89 #define IXGBE_I2C_EEPROM_STATUS_FAIL	0x2
90 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS	0x3
91 
92 #define IXGBE_CS4227			0xBE	/* CS4227 address */
93 #define IXGBE_CS4227_GLOBAL_ID_LSB	0
94 #define IXGBE_CS4227_GLOBAL_ID_MSB	1
95 #define IXGBE_CS4227_SCRATCH		2
96 #define IXGBE_CS4227_GLOBAL_ID_VALUE	0x03E5
97 #define IXGBE_CS4227_EFUSE_PDF_SKU	0x19F
98 #define IXGBE_CS4223_SKU_ID		0x0010	/* Quad port */
99 #define IXGBE_CS4227_SKU_ID		0x0014	/* Dual port */
100 #define IXGBE_CS4227_RESET_PENDING	0x1357
101 #define IXGBE_CS4227_RESET_COMPLETE	0x5AA5
102 #define IXGBE_CS4227_RETRIES		15
103 #define IXGBE_CS4227_EFUSE_STATUS	0x0181
104 #define IXGBE_CS4227_LINE_SPARE22_MSB	0x12AD	/* Reg to program speed */
105 #define IXGBE_CS4227_LINE_SPARE24_LSB	0x12B0	/* Reg to program EDC */
106 #define IXGBE_CS4227_HOST_SPARE22_MSB	0x1AAD	/* Reg to program speed */
107 #define IXGBE_CS4227_HOST_SPARE24_LSB	0x1AB0	/* Reg to program EDC */
108 #define IXGBE_CS4227_EEPROM_STATUS	0x5001
109 #define IXGBE_CS4227_EEPROM_LOAD_OK	0x0001
110 #define IXGBE_CS4227_SPEED_1G		0x8000
111 #define IXGBE_CS4227_SPEED_10G		0
112 #define IXGBE_CS4227_EDC_MODE_CX1	0x0002
113 #define IXGBE_CS4227_EDC_MODE_SR	0x0004
114 #define IXGBE_CS4227_EDC_MODE_DIAG	0x0008
115 #define IXGBE_CS4227_RESET_HOLD		500	/* microseconds */
116 #define IXGBE_CS4227_RESET_DELAY	450	/* milliseconds */
117 #define IXGBE_CS4227_CHECK_DELAY	30	/* milliseconds */
118 #define IXGBE_PE			0xE0	/* Port expander address */
119 #define IXGBE_PE_OUTPUT			1	/* Output register offset */
120 #define IXGBE_PE_CONFIG			3	/* Config register offset */
121 #define IXGBE_PE_BIT1			(1 << 1)
122 
123 /* Flow control defines */
124 #define IXGBE_TAF_SYM_PAUSE		0x400
125 #define IXGBE_TAF_ASM_PAUSE		0x800
126 
127 /* Bit-shift macros */
128 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT	24
129 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT	16
130 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT	8
131 
132 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
133 #define IXGBE_SFF_VENDOR_OUI_TYCO	0x00407600
134 #define IXGBE_SFF_VENDOR_OUI_FTL	0x00906500
135 #define IXGBE_SFF_VENDOR_OUI_AVAGO	0x00176A00
136 #define IXGBE_SFF_VENDOR_OUI_INTEL	0x001B2100
137 
138 /* I2C SDA and SCL timing parameters for standard mode */
139 #define IXGBE_I2C_T_HD_STA	4
140 #define IXGBE_I2C_T_LOW		5
141 #define IXGBE_I2C_T_HIGH	4
142 #define IXGBE_I2C_T_SU_STA	5
143 #define IXGBE_I2C_T_HD_DATA	5
144 #define IXGBE_I2C_T_SU_DATA	1
145 #define IXGBE_I2C_T_RISE	1
146 #define IXGBE_I2C_T_FALL	1
147 #define IXGBE_I2C_T_SU_STO	4
148 #define IXGBE_I2C_T_BUF		5
149 
150 #ifndef IXGBE_SFP_DETECT_RETRIES
151 #define IXGBE_SFP_DETECT_RETRIES	10
152 
153 #endif /* IXGBE_SFP_DETECT_RETRIES */
154 #define IXGBE_TN_LASI_STATUS_REG	0x9005
155 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM	0x0008
156 
157 /* SFP+ SFF-8472 Compliance */
158 #define IXGBE_SFF_SFF_8472_UNSUP	0x00
159 
160 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
161 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
162 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
163 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
164 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
165 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
166 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
167 			   u16 *phy_data);
168 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
169 			    u16 phy_data);
170 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
171 			       u32 device_type, u16 *phy_data);
172 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
173 				u32 device_type, u16 phy_data);
174 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
175 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
176 				       ixgbe_link_speed speed,
177 				       bool autoneg_wait_to_complete);
178 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
179 					       ixgbe_link_speed *speed,
180 					       bool *autoneg);
181 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
182 
183 /* PHY specific */
184 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
185 			     ixgbe_link_speed *speed,
186 			     bool *link_up);
187 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
188 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
189 				       u16 *firmware_version);
190 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
191 					   u16 *firmware_version);
192 
193 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
194 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
195 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
196 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
197 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);
198 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
199 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
200 					u16 *list_offset,
201 					u16 *data_offset);
202 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
203 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
204 				u8 dev_addr, u8 *data);
205 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
206 					 u8 dev_addr, u8 *data);
207 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
208 				 u8 dev_addr, u8 data);
209 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
210 					  u8 dev_addr, u8 data);
211 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
212 				  u8 *eeprom_data);
213 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
214 				   u8 eeprom_data);
215 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
216 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
217 					u16 *val, bool lock);
218 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
219 					 u16 val, bool lock);
220 #endif /* _IXGBE_PHY_H_ */
221