xref: /illumos-gate/usr/src/uts/common/io/igc/core/igc_phy.h (revision 6bbbd4428a21d3f4d1d329851dbc599121cb5d31)
1 /*-
2  * Copyright 2021 Intel Corp
3  * Copyright 2021 Rubicon Communications, LLC (Netgate)
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef _IGC_PHY_H_
8 #define _IGC_PHY_H_
9 
10 void igc_init_phy_ops_generic(struct igc_hw *hw);
11 s32  igc_null_read_reg(struct igc_hw *hw, u32 offset, u16 *data);
12 void igc_null_phy_generic(struct igc_hw *hw);
13 s32  igc_null_lplu_state(struct igc_hw *hw, bool active);
14 s32  igc_null_write_reg(struct igc_hw *hw, u32 offset, u16 data);
15 s32  igc_null_set_page(struct igc_hw *hw, u16 data);
16 s32  igc_check_downshift_generic(struct igc_hw *hw);
17 s32  igc_check_reset_block_generic(struct igc_hw *hw);
18 s32  igc_get_phy_id(struct igc_hw *hw);
19 void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl);
20 s32  igc_phy_hw_reset_generic(struct igc_hw *hw);
21 s32  igc_phy_reset_dsp_generic(struct igc_hw *hw);
22 s32  igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active);
23 s32  igc_setup_copper_link_generic(struct igc_hw *hw);
24 s32  igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
25 				u32 usec_interval, bool *success);
26 enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id);
27 s32  igc_determine_phy_address(struct igc_hw *hw);
28 s32  igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
29 s32  igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
30 void igc_power_up_phy_copper(struct igc_hw *hw);
31 void igc_power_down_phy_copper(struct igc_hw *hw);
32 s32  igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data);
33 s32  igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data);
34 
35 s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
36 			 u16 *data);
37 s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
38 			  u16 data);
39 s32  igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data);
40 s32  igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data);
41 
42 #define IGC_MAX_PHY_ADDR		8
43 
44 /* IGP01IGC Specific Registers */
45 #define IGP01IGC_PHY_PORT_CONFIG	0x10 /* Port Config */
46 #define IGP01IGC_PHY_PORT_STATUS	0x11 /* Status */
47 #define IGP01IGC_PHY_PORT_CTRL	0x12 /* Control */
48 #define IGP01IGC_PHY_LINK_HEALTH	0x13 /* PHY Link Health */
49 #define IGP02IGC_PHY_POWER_MGMT	0x19 /* Power Management */
50 #define IGP01IGC_PHY_PAGE_SELECT	0x1F /* Page Select */
51 #define BM_PHY_PAGE_SELECT		22   /* Page Select for BM */
52 #define IGP_PAGE_SHIFT			5
53 #define PHY_REG_MASK			0x1F
54 #define IGC_I225_PHPM			0x0E14 /* I225 PHY Power Management */
55 #define IGC_I225_PHPM_DIS_1000_D3	0x0008 /* Disable 1G in D3 */
56 #define IGC_I225_PHPM_LINK_ENERGY	0x0010 /* Link Energy Detect */
57 #define IGC_I225_PHPM_GO_LINKD	0x0020 /* Go Link Disconnect */
58 #define IGC_I225_PHPM_DIS_1000	0x0040 /* Disable 1G globally */
59 #define IGC_I225_PHPM_SPD_B2B_EN	0x0080 /* Smart Power Down Back2Back */
60 #define IGC_I225_PHPM_RST_COMPL	0x0100 /* PHY Reset Completed */
61 #define IGC_I225_PHPM_DIS_100_D3	0x0200 /* Disable 100M in D3 */
62 #define IGC_I225_PHPM_ULP		0x0400 /* Ultra Low-Power Mode */
63 #define IGC_I225_PHPM_DIS_2500	0x0800 /* Disable 2.5G globally */
64 #define IGC_I225_PHPM_DIS_2500_D3	0x1000 /* Disable 2.5G in D3 */
65 /* GPY211 - I225 defines */
66 #define GPY_MMD_MASK			0xFFFF0000
67 #define GPY_MMD_SHIFT			16
68 #define GPY_REG_MASK			0x0000FFFF
69 #define IGP01IGC_PHY_PCS_INIT_REG	0x00B4
70 #define IGP01IGC_PHY_POLARITY_MASK	0x0078
71 
72 #define IGP01IGC_PSCR_AUTO_MDIX	0x1000
73 #define IGP01IGC_PSCR_FORCE_MDI_MDIX	0x2000 /* 0=MDI, 1=MDIX */
74 
75 #define IGP01IGC_PSCFR_SMART_SPEED	0x0080
76 
77 #define IGP02IGC_PM_SPD		0x0001 /* Smart Power Down */
78 #define IGP02IGC_PM_D0_LPLU		0x0002 /* For D0a states */
79 #define IGP02IGC_PM_D3_LPLU		0x0004 /* For all other states */
80 
81 #define IGP01IGC_PLHR_SS_DOWNGRADE	0x8000
82 
83 #define IGP01IGC_PSSR_POLARITY_REVERSED	0x0002
84 #define IGP01IGC_PSSR_MDIX		0x0800
85 #define IGP01IGC_PSSR_SPEED_MASK	0xC000
86 #define IGP01IGC_PSSR_SPEED_1000MBPS	0xC000
87 
88 #define IGP02IGC_PHY_CHANNEL_NUM	4
89 #define IGP02IGC_PHY_AGC_A		0x11B1
90 #define IGP02IGC_PHY_AGC_B		0x12B1
91 #define IGP02IGC_PHY_AGC_C		0x14B1
92 #define IGP02IGC_PHY_AGC_D		0x18B1
93 
94 #define IGP02IGC_AGC_LENGTH_SHIFT	9   /* Course=15:13, Fine=12:9 */
95 #define IGP02IGC_AGC_LENGTH_MASK	0x7F
96 #define IGP02IGC_AGC_RANGE		15
97 
98 #define IGC_CABLE_LENGTH_UNDEFINED	0xFF
99 
100 #define IGC_KMRNCTRLSTA_OFFSET	0x001F0000
101 #define IGC_KMRNCTRLSTA_OFFSET_SHIFT	16
102 #define IGC_KMRNCTRLSTA_REN		0x00200000
103 #define IGC_KMRNCTRLSTA_DIAG_OFFSET	0x3    /* Kumeran Diagnostic */
104 #define IGC_KMRNCTRLSTA_TIMEOUTS	0x4    /* Kumeran Timeouts */
105 #define IGC_KMRNCTRLSTA_INBAND_PARAM	0x9    /* Kumeran InBand Parameters */
106 #define IGC_KMRNCTRLSTA_IBIST_DISABLE	0x0200 /* Kumeran IBIST Disable */
107 #define IGC_KMRNCTRLSTA_DIAG_NELPBK	0x1000 /* Nearend Loopback mode */
108 
109 #define IFE_PHY_EXTENDED_STATUS_CONTROL	0x10
110 #define IFE_PHY_SPECIAL_CONTROL		0x11 /* 100BaseTx PHY Special Ctrl */
111 #define IFE_PHY_SPECIAL_CONTROL_LED	0x1B /* PHY Special and LED Ctrl */
112 #define IFE_PHY_MDIX_CONTROL		0x1C /* MDI/MDI-X Control */
113 
114 /* IFE PHY Extended Status Control */
115 #define IFE_PESC_POLARITY_REVERSED	0x0100
116 
117 /* IFE PHY Special Control */
118 #define IFE_PSC_AUTO_POLARITY_DISABLE	0x0010
119 #define IFE_PSC_FORCE_POLARITY		0x0020
120 
121 /* IFE PHY Special Control and LED Control */
122 #define IFE_PSCL_PROBE_MODE		0x0020
123 #define IFE_PSCL_PROBE_LEDS_OFF		0x0006 /* Force LEDs 0 and 2 off */
124 #define IFE_PSCL_PROBE_LEDS_ON		0x0007 /* Force LEDs 0 and 2 on */
125 
126 /* IFE PHY MDIX Control */
127 #define IFE_PMC_MDIX_STATUS		0x0020 /* 1=MDI-X, 0=MDI */
128 #define IFE_PMC_FORCE_MDIX		0x0040 /* 1=force MDI-X, 0=force MDI */
129 #define IFE_PMC_AUTO_MDIX		0x0080 /* 1=enable auto, 0=disable */
130 
131 #endif
132