xref: /illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/phy_reg.h (revision d14abf155341d55053c76eeec58b787a456b753b)
1 #ifndef PHY_REG_H
2 #define PHY_REG_H
3 
4 #define MDIO_REG_BANK_CL73_IEEEB0                       0x0
5     #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL                0x0
6         #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN     0x0200
7         #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN          0x1000
8         #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST       0x8000
9 
10 #define MDIO_REG_BANK_CL73_IEEEB1                       0x10
11     #define MDIO_CL73_IEEEB1_AN_ADV2                        0x01
12         #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M             0x0000
13         #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX          0x0020
14         #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4           0x0040
15         #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR            0x0080
16 
17 #define MDIO_REG_BANK_RX0                               0x80b0
18     #define MDIO_RX0_RX_EQ_BOOST                            0x1c
19         #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
20         #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL                0x10
21 
22 #define MDIO_REG_BANK_RX1                               0x80c0
23     #define MDIO_RX1_RX_EQ_BOOST                            0x1c
24         #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
25         #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL                0x10
26 
27 #define MDIO_REG_BANK_RX2                               0x80d0
28     #define MDIO_RX2_RX_EQ_BOOST                            0x1c
29         #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
30         #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL                0x10
31 
32 #define MDIO_REG_BANK_RX3                               0x80e0
33     #define MDIO_RX3_RX_EQ_BOOST                            0x1c
34         #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK        0x7
35         #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL                0x10
36 
37 #define MDIO_REG_BANK_RX_ALL                            0x80f0
38     #define MDIO_RX_ALL_RX_EQ_BOOST                         0x1c
39         #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK     0x7
40         #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL             0x10
41 
42 #define MDIO_REG_BANK_TX0                               0x8060
43     #define MDIO_TX0_TX_DRIVER                              0x17
44         #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
45         #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
46         #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
47         #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
48         #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
49         #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
50         #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
51         #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
52         #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
53 
54 #define MDIO_REG_BANK_TX1                               0x8070
55     #define MDIO_TX1_TX_DRIVER                              0x17
56         #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
57         #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
58         #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
59         #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
60         #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
61         #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
62         #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
63         #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
64         #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
65 
66 #define MDIO_REG_BANK_TX2                               0x8080
67     #define MDIO_TX2_TX_DRIVER                              0x17
68         #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
69         #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
70         #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
71         #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
72         #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
73         #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
74         #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
75         #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
76         #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
77 
78 #define MDIO_REG_BANK_TX3                               0x8090
79     #define MDIO_TX3_TX_DRIVER                              0x17
80         #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK             0xf000
81         #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT            12
82         #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK                 0x0f00
83         #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT                8
84         #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK              0x00f0
85         #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT             4
86         #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK                0x000e
87         #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT               1
88         #define MDIO_TX0_TX_DRIVER_ICBUF1T                      1
89 
90 #define MDIO_REG_BANK_XGXS_BLOCK0                       0x8000
91     #define MDIO_BLOCK0_XGXS_CONTROL                        0x10
92 
93 #define MDIO_REG_BANK_XGXS_BLOCK1                       0x8010
94     #define MDIO_BLOCK1_LANE_CTRL0                          0x15
95     #define MDIO_BLOCK1_LANE_CTRL1                          0x16
96     #define MDIO_BLOCK1_LANE_CTRL2                          0x17
97     #define MDIO_BLOCK1_LANE_PRBS                           0x19
98 
99 #define MDIO_REG_BANK_XGXS_BLOCK2                       0x8100
100     #define MDIO_XGXS_BLOCK2_RX_LN_SWAP                     0x10
101         #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE              0x8000
102         #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE        0x4000
103     #define MDIO_XGXS_BLOCK2_TX_LN_SWAP                     0x11
104         #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE              0x8000
105     #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G               0x14
106         #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS      0x0001
107         #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS    0x0010
108     #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE                 0x15
109 
110 #define MDIO_REG_BANK_GP_STATUS                         0x8120
111     #define MDIO_GP_STATUS_TOP_AN_STATUS1                       0x1B
112         #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
113         #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
114         #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS           0x0004 //1= link up;0= link down
115         #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS         0x0008 //1= full-duplex; 0= half-duplex
116         #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 //1 = Indicates that the LP and the LD supports
117         #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE   0x0020 // the BAM function for Clause 37 AN. This bit is
118                                                                            // asserted when both the LD and the LP have
119                                                                            // successfully exchanged BAM73 NPs and, therefore,
120                                                                            // determined that a switch over to CL37 AN will follow
121 
122         #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
123         #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
124         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK	    0x3f00
125         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M      0x0000 //bits [13:8]
126         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M     0x0100 //bits [13:8]
127         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G       0x0200 //bits [13:8]
128         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G     0x0300 //bits [13:8]
129         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G       0x0400 //bits [13:8]
130         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G       0x0500 //bits [13:8]
131         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG  0x0600 //bits [13:8]
132         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4  0x0700 //bits [13:8]
133         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG  0x0800 //bits [13:8]
134         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G    0x0900 //bits [13:8]
135         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G      0x0A00 //bits [13:8]
136         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G      0x0B00 //bits [13:8]
137         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G      0x0C00 //bits [13:8]
138         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX    0x0D00 //bits [13:8]
139         #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4  0x0E00 //bits [13:8]
140 
141 
142 #define MDIO_REG_BANK_10G_PARALLEL_DETECT               0x8130
143     #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL        0x11
144         #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
145     #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK           0x13
146         #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT       (0xb71<<1)
147 
148 #define MDIO_REG_BANK_SERDES_DIGITAL                    0x8300
149     #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1            0x10
150         #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 //1= Fiber mode (1000X); 0= SGMII mode
151         #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF     0x0002 //1= Ten Bit Interface; 0= GMII interface
152         #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN     0x0004
153         #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
154         #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET    0x0010
155         #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE  0x0020
156     #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2            0x11
157         #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN  0x0001
158         #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
159     #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1             0x14
160         #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX      0x0004 //1= full-duplex; 0= half-duplex
161         #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK  0x0018
162         #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
163         #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G  0x0018
164         #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G    0x0010
165         #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M  0x0008
166         #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M   0x0000
167     #define MDIO_SERDES_DIGITAL_MISC1                       0x18
168         #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK       0xE000
169         #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M        0x0000
170         #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M       0x2000
171         #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M       0x4000
172         #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M    0x6000
173         #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M     0x8000
174         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL       0x0010
175         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK      0x000f
176         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G      0x0000
177         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G        0x0001
178         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G        0x0002
179         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG   0x0003
180         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4   0x0004
181         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G       0x0005
182         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G     0x0006
183         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G       0x0007
184         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G       0x0008
185         #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G       0x0009
186 
187 #define MDIO_REG_BANK_OVER_1G                           0x8320
188     #define MDIO_OVER_1G_DIGCTL_3_4                         0x14
189         #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK              0xffe0 //message page ID for over 1G next pages
190         #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT             5
191     #define MDIO_OVER_1G_UP1                                0x19
192         #define MDIO_OVER_1G_UP1_2_5G                           0x0001
193         #define MDIO_OVER_1G_UP1_5G                             0x0002
194         #define MDIO_OVER_1G_UP1_6G                             0x0004
195         #define MDIO_OVER_1G_UP1_10G                            0x0010
196         #define MDIO_OVER_1G_UP1_10GH                           0x0008
197 //        #define MDIO_OVER_1G_UP1_10G                            0x0008 - yaronw
198 //        #define MDIO_OVER_1G_UP1_10GH                           0x0010 - yaronw
199         #define MDIO_OVER_1G_UP1_12G                            0x0020
200         #define MDIO_OVER_1G_UP1_12_5G                          0x0040
201         #define MDIO_OVER_1G_UP1_13G                            0x0080
202         #define MDIO_OVER_1G_UP1_15G                            0x0100
203         #define MDIO_OVER_1G_UP1_16G                            0x0200
204     #define MDIO_OVER_1G_UP2                                0x1A
205         #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK                0x0007
206         #define MDIO_OVER_1G_UP2_IDRIVER_MASK                   0x0038
207         #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK               0x03C0
208     #define MDIO_OVER_1G_UP3                                0x1B
209         #define MDIO_OVER_1G_UP3_HIGIG2                         0x0001
210     #define MDIO_OVER_1G_LP_UP1                             0x1C
211     #define MDIO_OVER_1G_LP_UP2                             0x1D
212         #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK         0x03ff
213         #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK            0x0780
214         #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT           7
215     #define MDIO_OVER_1G_LP_UP3                             0x1E
216 
217 #define MDIO_REG_BANK_BAM_NEXT_PAGE                     0x8350
218     #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL           0x10
219         #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE  0x0001  //force teton_mode override
220         #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN  0x0002  //force teton_mode override value
221 
222 #define MDIO_REG_BANK_CL73_USERB0                       0x8370
223     #define MDIO_CL73_USERB0_CL73_BAM_CTRL1                 0x12
224         #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN                  0x8000 //Clause73 BAM73 AN enable
225         #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN     0x4000 //BAM73 Station Manager enable
226         #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN      0x2000 //Enables STA to send BAM73 Next Pagess immediately after Base Page; otherwise send BAM73 NPs following software NPs
227     #define MDIO_CL73_USERB0_CL73_BAM_CTRL3                 0x14
228         #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
229 
230 #define MDIO_REG_BANK_AER_BLOCK                         0xFFD0 // Address Expansion Register
231     #define MDIO_AER_BLOCK_AER_REG                          0x1E
232 
233 #define MDIO_REG_BANK_COMBO_IEEE0                       0xFFE0
234     #define MDIO_COMBO_IEEE0_MII_CONTROL                    0x10
235         #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK   0x2040 //The 2 bits are split
236         #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10     0x0000
237         #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100    0x2000
238         #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000   0x0040
239         #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX         0x0100 //0=half duplex
240         #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN          0x0200
241         #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN               0x1000
242         #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK            0x4000
243         #define MDIO_COMBO_IEEO_MII_CONTROL_RESET               0x8000
244     #define MDIO_COMBO_IEEE0_MII_STATUS                     0x11
245         #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS           0x0004 //status: 0=link fail; 1=link pass
246         #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE    0x0020
247     #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV                   0x14
248         #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX       0x0020
249         #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX       0x0040
250         #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK        0x0180
251         #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE        0x0000
252         #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC   0x0080
253         #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC  0x0100
254         #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH        0x0180
255         #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE         0x8000 //supports additional pages using NP function
256     #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
257         #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE    0x8000 //1=LP is NP able; 0= not able
258         #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK          0x4000 //1=LP has received link code word
259         #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK   0x0180
260         #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE        0x0000
261         //#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_SYMMETRIC   0x0080
262         //#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_ASYMMETRIC  0x0100
263         #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH        0x0180
264         #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
265         #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
266         // When the link partner is in SGMII mode (bit 0 = 1), then
267         // bit 15 = link, bit 12 = duplex, bits 11:10 = speed, bit 14 = acknowledge.
268         // The other bits are reserved and should be zero
269         #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE   0x0001 //1=SGMII mode; 0=fiber mode
270 
271 
272 // Optical Ext PHY (8705/6) registers
273         #define EXT_PHY_AUTO_NEG_DEVAD                          0x7
274         #define EXT_PHY_OPT_PMA_PMD_DEVAD                       0x1
275         #define EXT_PHY_OPT_WIS_DEVAD                           0x2
276         #define EXT_PHY_OPT_PCS_DEVAD                           0x3
277         #define EXT_PHY_OPT_PHY_XS_DEVAD                        0x4
278         #define EXT_PHY_OPT_CNTL                                0x0
279         #define EXT_PHY_OPT_CNTL2                               0x7
280         #define EXT_PHY_OPT_PMD_RX_SD                           0xa
281         #define EXT_PHY_OPT_PMD_MISC_CNTL                       0xca0a
282         #define EXT_PHY_OPT_PHY_IDENTIFIER                      0xc800
283         #define EXT_PHY_OPT_PMD_DIGITAL_CNT                     0xc808
284         #define EXT_PHY_OPT_PMD_DIGITAL_SATUS                   0xc809
285         #define EXT_PHY_OPT_CMU_PLL_BYPASS                      0xca09
286         #define EXT_PHY_OPT_LASI_CNTL                           0x9002
287         #define EXT_PHY_OPT_RX_ALARM                            0x9003
288         #define EXT_PHY_OPT_LASI_STATUS                         0x9005
289         #define EXT_PHY_OPT_PCS_STATUS                          0x0020
290         #define EXT_PHY_OPT_XGXS_LANE_STATUS                    0x0018
291         #define EXT_PHY_OPT_AN_LINK_STATUS                      0x8304
292         #define EXT_PHY_OPT_AN_CL37_CL73                        0x8370
293         #define EXT_PHY_OPT_AN_CL37_FD                          0xffe4
294         #define EXT_PHY_OPT_AN_CL37_AN                          0xffe0
295         #define EXT_PHY_OPT_AN_ADV                              0x11
296 
297 // KR (8072) Registers
298         #define EXT_PHY_KR_PMA_PMD_DEVAD                        0x1
299         #define EXT_PHY_KR_PCS_DEVAD                            0x3
300         #define EXT_PHY_KR_AUTO_NEG_DEVAD                       0x7
301         #define EXT_PHY_KR_CTRL                                 0x0000
302         #define EXT_PHY_KR_STATUS                               0x0001
303         #define EXT_PHY_KR_AUTO_NEG_COMPLETE                    0x0020 //bit5
304         #define EXT_PHY_KR_AUTO_NEG_ADVERT                      0x0010
305         #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE                0x0400 //bit10
306         #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC     0x0800 //bit11
307         #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH           0x0C00 //bit10+bit11
308         #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK           0x0C00 //bit10+bit11
309         #define EXT_PHY_KR_LP_AUTO_NEG                          0x0013
310         #define EXT_PHY_KR_CTRL2                                0x0007
311         #define EXT_PHY_KR_PCS_STATUS                           0x0020
312         #define EXT_PHY_KR_PMD_CTRL                             0x0096
313         #define EXT_PHY_KR_LASI_CNTL                            0x9002
314         #define EXT_PHY_KR_LASI_STATUS                          0x9005
315         #define EXT_PHY_KR_MISC_CTRL1                           0xca85
316         #define EXT_PHY_KR_GEN_CTRL                             0xca10
317         #define EXT_PHY_KR_ROM_CODE                             0xca19
318         #define EXT_PHY_KR_ROM_RESET_INTERNAL_MP                0x0188
319         #define EXT_PHY_KR_ROM_MICRO_RESET                      0x018a
320 
321 // SFX7101 Registers
322         #define EXT_PHY_SFX7101_XGXS_TEST1                      0xc00a
323 
324 
325 #endif //PHY_REG_H
326