xref: /illumos-gate/usr/src/uts/common/io/atge/atge_cmn_reg.h (revision 5e8715b93d1d651ab2805b5e6e98b17df49fa92f)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2012 Gary Mills
23  *
24  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
25  * Use is subject to license terms.
26  */
27 /*
28  * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
29  * All rights reserved.
30  *
31  * Redistribution and use in source and binary forms, with or without
32  * modification, are permitted provided that the following conditions
33  * are met:
34  * 1. Redistributions of source code must retain the above copyright
35  *    notice unmodified, this list of conditions, and the following
36  *    disclaimer.
37  * 2. Redistributions in binary form must reproduce the above copyright
38  *    notice, this list of conditions and the following disclaimer in the
39  *    documentation and/or other materials provided with the distribution.
40  *
41  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
51  * SUCH DAMAGE.
52  */
53 
54 #ifndef _ATGE_CMN_REG_H
55 #define	_ATGE_CMN_REG_H
56 
57 #ifdef __cplusplus
58 	extern "C" {
59 #endif
60 
61 #define	ATGE_SPI_CTRL	0x200
62 #define	SPI_VPD_ENB	0x00002000
63 
64 #define	PCIE_DEVCTRL	0x0060	/* L1 */
65 
66 /*
67  * Station Address
68  */
69 #define	ATGE_PAR0		0x1488
70 #define	ATGE_PAR1		0x148C
71 
72 #define	ATGE_MASTER_CFG		0x1400
73 #define	MASTER_RESET		0x00000001
74 #define	MASTER_ITIMER_ENB	0x00000004	/* L1 */
75 #define	MASTER_MANUAL_INT_ENB	0x00000008
76 #define	MASTER_INT_RDCLR	0x00000040
77 #define	MASTER_SA_TIMER_ENB	0x00000080
78 #define	MASTER_MTIMER_ENB	0x00000100
79 #define	MASTER_LED_MODE		0x00000200
80 #define	MASTER_MANUAL_INTR_ENB	0x00000200
81 #define	MASTER_IM_TX_TIMER_ENB	0x00000400
82 #define	MASTER_IM_RX_TIMER_ENB	0x00000800
83 #define	MASTER_CLK_SEL_DIS	0x00001000
84 #define	MASTER_CLK_SWH_MODE	0x00002000
85 #define	MASTER_INTR_RD_CLR	0x00004000
86 #define	MASTER_CHIP_REV_MASK	0x00FF0000
87 #define	MASTER_CHIP_ID_MASK	0xFF000000
88 #define	MASTER_CHIP_ID_MASKXXX	0x7F000000 /* XXX */
89 #define	MASTER_OTP_SEL		0x80000000
90 #define	MASTER_TEST_MODE_SHIFT	2
91 #define	MASTER_CHIP_REV_SHIFT	16
92 #define	MASTER_CHIP_ID_SHIFT	24
93 
94 #define	ATGE_RESET_TIMEOUT	100
95 
96 #define	ATGE_IDLE_STATUS	0x1410
97 #define	IDLE_STATUS_RXMAC	0x00000001
98 #define	IDLE_STATUS_TXMAC	0x00000002
99 #define	IDLE_STATUS_RXQ		0x00000004
100 #define	IDLE_STATUS_TXQ		0x00000008
101 #define	IDLE_STATUS_DMARD	0x00000010
102 #define	IDLE_STATUS_DMAWR	0x00000020
103 #define	IDLE_STATUS_SMB		0x00000040
104 #define	IDLE_STATUS_CMB		0x00000080
105 
106 #define	ATGE_SERDES_LOCK		0x1424
107 #define	SERDES_LOCK_DET			0x00000001
108 #define	SERDES_LOCK_DET_ENB		0x00000002
109 #define	SERDES_MAC_CLK_SLOWDOWN		0x00020000
110 #define	SERDES_PHY_CLK_SLOWDOWN		0x00040000
111 
112 #define	ATGE_MAC_CFG			0x1480
113 #define	ATGE_CFG_TX_ENB			0x00000001
114 #define	ATGE_CFG_RX_ENB			0x00000002
115 #define	ATGE_CFG_TX_FC			0x00000004
116 #define	ATGE_CFG_RX_FC			0x00000008
117 #define	ATGE_CFG_LOOP			0x00000010
118 #define	ATGE_CFG_FULL_DUPLEX		0x00000020
119 #define	ATGE_CFG_TX_CRC_ENB		0x00000040
120 #define	ATGE_CFG_TX_AUTO_PAD		0x00000080
121 #define	ATGE_CFG_TX_LENCHK		0x00000100
122 #define	ATGE_CFG_RX_JUMBO_ENB		0x00000200
123 #define	ATGE_CFG_PREAMBLE_MASK		0x00003C00
124 #define	ATGE_CFG_VLAN_TAG_STRIP		0x00004000
125 #define	ATGE_CFG_PROMISC		0x00008000
126 #define	ATGE_CFG_TX_PAUSE		0x00010000
127 #define	ATGE_CFG_SCNT			0x00020000
128 #define	ATGE_CFG_SYNC_RST_TX		0x00040000
129 #define	ATGE_CFG_SPEED_MASK		0x00300000
130 #define	ATGE_CFG_SPEED_10_100		0x00100000
131 #define	ATGE_CFG_SPEED_1000		0x00200000
132 #define	ATGE_CFG_DBG_TX_BACKOFF		0x00400000
133 #define	ATGE_CFG_TX_JUMBO_ENB		0x00800000
134 #define	ATGE_CFG_RXCSUM_ENB		0x01000000
135 #define	ATGE_CFG_ALLMULTI		0x02000000
136 #define	ATGE_CFG_BCAST			0x04000000
137 #define	ATGE_CFG_DBG			0x08000000
138 #define	ATGE_CFG_SINGLE_PAUSE_ENB	0x10000000
139 #define	ATGE_CFG_HASH_ALG_CRC32		0x20000000
140 #define	ATGE_CFG_SPEED_MODE_SW		0x40000000
141 #define	ATGE_CFG_PREAMBLE_SHIFT		10
142 #define	ATGE_CFG_PREAMBLE_DEFAULT	7
143 
144 /*
145  * Interrupt related registers.
146  */
147 #define	ATGE_INTR_MASK			0x1604
148 #define	ATGE_INTR_STATUS		0x1600
149 #define	INTR_SMB			0x00000001
150 #define	INTR_MOD_TIMER			0x00000002
151 #define	INTR_MANUAL_TIMER		0x00000004
152 #define	INTR_RX_FIFO_OFLOW		0x00000008
153 #define	INTR_RD_UNDERRUN		0x00000010
154 #define	INTR_RRD_OFLOW			0x00000020
155 #define	INTR_TX_FIFO_UNDERRUN		0x00000040
156 #define	INTR_LINK_CHG			0x00000080
157 #define	INTR_HOST_RD_UNDERRUN		0x00000100
158 #define	INTR_HOST_RRD_OFLOW		0x00000200
159 #define	INTR_DMA_RD_TO_RST		0x00000400
160 #define	INTR_DMA_WR_TO_RST		0x00000800
161 #define	INTR_GPHY			0x00001000
162 #define	INTR_RX_PKT			0x00010000
163 #define	INTR_TX_PKT			0x00020000
164 #define	INTR_TX_DMA			0x00040000	/* L1 intr status */
165 #define	INTR_MAC_RX			0x00400000
166 #define	INTR_MAC_TX			0x00800000
167 #define	INTR_UNDERRUN			0x01000000
168 #define	INTR_FRAME_ERROR		0x02000000
169 #define	INTR_FRAME_OK			0x04000000
170 #define	INTR_CSUM_ERROR			0x08000000
171 #define	INTR_PHY_LINK_DOWN		0x10000000
172 #define	INTR_DIS_SM			0x20000000
173 #define	INTR_DIS_DMA			0x40000000
174 #define	INTR_DIS_INT			0x80000000
175 
176 /* L1E intr status */
177 #define	INTR_RX_PKT1			0x00080000
178 #define	INTR_RX_PKT2			0x00100000
179 #define	INTR_RX_PKT3			0x00200000
180 
181 /*
182  * L1E specific errors. We keep it here since some errors are common for
183  * both L1 and L1E chip.
184  *
185  */
186 #define	L1E_INTR_ERRORS		\
187 	(INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)
188 
189 /*
190  * TXQ CFG registers.
191  */
192 #define	ATGE_TXQ_CFG			0x1580
193 #define	TXQ_CFG_TPD_BURST_MASK		0x0000000F
194 #define	TXQ_CFG_ENB			0x00000020
195 #define	TXQ_CFG_ENHANCED_MODE		0x00000040
196 #define	TXQ_CFG_TX_FIFO_BURST_MASK	0xFFFF0000
197 #define	TXQ_CFG_TPD_BURST_SHIFT		0
198 #define	TXQ_CFG_TPD_BURST_DEFAULT	4
199 #define	TXQ_CFG_TX_FIFO_BURST_SHIFT	16
200 #define	TXQ_CFG_TX_FIFO_BURST_DEFAULT	256
201 
202 /*
203  * Common registers for DMA CFG.
204  */
205 #define	ATGE_DMA_CFG			0x15C0
206 #define	DMA_CFG_IN_ORDER		0x00000001
207 #define	DMA_CFG_ENH_ORDER		0x00000002
208 #define	DMA_CFG_OUT_ORDER		0x00000004
209 #define	DMA_CFG_RCB_64			0x00000000
210 #define	DMA_CFG_RCB_128			0x00000008
211 #define	DMA_CFG_RD_BURST_128		0x00000000
212 #define	DMA_CFG_RD_BURST_256		0x00000010
213 #define	DMA_CFG_RD_BURST_512		0x00000020
214 #define	DMA_CFG_RD_BURST_1024		0x00000030
215 #define	DMA_CFG_RD_BURST_2048		0x00000040
216 #define	DMA_CFG_RD_BURST_4096		0x00000050
217 #define	DMA_CFG_WR_BURST_128		0x00000000
218 #define	DMA_CFG_WR_BURST_256		0x00000080
219 #define	DMA_CFG_WR_BURST_512		0x00000100
220 #define	DMA_CFG_WR_BURST_1024		0x00000180
221 #define	DMA_CFG_WR_BURST_2048		0x00000200
222 #define	DMA_CFG_WR_BURST_4096		0x00000280
223 
224 /* L1E specific but can go into common regs */
225 #define	DMA_CFG_RXCMB_ENB		0x00200000
226 #define	DMA_CFG_RD_DELAY_CNT_DEFAULT	15
227 #define	DMA_CFG_RD_DELAY_CNT_SHIFT	11
228 #define	DMA_CFG_RD_DELAY_CNT_MASK	0x0000F800
229 #define	DMA_CFG_WR_DELAY_CNT_DEFAULT	4
230 #define	DMA_CFG_WR_DELAY_CNT_SHIFT	16
231 #define	DMA_CFG_WR_DELAY_CNT_MASK	0x000F0000
232 
233 /*
234  * Common PHY registers.
235  */
236 #define	ATGE_MDIO			0x1414
237 #define	MDIO_DATA_MASK			0x0000FFFF
238 #define	MDIO_REG_ADDR_MASK		0x001F0000
239 #define	MDIO_OP_READ			0x00200000
240 #define	MDIO_OP_WRITE			0x00000000
241 #define	MDIO_SUP_PREAMBLE		0x00400000
242 #define	MDIO_OP_EXECUTE			0x00800000
243 #define	MDIO_CLK_25_4			0x00000000
244 #define	MDIO_CLK_25_6			0x02000000
245 #define	MDIO_CLK_25_8			0x03000000
246 #define	MDIO_CLK_25_10			0x04000000
247 #define	MDIO_CLK_25_14			0x05000000
248 #define	MDIO_CLK_25_20			0x06000000
249 #define	MDIO_CLK_25_28			0x07000000
250 #define	MDIO_OP_BUSY			0x08000000
251 #define	MDIO_DATA_SHIFT			0
252 #define	MDIO_REG_ADDR_SHIFT		16
253 
254 #define	MDIO_REG_ADDR(x)	\
255 	(((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK)
256 
257 #define	ATGE_GPHY_CTRL			0x140C	/* 16-bits */
258 #define	GPHY_CTRL_RST			0x0000
259 #define	GPHY_CTRL_CLR			0x0001
260 #define	ATPHY_CDTC			0x16
261 #define	PHY_CDTC_ENB			0x0001
262 #define	PHY_CDTC_POFF			0x8
263 #define	ATPHY_CDTS			0x1C
264 
265 
266 #define	ATGE_PHY_ADDR			0
267 #define	ATGE_PHY_STATUS			0x1418
268 #define	PHY_TIMEOUT			1000
269 
270 #define	ATGE_DESC_TPD_CNT		0x155C
271 #define	DESC_TPD_CNT_MASK		0x00003FF
272 #define	DESC_TPD_CNT_SHIFT		0
273 
274 #define	ATGE_DMA_BLOCK			0x1534
275 #define	DMA_BLOCK_LOAD			0x00000001
276 
277 /* From Freebsd if_alcreg.h */
278 /* 0x0000 - 0x02FF : PCIe configuration space */
279 
280 #define	ATGE_PEX_UNC_ERR_SEV		0x10C
281 #define	PEX_UNC_ERR_SEV_TRN		0x00000001
282 #define	PEX_UNC_ERR_SEV_DLP		0x00000010
283 #define	PEX_UNC_ERR_SEV_PSN_TLP		0x00001000
284 #define	PEX_UNC_ERR_SEV_FCP		0x00002000
285 #define	PEX_UNC_ERR_SEV_CPL_TO		0x00004000
286 #define	PEX_UNC_ERR_SEV_CA		0x00008000
287 #define	PEX_UNC_ERR_SEV_UC		0x00010000
288 #define	PEX_UNC_ERR_SEV_ROV		0x00020000
289 #define	PEX_UNC_ERR_SEV_MLFP		0x00040000
290 #define	PEX_UNC_ERR_SEV_ECRC		0x00080000
291 #define	PEX_UNC_ERR_SEV_UR		0x00100000
292 
293 #define	ATGE_PCIE_PHYMISC		0x1000
294 #define	PCIE_PHYMISC_FORCE_RCV_DET	0x00000004
295 
296 #define	ATGE_PCIE_PHYMISC2		0x1004
297 #define	PCIE_PHYMISC2_SERDES_CDR_MASK	0x00030000
298 #define	PCIE_PHYMISC2_SERDES_TH_MASK	0x000C0000
299 #define	PCIE_PHYMISC2_SERDES_CDR_SHIFT	16
300 #define	PCIE_PHYMISC2_SERDES_TH_SHIFT	18
301 
302 #define	ATGE_LTSSM_ID_CFG		0x12FC
303 #define	LTSSM_ID_WRO_ENB		0x00001000
304 
305 #define	ATGE_SMB_STAT_TIMER		0x15C4
306 #define	SMB_STAT_TIMER_MASK		0x00FFFFFF
307 #define	SMB_STAT_TIMER_SHIFT		0
308 
309 #define	ATGE_CMB_TD_THRESH		0x15C8
310 #define	CMB_TD_THRESH_MASK		0x0000FFFF
311 #define	CMB_TD_THRESH_SHIFT		0
312 
313 #define	ATGE_CMB_TX_TIMER		0x15CC
314 #define	CMB_TX_TIMER_MASK		0x0000FFFF
315 #define	CMB_TX_TIMER_SHIFT		0
316 
317 #define	ATGE_MBOX_RD0_PROD_IDX		0x15E0
318 
319 #define	ATGE_MBOX_RD1_PROD_IDX		0x15E4
320 
321 #define	ATGE_MBOX_RD2_PROD_IDX		0x15E8
322 
323 #define	ATGE_MBOX_RD3_PROD_IDX		0x15EC
324 
325 #define	ATGE_MBOX_RD_PROD_MASK		0x0000FFFF
326 #define	MBOX_RD_PROD_SHIFT		0
327 
328 #define	ATGE_MBOX_TD_PROD_IDX		0x15F0
329 #define	MBOX_TD_PROD_HI_IDX_MASK	0x0000FFFF
330 #define	MBOX_TD_PROD_LO_IDX_MASK	0xFFFF0000
331 #define	MBOX_TD_PROD_HI_IDX_SHIFT	0
332 #define	MBOX_TD_PROD_LO_IDX_SHIFT	16
333 
334 #define	ATGE_MBOX_TD_CONS_IDX		0x15F4
335 #define	MBOX_TD_CONS_HI_IDX_MASK	0x0000FFFF
336 #define	MBOX_TD_CONS_LO_IDX_MASK	0xFFFF0000
337 #define	MBOX_TD_CONS_HI_IDX_SHIFT	0
338 #define	MBOX_TD_CONS_LO_IDX_SHIFT	16
339 
340 #define	ATGE_MBOX_RD01_CONS_IDX		0x15F8
341 #define	MBOX_RD0_CONS_IDX_MASK		0x0000FFFF
342 #define	MBOX_RD1_CONS_IDX_MASK		0xFFFF0000
343 #define	MBOX_RD0_CONS_IDX_SHIFT		0
344 #define	MBOX_RD1_CONS_IDX_SHIFT		16
345 
346 #define	ATGE_MBOX_RD23_CONS_IDX		0x15FC
347 #define	MBOX_RD2_CONS_IDX_MASK		0x0000FFFF
348 #define	MBOX_RD3_CONS_IDX_MASK		0xFFFF0000
349 #define	MBOX_RD2_CONS_IDX_SHIFT		0
350 #define	MBOX_RD3_CONS_IDX_SHIFT		16
351 
352 #define	ATGE_INTR_RETRIG_TIMER		0x1608
353 #define	INTR_RETRIG_TIMER_MASK		0x0000FFFF
354 #define	INTR_RETRIG_TIMER_SHIFT		0
355 
356 #define	ATGE_HDS_CFG			0x160C
357 #define	HDS_CFG_ENB			0x00000001
358 #define	HDS_CFG_BACKFILLSIZE_MASK	0x000FFF00
359 #define	HDS_CFG_MAX_HDRSIZE_MASK	0xFFF00000
360 #define	HDS_CFG_BACKFILLSIZE_SHIFT	8
361 #define	HDS_CFG_MAX_HDRSIZE_SHIFT	20
362 
363 /* AR813x/AR815x registers for MAC statistics */
364 #define	ATGE_RX_MIB_BASE		0x1700
365 
366 #define	ATGE_TX_MIB_BASE		0x1760
367 
368 #define	ATGE_CLK_GATING_CFG		0x1814
369 #define	CLK_GATING_DMAW_ENB		0x0001
370 #define	CLK_GATING_DMAR_ENB		0x0002
371 #define	CLK_GATING_TXQ_ENB		0x0004
372 #define	CLK_GATING_RXQ_ENB		0x0008
373 #define	CLK_GATING_TXMAC_ENB		0x0010
374 #define	CLK_GATING_RXMAC_ENB		0x0020
375 
376 #define	ATGE_DEBUG_DATA0		0x1900
377 
378 #define	ATGE_DEBUG_DATA1		0x1904
379 
380 #define	ATGE_MII_DBG_ADDR		0x1D
381 #define	ATGE_MII_DBG_DATA		0x1E
382 /* End Freebsd if_alcreg.h */
383 
384 #define	ATGE_MBOX			0x15F0
385 #define	MBOX_RD_PROD_IDX_MASK		0x000007FF
386 #define	MBOX_RRD_CONS_IDX_MASK		0x003FF800
387 #define	MBOX_TD_PROD_IDX_MASK		0xFFC00000
388 #define	MBOX_RD_PROD_IDX_SHIFT		0
389 #define	MBOX_RRD_CONS_IDX_SHIFT		11
390 #define	MBOX_TD_PROD_IDX_SHIFT		22
391 
392 
393 #define	ATGE_IPG_IFG_CFG		0x1484
394 #define	IPG_IFG_IPGT_MASK		0x0000007F
395 #define	IPG_IFG_MIFG_MASK		0x0000FF00
396 #define	IPG_IFG_IPG1_MASK		0x007F0000
397 #define	IPG_IFG_IPG2_MASK		0x7F000000
398 #define	IPG_IFG_IPGT_SHIFT		0
399 #define	IPG_IFG_IPGT_DEFAULT		0x60
400 #define	IPG_IFG_MIFG_SHIFT		8
401 #define	IPG_IFG_MIFG_DEFAULT		0x50
402 #define	IPG_IFG_IPG1_SHIFT		16
403 #define	IPG_IFG_IPG1_DEFAULT		0x40
404 #define	IPG_IFG_IPG2_SHIFT		24
405 #define	IPG_IFG_IPG2_DEFAULT		0x60
406 
407 /* half-duplex parameter configuration. */
408 #define	ATGE_HDPX_CFG			0x1498
409 #define	HDPX_CFG_LCOL_MASK		0x000003FF
410 #define	HDPX_CFG_RETRY_MASK		0x0000F000
411 #define	HDPX_CFG_EXC_DEF_EN		0x00010000
412 #define	HDPX_CFG_NO_BACK_C		0x00020000
413 #define	HDPX_CFG_NO_BACK_P		0x00040000
414 #define	HDPX_CFG_ABEBE			0x00080000
415 #define	HDPX_CFG_ABEBT_MASK		0x00F00000
416 #define	HDPX_CFG_JAMIPG_MASK		0x0F000000
417 #define	HDPX_CFG_LCOL_SHIFT		0
418 #define	HDPX_CFG_LCOL_DEFAULT		0x37
419 #define	HDPX_CFG_RETRY_SHIFT		12
420 #define	HDPX_CFG_RETRY_DEFAULT		0x0F
421 #define	HDPX_CFG_ABEBT_SHIFT		20
422 #define	HDPX_CFG_ABEBT_DEFAULT		0x0A
423 #define	HDPX_CFG_JAMIPG_SHIFT		24
424 #define	HDPX_CFG_JAMIPG_DEFAULT		0x07
425 
426 #define	ATGE_FRAME_SIZE			0x149C
427 
428 #define	ATGE_WOL_CFG			0x14A0
429 #define	WOL_CFG_PATTERN			0x00000001
430 #define	WOL_CFG_PATTERN_ENB		0x00000002
431 #define	WOL_CFG_MAGIC			0x00000004
432 #define	WOL_CFG_MAGIC_ENB		0x00000008
433 #define	WOL_CFG_LINK_CHG		0x00000010
434 #define	WOL_CFG_LINK_CHG_ENB		0x00000020
435 #define	WOL_CFG_PATTERN_DET		0x00000100
436 #define	WOL_CFG_MAGIC_DET		0x00000200
437 #define	WOL_CFG_LINK_CHG_DET		0x00000400
438 #define	WOL_CFG_CLK_SWITCH_ENB		0x00008000
439 #define	WOL_CFG_PATTERN0		0x00010000
440 #define	WOL_CFG_PATTERN1		0x00020000
441 #define	WOL_CFG_PATTERN2		0x00040000
442 #define	WOL_CFG_PATTERN3		0x00080000
443 #define	WOL_CFG_PATTERN4		0x00100000
444 #define	WOL_CFG_PATTERN5		0x00200000
445 #define	WOL_CFG_PATTERN6		0x00400000
446 
447 /* WOL pattern length. */
448 #define	ATGE_PATTERN_CFG0		0x14A4
449 #define	PATTERN_CFG_0_LEN_MASK		0x0000007F
450 #define	PATTERN_CFG_1_LEN_MASK		0x00007F00
451 #define	PATTERN_CFG_2_LEN_MASK		0x007F0000
452 #define	PATTERN_CFG_3_LEN_MASK		0x7F000000
453 
454 #define	ATGE_PATTERN_CFG1		0x14A8
455 #define	PATTERN_CFG_4_LEN_MASK		0x0000007F
456 #define	PATTERN_CFG_5_LEN_MASK		0x00007F00
457 #define	PATTERN_CFG_6_LEN_MASK		0x007F0000
458 
459 #define	ATGE_TICK_USECS			2
460 #define	ATGE_USECS(x)			((x) / ATGE_TICK_USECS)
461 
462 #define	ATGE_INTR_CLR_TIMER		0x140E	/* 16-bits */
463 #define	ATGE_IM_TIMER			0x1408
464 #define	ATGE_IM_TIMER2			0x140A
465 #define	ATGE_IM_TIMER_MIN		0
466 #define	ATGE_IM_TIMER_MAX		130000	/* 130 ms */
467 #define	ATGE_IM_TIMER_DEFAULT		100
468 #define	ATGE_IM_RX_TIMER_DEFAULT	1
469 #define	ATGE_IM_TX_TIMER_DEFAULT	1
470 #define	IM_TIMER_TX_SHIFT		0
471 #define	IM_TIMER_RX_SHIFT		16
472 
473 #define	ATGE_DESC_ADDR_HI		0x1540
474 #define	ATGE_DESC_RD_ADDR_LO		0x1544
475 #define	ATGE_DESC_RRD_ADDR_LO		0x1548
476 #define	ATGE_DESC_TPD_ADDR_LO		0x154C
477 #define	ATGE_DESC_CMB_ADDR_LO		0x1550
478 #define	ATGE_DESC_SMB_ADDR_LO		0x1554
479 #define	ATGE_DESC_RRD_RD_CNT		0x1558
480 
481 #define	ATGE_RXQ_JUMBO_CFG		0x15A4
482 #define	RXQ_JUMBO_CFG_SZ_THRESH_SHIFT	0
483 #define	RXQ_JUMBO_CFG_SZ_THRESH_MASK	0x000007FF
484 #define	RXQ_JUMBO_CFG_LKAH_DEFAULT	0x01
485 #define	RXQ_JUMBO_CFG_LKAH_SHIFT	11
486 #define	RXQ_JUMBO_CFG_LKAH_MASK		0x00007800
487 #define	RXQ_JUMBO_CFG_RRD_TIMER_SHIFT	16
488 #define	RXQ_JUMBO_CFG_RRD_TIMER_MASK	0xFFFF0000
489 
490 #define	ATGE_RXQ_FIFO_PAUSE_THRESH	0x15A8
491 #define	RXQ_FIFO_PAUSE_THRESH_LO_MASK	0x00000FFF
492 #define	RXQ_FIFO_PAUSE_THRESH_HI_MASK	0x0FFF000
493 #define	RXQ_FIFO_PAUSE_THRESH_LO_SHIFT	0
494 #define	RXQ_FIFO_PAUSE_THRESH_HI_SHIFT	16
495 
496 /*
497  * RXQ CFG register.
498  */
499 #define	ATGE_RXQ_CFG			0x15A0
500 #define	RXQ_CFG_ALIGN_32		0x00000000
501 #define	RXQ_CFG_ALIGN_64		0x00000001
502 #define	RXQ_CFG_ALIGN_128		0x00000002
503 #define	RXQ_CFG_ALIGN_256		0x00000003
504 #define	RXQ_CFG_QUEUE1_ENB		0x00000010
505 #define	RXQ_CFG_QUEUE2_ENB		0x00000020
506 #define	RXQ_CFG_QUEUE3_ENB		0x00000040
507 #define	RXQ_CFG_IPV6_CSUM_VERIFY	0x00000080
508 #define	RXQ_CFG_RSS_HASH_TBL_LEN_MASK	0x0000FF00
509 #define	RXQ_CFG_RSS_HASH_IPV4		0x00010000
510 #define	RXQ_CFG_RSS_HASH_IPV4_TCP	0x00020000
511 #define	RXQ_CFG_RSS_HASH_IPV6		0x00040000
512 #define	RXQ_CFG_RSS_HASH_IPV6_TCP	0x00080000
513 #define	RXQ_CFG_RSS_MODE_DIS		0x00000000
514 #define	RXQ_CFG_RSS_MODE_SQSINT		0x04000000
515 #define	RXQ_CFG_RSS_MODE_MQUESINT	0x08000000
516 #define	RXQ_CFG_RSS_MODE_MQUEMINT	0x0C000000
517 #define	RXQ_CFG_NIP_QUEUE_SEL_TBL	0x10000000
518 #define	RXQ_CFG_RSS_HASH_ENB		0x20000000
519 #define	RXQ_CFG_CUT_THROUGH_ENB		0x40000000
520 #define	RXQ_CFG_ENB			0x80000000
521 #define	RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT	8
522 
523 /* 64bit multicast hash register. */
524 #define	ATGE_MAR0			0x1490
525 #define	ATGE_MAR1			0x1494
526 
527 #define	ATPHY_DBG_ADDR			0x1D
528 #define	ATPHY_DBG_DATA			0x1E
529 
530 /* From Freebsd if_alcreg.h */
531 #define	MII_ANA_CFG0			0x00
532 #define	ANA_RESTART_CAL			0x0001
533 #define	ANA_MANUL_SWICH_ON_MASK		0x001E
534 #define	ANA_MAN_ENABLE			0x0020
535 #define	ANA_SEL_HSP			0x0040
536 #define	ANA_EN_HB			0x0080
537 #define	ANA_EN_HBIAS			0x0100
538 #define	ANA_OEN_125M			0x0200
539 #define	ANA_EN_LCKDT			0x0400
540 #define	ANA_LCKDT_PHY			0x0800
541 #define	ANA_AFE_MODE			0x1000
542 #define	ANA_VCO_SLOW			0x2000
543 #define	ANA_VCO_FAST			0x4000
544 #define	ANA_SEL_CLK125M_DSP		0x8000
545 #define	ANA_MANUL_SWICH_ON_SHIFT	1
546 
547 #define	MII_ANA_CFG4			0x04
548 #define	ANA_IECHO_ADJ_MASK		0x0F
549 #define	ANA_IECHO_ADJ_3_MASK		0x000F
550 #define	ANA_IECHO_ADJ_2_MASK		0x00F0
551 #define	ANA_IECHO_ADJ_1_MASK		0x0F00
552 #define	ANA_IECHO_ADJ_0_MASK		0xF000
553 #define	ANA_IECHO_ADJ_3_SHIFT		0
554 #define	ANA_IECHO_ADJ_2_SHIFT		4
555 #define	ANA_IECHO_ADJ_1_SHIFT		8
556 #define	ANA_IECHO_ADJ_0_SHIFT		12
557 
558 #define	MII_ANA_CFG5			0x05
559 #define	ANA_SERDES_CDR_BW_MASK		0x0003
560 #define	ANA_MS_PAD_DBG			0x0004
561 #define	ANA_SPEEDUP_DBG			0x0008
562 #define	ANA_SERDES_TH_LOS_MASK		0x0030
563 #define	ANA_SERDES_EN_DEEM		0x0040
564 #define	ANA_SERDES_TXELECIDLE		0x0080
565 #define	ANA_SERDES_BEACON		0x0100
566 #define	ANA_SERDES_HALFTXDR		0x0200
567 #define	ANA_SERDES_SEL_HSP		0x0400
568 #define	ANA_SERDES_EN_PLL		0x0800
569 #define	ANA_SERDES_EN			0x1000
570 #define	ANA_SERDES_EN_LCKDT		0x2000
571 #define	ANA_SERDES_CDR_BW_SHIFT		0
572 #define	ANA_SERDES_TH_LOS_SHIFT		4
573 
574 #define	MII_ANA_CFG11			0x0B
575 #define	ANA_PS_HIB_EN			0x8000
576 
577 #define	MII_ANA_CFG18			0x12
578 #define	ANA_TEST_MODE_10BT_01MASK	0x0003
579 #define	ANA_LOOP_SEL_10BT		0x0004
580 #define	ANA_RGMII_MODE_SW		0x0008
581 #define	ANA_EN_LONGECABLE		0x0010
582 #define	ANA_TEST_MODE_10BT_2		0x0020
583 #define	ANA_EN_10BT_IDLE		0x0400
584 #define	ANA_EN_MASK_TB			0x0800
585 #define	ANA_TRIGGER_SEL_TIMER_MASK	0x3000
586 #define	ANA_INTERVAL_SEL_TIMER_MASK	0xC000
587 #define	ANA_TEST_MODE_10BT_01SHIFT	0
588 #define	ANA_TRIGGER_SEL_TIMER_SHIFT	12
589 #define	ANA_INTERVAL_SEL_TIMER_SHIFT	14
590 
591 #define	MII_ANA_CFG41			0x29
592 #define	ANA_TOP_PS_EN			0x8000
593 
594 #define	MII_ANA_CFG54			0x36
595 #define	ANA_LONG_CABLE_TH_100_MASK	0x003F
596 #define	ANA_DESERVED			0x0040
597 #define	ANA_EN_LIT_CH			0x0080
598 #define	ANA_SHORT_CABLE_TH_100_MASK	0x3F00
599 #define	ANA_BP_BAD_LINK_ACCUM		0x4000
600 #define	ANA_BP_SMALL_BW			0x8000
601 #define	ANA_LONG_CABLE_TH_100_SHIFT	0
602 #define	ANA_SHORT_CABLE_TH_100_SHIFT	8
603 /* End Freebsd if_alcreg.h */
604 
605 #define	ATGE_TD_EOP			0x00000001
606 #define	ATGE_TD_BUFLEN_MASK		0x00003FFF
607 #define	ATGE_TD_BUFLEN_SHIFT		0
608 #define	ATGE_TX_BYTES(x)	\
609 	(((x) << ATGE_TD_BUFLEN_SHIFT) & ATGE_TD_BUFLEN_MASK)
610 
611 #define	ATGE_ISR_ACK_GPHY		19
612 
613 #ifdef __cplusplus
614 }
615 #endif
616 
617 #endif	/* _ATGE_CMN_REG_H */
618