xref: /illumos-gate/usr/src/uts/sun4u/sys/cheetahregs.h (revision 7bebe46c240b554f47faeed19186123896281967)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_CHEETAHREGS_H
27 #define	_SYS_CHEETAHREGS_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #include <sys/machasi.h>
32 #include <sys/cpu_impl.h>
33 #ifdef _KERNEL
34 #include <sys/fpras.h>
35 #endif /* _KERNEL */
36 
37 /*
38  * This file is cpu dependent.
39  */
40 
41 #ifdef	__cplusplus
42 extern "C" {
43 #endif
44 
45 /*
46  * Cheetah includes the process info in its mask to make things
47  * more difficult.  The process is the low bit of the major mask,
48  * so to convert to the netlist major:
49  * netlist_major = ((mask_major >> 1) + 1)
50  */
51 #define	REMAP_CHEETAH_MASK(x)	(((((x) >> 1) + 0x10) & 0xf0) | ((x) & 0xf))
52 
53 #ifdef _ASM
54 /*
55  * assembler doesn't understand the 'ull' suffix for C constants so
56  * use the inttypes.h macros and undefine them here for assembly code
57  */
58 #undef INT64_C
59 #undef UINT64_C
60 #define	INT64_C(x)	(x)
61 #define	UINT64_C(x)	(x)
62 #endif	/* _ASM */
63 
64 /*
65  * DCU Control Register
66  *
67  * +------+----+----+----+----+----+-----+-----+----+----+----+
68  * | Resv | CP | CV | ME | RE | PE | HPE | SPE | SL | WE | PM |
69  * +------+----+----+----+----+----+-----+-----+----+----+----+
70  *  63:50   49   48   47   46	45    44    43   42   41 40:33
71  *
72  * +----+----+----+----+----+----------+-----+----+----+----+---+
73  * | VM | PR | PW | VR | VW | Reserved | WIH | DM | IM | DC | IC|
74  * +----+----+----+----+----+----------+-----+----+----+----+---+
75  * 32:25  24   23   22   21      20:5     4     3    2    1   0
76  */
77 
78 #define	ASI_DCU	ASI_LSU			    /* same as spitfire ASI_LSU 0x45 */
79 #define	DCU_IC	INT64_C(0x0000000000000001) /* icache enable		*/
80 #define	DCU_DC	INT64_C(0x0000000000000002) /* dcache enable		*/
81 #define	DCU_IM	INT64_C(0x0000000000000004) /* immu enable		*/
82 #define	DCU_DM	INT64_C(0x0000000000000008) /* dmmu enable		*/
83 #define	DCU_WIH	INT64_C(0x0000000000000010) /* Jaguar only - W$ hash index */
84 #define	DCU_VW	INT64_C(0x0000000000200000) /* virt watchpoint write enable  */
85 #define	DCU_VR	INT64_C(0x0000000000400000) /* virt watchpoint read enable   */
86 #define	DCU_PW	INT64_C(0x0000000000800000) /* phys watchpoint write enable  */
87 #define	DCU_PR	INT64_C(0x0000000001000000) /* phys watchpoint read enable   */
88 #define	DCU_VM	INT64_C(0x00000001FE000000) /* virtual watchpoint write mask */
89 #define	DCU_PM	INT64_C(0x000001FE00000000) /* phys watchpoint write mask    */
90 #define	DCU_WE	INT64_C(0x0000020000000000) /* write cache enable	*/
91 #define	DCU_SL	INT64_C(0x0000040000000000) /* second load control	*/
92 #define	DCU_SPE	INT64_C(0x0000080000000000) /* software prefetch enable */
93 #define	DCU_HPE	INT64_C(0x0000100000000000) /* hardware prefetch enable */
94 #define	DCU_PE	INT64_C(0x0000200000000000) /* prefetch enable		*/
95 #define	DCU_RE	INT64_C(0x0000400000000000) /* RAW bypass enable	*/
96 #define	DCU_ME	INT64_C(0x0000800000000000) /* noncache store merging enable */
97 #define	DCU_CV	INT64_C(0x0001000000000000) /* virt cacheability when DM=0   */
98 #define	DCU_CP	INT64_C(0x0002000000000000) /* phys cacheable when DM,IM=0   */
99 #define	DCU_CACHE (DCU_IC|DCU_DC|DCU_WE|DCU_SPE|DCU_HPE|DCU_PE)
100 #define	DCU_IPS_MASK	INT64_C(0x0030000000000000)
101 
102 /*
103  * bit shifts for the prefetch enable bit
104  */
105 #define	DCU_PE_SHIFT	45
106 
107 /*
108  * Safari Configuration Register
109  */
110 #define	ASI_SAFARI_CONFIG	ASI_UPA_CONFIG /* Safari Config Reg, 0x4A */
111 #define	SAFARI_CONFIG_ECLK_1	INT64_C(0x0000000000000000) /* 1/1 clock */
112 #define	SAFARI_CONFIG_ECLK_1_DIV	1	/* clock divisor: 1 */
113 #define	SAFARI_CONFIG_ECLK_2	INT64_C(0x0000000040000000) /* 1/2 clock */
114 #define	SAFARI_CONFIG_ECLK_2_DIV	2	/* clock divisor: 2 */
115 #define	SAFARI_CONFIG_ECLK_32	INT64_C(0x0000000080000000) /* 1/32 clock */
116 #define	SAFARI_CONFIG_ECLK_32_DIV	32	/* clock divisor: 32 */
117 #define	SAFARI_CONFIG_ECLK_MASK	(SAFARI_CONFIG_ECLK_32 | SAFARI_CONFIG_ECLK_2)
118 
119 #if defined(JALAPENO) || defined(SERRANO)
120 /*
121  * JBUS Configuration Register
122  */
123 #define	ASI_JBUS_CONFIG		ASI_UPA_CONFIG /* JBUS Config Reg, 0x4A */
124 #define	JBUS_CONFIG_ECLK_1	INT64_C(0x0000000000000000) /* 1/1 clock */
125 #define	JBUS_CONFIG_ECLK_1_DIV	1	/* clock divisor: 1 */
126 #define	JBUS_CONFIG_ECLK_2	INT64_C(0x0000000000002000) /* 1/2 clock */
127 #define	JBUS_CONFIG_ECLK_2_DIV	2	/* clock divisor: 2 */
128 #define	JBUS_CONFIG_ECLK_32	INT64_C(0x0000000000004000) /* 1/32 clock */
129 #define	JBUS_CONFIG_ECLK_32_DIV	32	/* clock divisor: 32 */
130 #define	JBUS_CONFIG_ECLK_MASK	(JBUS_CONFIG_ECLK_32 | JBUS_CONFIG_ECLK_2)
131 #define	JBUS_CONFIG_ECLK_SHIFT	13
132 
133 /*
134  * Jalapeno/Serrano MCU control registers and ASI
135  */
136 #define	ASI_MCU_CTRL		0x72		/* MCU Control Reg ASI */
137 #define	JP_MCU_FSM_MASK		INT64_C(0x0000000006000000) /* 26..25 */
138 #define	JP_MCU_FSM_SHIFT	25
139 #endif /* JALAPENO || SERRANO */
140 
141 #if defined(SERRANO)
142 #define	ASI_MCU_AFAR2_VA	0x18	/* captures FRC/FRU addr */
143 #endif	/* SERRANO */
144 
145 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
146 /*
147  * Tomatillo Estar control registers (for JP Errataum 85)
148  */
149 #define	JBUS_SLAVE_T_PORT_BIT	48
150 #define	TOM_HIGH_PA		0x400		/* Hi 32 bit of Tom reg PA */
151 #define	M_T_ESTAR_CTRL_PA	0x0f410050	/* M T estar PA */
152 #define	S_T_ESTAR_CTRL_PA	0x0e410050	/* S T estar PA */
153 #define	M_T_J_CHNG_INIT_PA	0x0f410058	/* Master T estar PA */
154 #define	TOM_ESTAR_ELCK_MASK	0x23		/* bit 5,1,0 */
155 #define	TOM_FULL_SPEED		0x1
156 #define	TOM_HALF_SPEED		0x2
157 #define	TOM_SLOW_SPEED		0x20
158 #define	TOM_TRIGGER_MASK	0x18
159 #define	TOM_TRIGGER		0x10
160 
161 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
162 
163 
164 /*
165  * Miscellaneous ASI definitions not in machasi.h
166  */
167 #define	ASI_DC_UTAG		0x43	/* Dcache Microtag Fields */
168 #define	ASI_DC_SNP_TAG		0x44	/* Dcache Snoop Tag Fields */
169 #define	ASI_IC_SNP_TAG		0x68	/* Icache Snoop Tag Fields */
170 #define	ASI_IPB_DATA		0x69	/* Instruction Prefetch Buffer Data */
171 #define	ASI_IPB_TAG		0x6A	/* Instruction Prefetch Buffer Tag */
172 #define	ASI_MC_DECODE		0x72	/* Memory Address Decoding Registers */
173 #define	ASI_EC_CFG_TIMING	0x73	/* Jaguar shared Ecache Control Reg */
174 #define	ASI_EC_DATA		0x74	/* Ecache Data Staging Registers */
175 #define	ASI_EC_CTRL		0x75	/* Ecache Control Register */
176 #define	ASI_PC_STATUS_DATA	0x30	/* Pcache Status Data Access */
177 #define	ASI_PC_DATA		0x31	/* Pcache Diagnostic Data Register */
178 #define	ASI_PC_TAG		0x32	/* Pcache Virtual Tag/Valid Field */
179 #define	ASI_PC_SNP_TAG		0x33	/* Pcache Snoop Tag Register */
180 #define	ASI_L2_DATA		0x6B	/* L2 cache Data Diagnostic Access */
181 #define	ASI_L2_TAG		0x6C	/* L2 cache Tag Diagnostic Access */
182 #define	ASI_L2CACHE_CTRL	0x6D	/* L2 cache Control Register */
183 
184 /*
185  * Bits of Cheetah Asynchronous Fault Status Register
186  *
187  * +---+--+----+----+----+----+---+---+---+---+--+----
188  * |rsv|ME|PRIV|PERR|IERR|ISAP|EMC|EMU|IVC|IVU|TO|BERR
189  * +---+--+----+----+----+----+---+---+---+---+--+----
190  * 63:54 53 52   51   50   49   48  47  46  45 44  43
191  * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+
192  * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|rsv|M_SYND|rsv||E_SYND|
193  * +---+---+---+---+---+---+---+---+--+--+---+------+---+-------+
194  *   42  41  40  39  38  37  36  35 34 33 32:20 19:16 15:9 8:0
195  *
196  */
197 #if defined(CHEETAH_PLUS)
198 /*
199  * Bits of Cheetah+ Asynchronous Fault Status Register
200  *
201  * +------------------+----------------------------
202  * |rsv|TUE_SH|IMC|IMU|DTO|DBERR|THCE|TSCE|TUE|DUE|
203  * +------------------+---------------------------- . . .
204  *   63    62   61  60  59    58   57   56  55  54
205  *
206  * Note that bits 60-62 are only implemented in Panther (reserved
207  * in Cheetah+ and Jaguar. Also, bit 56 is reserved in Panther instead
208  * of TSCE since those errors are HW corrected in Panther.
209  */
210 #define	C_AFSR_TUE_SH INT64_C(0x4000000000000000) /* uncorrectable tag UE  */
211 #define	C_AFSR_IMC  INT64_C(0x2000000000000000)	/* intr vector MTAG ECC */
212 #define	C_AFSR_IMU  INT64_C(0x1000000000000000)	/* intr vector MTAG ECC */
213 #define	C_AFSR_DTO  INT64_C(0x0800000000000000)	/* disrupting TO error */
214 #define	C_AFSR_DBERR INT64_C(0x0400000000000000) /* disrupting BERR error */
215 #define	C_AFSR_THCE INT64_C(0x0200000000000000)	/* h/w correctable E$ tag err */
216 #define	C_AFSR_TSCE INT64_C(0x0100000000000000)	/* s/w correctable E$ tag err */
217 #define	C_AFSR_TUE  INT64_C(0x0080000000000000)	/* uncorrectable E$ tag error */
218 #define	C_AFSR_DUE  INT64_C(0x0040000000000000)	/* disrupting UE error */
219 #endif	/* CHEETAH_PLUS */
220 #define	C_AFSR_ME   INT64_C(0x0020000000000000)	/* errors > 1, same type!=CE */
221 #define	C_AFSR_PRIV INT64_C(0x0010000000000000)	/* priv code access error    */
222 #define	C_AFSR_PERR INT64_C(0x0008000000000000)	/* system interface protocol */
223 #define	C_AFSR_IERR INT64_C(0x0004000000000000)	/* internal system interface */
224 #define	C_AFSR_ISAP INT64_C(0x0002000000000000)	/* system request parity err */
225 #define	C_AFSR_EMC  INT64_C(0x0001000000000000)	/* mtag   with   CE   error  */
226 #define	C_AFSR_EMU  INT64_C(0x0000800000000000)	/* mtag   with   UE   error  */
227 #define	C_AFSR_IVC  INT64_C(0x0000400000000000)	/* intr vector with CE error */
228 #define	C_AFSR_IVU  INT64_C(0x0000200000000000)	/* intr vector with UE error */
229 #define	C_AFSR_TO   INT64_C(0x0000100000000000)	/* bus timeout from sys bus  */
230 #define	C_AFSR_BERR INT64_C(0x0000080000000000)	/* bus error from system bus */
231 #define	C_AFSR_UCC  INT64_C(0x0000040000000000)	/* E$ with software CE error */
232 #define	C_AFSR_UCU  INT64_C(0x0000020000000000)	/* E$ with software UE error */
233 #define	C_AFSR_CPC  INT64_C(0x0000010000000000) /* copyout  with  CE  error  */
234 #define	C_AFSR_CPU  INT64_C(0x0000008000000000) /* copyout  with  UE  error  */
235 #define	C_AFSR_WDC  INT64_C(0x0000004000000000) /* writeback ecache CE error */
236 #define	C_AFSR_WDU  INT64_C(0x0000002000000000) /* writeback ecache UE error */
237 #define	C_AFSR_EDC  INT64_C(0x0000001000000000) /* ecache  CE  ECC  error    */
238 #define	C_AFSR_EDU  INT64_C(0x0000000800000000) /* ecache  UE  ECC  error    */
239 #define	C_AFSR_UE   INT64_C(0x0000000400000000) /* uncorrectable ECC error   */
240 #define	C_AFSR_CE   INT64_C(0x0000000200000000) /* correctable   ECC error   */
241 #define	C_AFSR_M_SYND	INT64_C(0x00000000000f0000) /* mtag  ECC  syndrome   */
242 #define	C_AFSR_E_SYND	INT64_C(0x00000000000001ff) /* data  ECC  syndrome   */
243 
244 /* AFSR bits that could result in CPU removal due to E$ error */
245 #define	C_AFSR_L2_SERD_FAIL_UE	(C_AFSR_UCU | C_AFSR_CPU | C_AFSR_WDU | \
246 				C_AFSR_EDU)
247 #define	C_AFSR_L2_SERD_FAIL_CE	(C_AFSR_UCC | C_AFSR_CPC | C_AFSR_WDC | \
248 				C_AFSR_EDC)
249 /*
250  * Bits of the Panther Extended Asynchronous Fault Status Register (AFSR_EXT)
251  *
252  * +-----+-------+-----------+-------+-------+---------+------+------+------+
253  * | rsv |RED_ERR|EFA_PAR_ERR|L3_MECC|L3_THCE|L3_TUE_SH|L3_TUE|L3_EDC|L3_EDU|
254  * +-----+-------+-----------+-------+-------+---------+------+------+------+
255  *  63:14   13        12        11       10       9        8      7      6
256  *
257  * +------+------+------+------+------+------+
258  * |L3_UCC|L3_UCU|L3_CPC|L3_CPU|L3_WDC|L3_WDU|
259  * +------+------+------+------+------+------+
260  *     5      4      3      2      1      0
261  *
262  * If the L3_MECC bit is set along with any of the L3 cache errors (bits 0-7)
263  * above, it indicates that an address parity error has occured.
264  */
265 #define	C_AFSR_RED_ERR   INT64_C(0x0000000000002000) /* redunancy Efuse error */
266 #define	C_AFSR_EFA_PAR_ERR INT64_C(0x0000000000001000) /* Efuse parity error */
267 #define	C_AFSR_L3_MECC   INT64_C(0x0000000000000800) /* L3 address parity */
268 #define	C_AFSR_L3_THCE   INT64_C(0x0000000000000400) /* tag CE */
269 #define	C_AFSR_L3_TUE_SH INT64_C(0x0000000000000200) /* tag UE from snp/cpy */
270 #define	C_AFSR_L3_TUE    INT64_C(0x0000000000000100) /* tag UE */
271 #define	C_AFSR_L3_EDC    INT64_C(0x0000000000000080) /* L3 cache CE */
272 #define	C_AFSR_L3_EDU    INT64_C(0x0000000000000040) /* L3 cache UE */
273 #define	C_AFSR_L3_UCC    INT64_C(0x0000000000000020) /* software recover CE */
274 #define	C_AFSR_L3_UCU    INT64_C(0x0000000000000010) /* software recover UE */
275 #define	C_AFSR_L3_CPC    INT64_C(0x0000000000000008) /* copyout with CE */
276 #define	C_AFSR_L3_CPU    INT64_C(0x0000000000000004) /* copyout with UE */
277 #define	C_AFSR_L3_WDC    INT64_C(0x0000000000000002) /* writeback CE */
278 #define	C_AFSR_L3_WDU    INT64_C(0x0000000000000001) /* writeback UE */
279 
280 #if defined(JALAPENO) || defined(SERRANO)
281 /*
282  * Bits of Jalapeno Asynchronous Fault Status Register
283  *
284  * +-----+------------------------------------------------------------------
285  * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETP|OM|UMS|IVPE|TO|BERR|
286  * +-----+------------------------------------------------------------------
287  * 63:58   57   56   55  54  53  52   51   50   49  48  47  46  45  44  43
288  *
289  * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
290  * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU|
291  * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
292  *   42  41  40  39  38  37  36  35 34 33 32  31  30 29  28  27
293  *
294  * +-----+-----+-----+------+-----------+-------+
295  * | JREQ| ETW | rsv |B_SYND| rsv | AID | E_SYND|
296  * +-----+-----+-----+------+-----+-----+-------+
297  *  26:24 23:22 21:20  19:16 15:14 13:9   8:0
298  *
299  */
300 
301 /*
302  * Bits of Serrano Asynchronous Fault Status Register
303  *
304  * +-----+------------------------------------------------------------------
305  * | rsv |JETO|SCE|JEIC|JEIT|ME|PRIV|JEIS|IERR|ISAP|ETU|OM|UMS|IVPE|TO|BERR|
306  * +-----+------------------------------------------------------------------
307  * 63:58   57   56   55  54  53  52   51   50   49  48  47  46  45  44  43
308  *
309  * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
310  * |UCC|UCU|CPC|CPU|WDC|WDU|EDC|EDU|UE|CE|RUE|RCE|BP|WBP|FRC|FRU|
311  * +---+---+---+---+---+---+---+---+--+--+---+---+--+---+-------+
312  *   42  41  40  39  38  37  36  35 34 33 32  31  30 29  28  27
313  *
314  * +-----+-----+------+---+------+---+---+-----+-------+
315  * | JREQ| ETW | EFES |ETS|B_SYND|ETI|ETC| AID | E_SYND|
316  * +-----+-----+------+---+------+---+---+-----+-------+
317  *  26:24 23:22    21   20  19:16  15  14  13:9    8:0
318  *
319  */
320 
321 #define	C_AFSR_JETO	INT64_C(0x0200000000000000) /* JBus Timeout */
322 #define	C_AFSR_SCE	INT64_C(0x0100000000000000) /* Snoop parity error */
323 #define	C_AFSR_JEIC	INT64_C(0x0080000000000000) /* JBus Illegal Cmd */
324 #define	C_AFSR_JEIT	INT64_C(0x0040000000000000) /* Illegal ADTYPE */
325 #define	C_AFSR_JEIS	INT64_C(0x0008000000000000) /* Illegal Install State */
326 #if defined(SERRANO)
327 #define	C_AFSR_ETU	INT64_C(0x0001000000000000) /* L2$ tag CE error */
328 #elif defined(JALAPENO)
329 #define	C_AFSR_ETP	INT64_C(0x0001000000000000) /* L2$ tag parity error */
330 #endif /* JALAPENO */
331 #define	C_AFSR_OM	INT64_C(0x0000800000000000) /* out of range mem error */
332 #define	C_AFSR_UMS	INT64_C(0x0000400000000000) /* Unsupported store */
333 #define	C_AFSR_IVPE	INT64_C(0x0000200000000000) /* intr vector parity err */
334 #define	C_AFSR_RUE	INT64_C(0x0000000100000000) /* remote mem UE error */
335 #define	C_AFSR_RCE	INT64_C(0x0000000080000000) /* remote mem CE error */
336 #define	C_AFSR_BP	INT64_C(0x0000000040000000) /* read data parity err */
337 #define	C_AFSR_WBP	INT64_C(0x0000000020000000) /* wb/bs data parity err */
338 #define	C_AFSR_FRC	INT64_C(0x0000000010000000) /* foregin mem CE error */
339 #define	C_AFSR_FRU	INT64_C(0x0000000008000000) /* foregin mem UE error */
340 #define	C_AFSR_JREQ	INT64_C(0x0000000007000000) /* Active JBus req at err */
341 #define	C_AFSR_ETW	INT64_C(0x0000000000c00000) /* AID causing UE/CE */
342 
343 #if defined(SERRANO)
344 #define	C_AFSR_EFES	INT64_C(0x0000000000200000) /* E-fuse error summary */
345 #define	C_AFSR_ETS	INT64_C(0x0000000000100000) /* L2$ tag SRAM stuck-at */
346 #endif /* SERRANO */
347 
348 #define	C_AFSR_B_SYND	INT64_C(0x00000000000f0000) /* jbus parity syndrome */
349 
350 #if defined(SERRANO)
351 #define	C_AFSR_ETI	INT64_C(0x0000000000008000) /* L2$ tag intermittent */
352 #define	C_AFSR_ETC	INT64_C(0x0000000000004000) /* L2$ tag CE */
353 #endif /* SERRANO */
354 
355 #define	C_AFSR_AID	INT64_C(0x0000000000003e00) /* AID causing UE/CE */
356 
357 /* bit shifts for selected errors */
358 #define	C_AFSR_WDU_SHIFT	37
359 #define	C_AFSR_UCU_SHIFT	41
360 #define	C_AFSR_UCC_SHIFT	42
361 #define	C_AFSR_JREQ_SHIFT	24
362 #define	C_AFSR_AID_SHIFT	9
363 
364 /*
365  * Overloaded AFSR fields. During error processing, some of the reserved
366  * fields within the saved AFSR are overwritten with extra information.
367  */
368 #define	C_AFSR_PANIC_SHIFT		62
369 #define	C_AFSR_IPE_SHIFT		59
370 #define	C_AFSR_DPE_SHIFT		58
371 
372 #else /* JALAPENO || SERRANO */
373 
374 /* bit shifts for selected errors */
375 #define	C_AFSR_WDU_SHIFT	37
376 #define	C_AFSR_UCU_SHIFT	41
377 #define	C_AFSR_UCC_SHIFT	42
378 #define	C_AFSR_L3_UCU_SHIFT	4
379 
380 /*
381  * Overloaded AFSR fields. During error processing, some of the reserved fields
382  * within the saved AFSR are overwritten with extra information.
383  */
384 #define	C_AFSR_FIRSTFLT_SHIFT	63
385 #define	C_AFSR_PANIC_SHIFT	30
386 #define	C_AFSR_DPE_SHIFT	20
387 #define	C_AFSR_IPE_SHIFT	21
388 
389 #endif /* JALAPENO || SERRANO */
390 
391 #if defined(JALAPENO) || defined(SERRANO)
392 /*
393  * Jalapeno L2 Cache Control Register Bits.
394  *
395  *	Bit#	Name		Description
396  *	63-24	-		reserved
397  *	23:20	EC_ACT_WAY	(read only) indicates which sets are present
398  *	19:16	EC_BLK_WAY	Bit mask indicating which sets are blocked
399  *				from replacement
400  *	15:14	EC_SIZE		L2 cache size
401  *	13:12	-		reserved
402  *	11	EC_PAR_EN	Enables parity checking on L2 cache tags
403  *	10	EC_ECC_EN	Enables ECC checking on L2 cache data
404  *	9	EC_ECC_FORCE	Enables EC_CHECK[8:0] onto L2 cache ECC bits
405  *	8:0	EC_CHECK	ECC check vector to force onto ECC bits
406  */
407 
408 #define	JP_ECCTRL_ECSIZE_MASK		0xc000
409 #define	JP_ECCTRL_ECSIZE_SHIFT		14
410 #define	JP_ECCTRL_ECSIZE_MIN		0x80000
411 
412 /*
413  * Jalapeno L2 Cache Error Enable Register Bits
414  *
415  *	Bit#	Name	Description
416  *	63-33	-	reserved
417  *	32	SCDE	Enable detection of JBUS control parity error
418  *	31:24	-	reserved
419  *	23	IAEN	Enable trap on illegal physical address
420  *	22	IERREN	Enable FERR system reset on CPU internal errors
421  *	21	PERREN	Enable FERR system reset on JBUS protocol errors
422  *	20	SCEN	Enable FERR system reset on JBUS control parity error
423  *	19:11	FMED	Forced error on the memory ECC
424  *	10	FME	Force error on memory ECC
425  *	9:6	FPD	Bits to use when FSP forces JBUS addr/data parity error
426  *	5	FSP	Force error on outgoing JBUS addr/data parity
427  *	4	ETPEN	Enable FERR system reset on L2 tags parity error
428  *	3	UCEEN	Enable trap on SW handled external cache error
429  *	2	ISAPEN	Enable FERR system reset on request parity error
430  *	1	NCEEN	Enable trap on uncorrectable ECC error and system err
431  *	0	CEEN	Enable trap on correctable ECC errors
432  */
433 
434 #define	EN_REG_UCEEN	INT64_C(0x0000000000000008) /* enable UCC,UCU */
435 #define	EN_REG_ISAPEN	INT64_C(0x0000000000000004) /* enable ISAP */
436 #define	EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */
437 #define	EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */
438 
439 #define	EN_REG_DISABLE	INT64_C(0x0000000000000000) /* no errors enabled */
440 #define	EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN)
441 #define	EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN)
442 #define	EN_REG_ENABLE \
443 	(EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN)
444 
445 #else /* JALAPENO || SERRANO */
446 #if defined(CHEETAH_PLUS)
447 /*
448  * Cheetah+ External Cache Control Register Bits.
449  */
450 #define	ECCR_ASSOC	INT64_C(0x0000000001000000) /* Ecache Assoc. */
451 #define	ECCR_ASSOC_SHIFT	24
452 #endif	/* CHEETAH_PLUS */
453 
454 /*
455  * Bits of Cheetah External Cache Error Enable Register
456  *
457  * +-----+-----+-------+-----+-------+-------+--------+-------+------+
458  * | rsv | FMT | FMECC | FMD | FDECC | UCEEN | ISAPEN | NCEEN | CEEN |
459  * +-----+-----+-------+-----+-------+-------+--------+-------+------+
460  *  63:19   18  17  14    13    12:4     3        2       1       0
461  *
462  */
463 #define	EN_REG_FMT	INT64_C(0x0000000000040000) /* force system mtag ECC */
464 #define	EN_REG_FMECC	INT64_C(0x000000000003C000) /* forced mtag ECC vector */
465 #define	EN_REG_FMD	INT64_C(0x0000000000002000) /* force system data ECC */
466 #define	EN_REG_FDECC	INT64_C(0x0000000000001ff0) /* forced data ECC vector */
467 #define	EN_REG_UCEEN	INT64_C(0x0000000000000008) /* enable UCC,UCU */
468 #define	EN_REG_ISAPEN	INT64_C(0x0000000000000004) /* enable ISAP */
469 #define	EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */
470 #define	EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */
471 #define	EN_REG_DISABLE	INT64_C(0x0000000000000000) /* no errors enabled */
472 #define	EN_REG_ECC_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN)
473 #define	EN_REG_CE_DISABLE (EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN)
474 #define	EN_REG_ENABLE \
475 	(EN_REG_UCEEN | EN_REG_ISAPEN | EN_REG_NCEEN | EN_REG_CEEN)
476 #endif	/* JALAPENO || SERRANO */
477 
478 /*
479  * bit shifts for selected bits
480  */
481 #define	EN_REG_CEEN_SHIFT	0
482 
483 /* Cheetah/Cheetah+ Dcache size */
484 #define	CH_DCACHE_SIZE		0x10000
485 
486 /* Cheetah/Cheetah+ Dcache linesize */
487 #define	CH_DCACHE_LSIZE		0x20
488 
489 /* Cheetah/Cheetah+/Jaguar Icache size */
490 #define	CH_ICACHE_SIZE		0x8000
491 
492 /* Cheetah/Cheetah+/Jaguar Icache linesize */
493 #define	CH_ICACHE_LSIZE		0x20
494 
495 /* Panther Icache size */
496 #define	PN_ICACHE_SIZE		0x10000
497 
498 /* Panther Icache linesize */
499 #define	PN_ICACHE_LSIZE		0x40
500 
501 /* Pcache size for the cheetah family of CPUs */
502 #define	CH_PCACHE_SIZE		0x800
503 
504 /* Pcache linesize  for the cheetah family of CPUs */
505 #define	CH_PCACHE_LSIZE		0x40
506 
507 /*
508  * The cheetah+ CPU module handles Cheetah+, Jaguar, and Panther so
509  * we have to pick max size and min linesize values for the Icache
510  * accordingly.
511  */
512 #define	CHP_ICACHE_MAX_SIZE	PN_ICACHE_SIZE
513 #define	CHP_ICACHE_MIN_LSIZE	CH_ICACHE_LSIZE
514 
515 /*
516  * The minimum size needed to ensure consistency on a virtually address
517  * cache.  Computed by taking the largest virtually indexed cache and dividing
518  * by its associativity.
519  */
520 #define	CH_VAC_SIZE		0x4000
521 
522 /*
523  * The following definitions give the syndromes that will be seen when attempts
524  * are made to read data that has been intentionally poisoned.  Intentional
525  * poisoning is performed when an error has been detected, and is designed to
526  * allow software to effectively distinguish between root problems and secondary
527  * effects.  The following syndromes and their descriptions are taken from the
528  * UltraSPARC-III Cu Error Manual, Section 5.4.3.1.
529  */
530 
531 /*
532  * For a DSTAT = 2 or 3 event (see Sec 5.3.4.4) from the system bus for a
533  * cacheable load, data bits [1:0] are inverted in the data stored in the
534  * L2-cache.  The syndrome seen when one of these signalling words is read will
535  * be 0x11c.
536  */
537 #define	CH_POISON_SYND_FROM_DSTAT23	0x11c
538 
539 /*
540  * For an uncorrectable data ECC error from the L2-cache, data bits [127:126]
541  * are inverted in data sent to the system bus as part of a writeback or
542  * copyout.  The syndrome seen when one of these signalling words is read will
543  * be 0x071.
544  */
545 #define	CH_POISON_SYND_FROM_XXU_WRITE	0x71
546 
547 /*
548  * For uncorrectable data ECC error on the L2-cache read done to complete a
549  * store merge event, where bytes written by the processor are merged with
550  * bytes from an L2-cache line, ECC check bits [1:0] are inverted in the data
551  * scrubbed back to the L2-cache.  The syndrome seen when one of these
552  * signalling words is read will be 0x003.
553  */
554 #define	CH_POISON_SYND_FROM_XXU_WRMERGE	0x3
555 
556 /*
557  * To help understand the following definitions, this block of comments
558  * provides information on Cheetah's E$.
559  *
560  * Cheetah supports three different E$ sizes (1MB, 4MB, and 8MB). The
561  * number of E$ lines remains constant regardless of the size of the E$
562  * as does the subblock size, however the number of 64-byte subblocks per
563  * line varies depending on the E$ size.
564  *
565  * An E$ tag (for an E$ line) contains an EC_tag field, corresponding to the
566  * high order physical address bits of that E$ line's contents, and 1 to 8
567  * EC_state fields, indicating the state of each subblock. Due to the E$ line
568  * size variance depending on the total size of the E$, the number of bits in
569  * the EC_tag field varies as does the number of subblocks (and EC_state
570  * fields) per E$ line.
571  *
572  * A 1MB E$ has a line size of 64 bytes, containing 1 subblock per line.
573  * A 4MB E$ has a line size of 256 bytes, containing 4 subblocks per line.
574  * An 8MB E$ has a line size of 512 bytes, containing 8 subblocks per line.
575  *
576  * An E$ tag for a particular E$ line can be read via a diagnostic ASI
577  * as a 64-bit value.
578  * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows:
579  *	- for a 1MB E$, the EC_tag is in bits <43:21> and corresponds
580  *		to physical address bits <42:20> (bits <41:19> for Cheetah+)
581  *	- for a 4MB E$, the EC_tag is in bits <43:23> and corresponds
582  *		to physical address bits <42:22> (bits <41:21> for Cheetah+)
583  *	- for an 8MB E$, the EC_tag is in bits <43:24> and corresponds
584  *		to physical address bits <42:23> (bits <41:22> for Cheetah+)
585  * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted
586  * as follows:
587  *	- for a 1MB E$, EC_state0 is in bits <2:0>
588  *	- for a 4MB E$, EC_state0 is in bits <2:0>, EC_state1 is in
589  *		bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is
590  *		in bits <11:9>
591  *	- for an 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in
592  *		bits <5:3>, EC_state2 is in bits <8:6>, EC_state3 is
593  *		in bits <11:9>, EC_state4 is in bits <14:12>, EC_state5
594  *		is in bits <17:15>, EC_state6 is in bits <20:18>,
595  *		EC_state7 is in bits <23:21>
596  * Note that each EC_state field contains a value representing the state
597  * of its corresponding subblock.
598  *
599  */
600 /*
601  * Jaguar changes from Cheetah/Cheetah+ Ecache:
602  *
603  * The Jaguar Ecache is similiar to that used for Cheetah/Cheetah+ with a
604  * couple of differences :
605  *	- Jaguar Ecache only comes in 4MB and 8MB versions.
606  *		- 8MB E$ has 2 64 byte subblocks per line.
607  *		- 4MB E$ has 1 64 byte subblock per line.
608  *
609  * An E$ tag for a particular E$ line can be read via a diagnostic ASI
610  * as a 64-bit value.
611  * Within the E$ tag 64-bit value, the EC_tag field is interpreted as follows:
612  *	- for a 4MB E$, the EC_tag is in bits <41:21> and corresponds
613  *		to physical address bits <41:21>
614  *	- for a 8MB E$, the EC_tag is in bits <41:22> and corresponds
615  *		to physical address bits <41:22>
616  *
617  * The Jaguar E$ tag also contains LRU field in bit <42> which must be
618  * masked off when the tag value is being compared to a PA.
619  *
620  * Within the E$ tag 64-bit value, the EC_state field(s) is(are) interpreted
621  * as follows:
622  *	- for 4MB E$, EC_state0 is in bits <2:0>
623  *	- for 8MB E$, EC_state0 is in bits <2:0>, EC_state1 is in bits <5:3>.
624  * Each EC_state field contains a value representing the state of its
625  * corresponding subblock.
626  *
627  * Note that the subblock size and state values are the same for both
628  * Cheetah/Cheetah+ and Jaguar.
629  */
630 
631 /* Ecache sizes */
632 #define	CH_ECACHE_8M_SIZE	0x800000
633 #define	CH_ECACHE_4M_SIZE	0x400000
634 #define	CH_ECACHE_1M_SIZE	0x100000
635 
636 #define	PN_L2_SIZE		0x200000
637 #define	PN_L2_LINESIZE		64
638 #define	PN_L2_ECC_WORDS		2
639 #define	PN_L2_NWAYS		4
640 #define	PN_L2_SET_SIZE		(PN_L2_SIZE / PN_L2_NWAYS)
641 #define	PN_L2_MAX_SET		(PN_L2_SIZE - PN_L2_SET_SIZE)
642 #define	PN_L2_DATA_ECC_SEL	0x200000 /* bit 21 selects ECC */
643 #define	PN_L2_ECC_LO_REG	0x20 /* bit 5 set for L2 tag access */
644 #define	PN_L2_INDEX_MASK	0x7ffc0 /* bits 18:6 */
645 #define	PN_L2_WAY_INCR		0x80000	/* l2-ec-way = <20:19> */
646 #define	PN_L2_WAY_LIM		INT64_C(0x200000)
647 #define	PN_L2_WAY_SHIFT		19
648 #define	PN_L2_WAY_MASK		(3ULL << PN_L2_WAY_SHIFT) /* <20:19> */
649 #define	PN_L2_HW_ECC_SHIFT	22 /* Set to force HW ECC generation */
650 #define	PN_L2_SPLIT_EN_SHIFT	2 /* L2_Cache_Ctrl<2> = L2_split_en */
651 
652 #define	PN_L3_SIZE		0x2000000
653 #define	PN_L3_LINESIZE		64
654 #define	PN_L3_NWAYS		4
655 #define	PN_L3_SET_SIZE		(PN_L3_SIZE / PN_L3_NWAYS)
656 #define	PN_L3_MAX_SET		(PN_L3_SIZE - PN_L3_SET_SIZE)
657 #define	PN_L3_WAY_SHIFT		23
658 #define	PN_L3_HW_ECC_SHIFT	25	/* Set to force HW ECC generation */
659 #define	PN_L3_TAG_RD_MASK	0x7fffc0	/* ec_tag = PA<22:6>  */
660 #define	PN_L3_WAY_INCR		0x800000	/* ec_way = <24:23> */
661 #define	PN_L3_WAY_MASK		(3ULL << PN_L3_WAY_SHIFT) /* <24:23> */
662 #define	PN_L3_WAY_LIM		INT64_C(0x2000000)
663 #define	PN_L3_SPLIT_EN_SHIFT	30	/* L3_Cache_Ctrl<30> = L3_split_en */
664 
665 /* Pcache Defines */
666 #define	PN_PCACHE_ADDR_MASK	0x1c0		/* PC_addr = <8:6> */
667 #define	PN_PCACHE_WAY_INCR	0x200		/* PC_way = <10:9> */
668 #define	PN_PCACHE_WORD_SHIFT	3		/* PC_dbl_word = <5:3> */
669 #define	PN_PCACHE_NWAYS		4
670 
671 /* Cheetah Ecache is direct-mapped, Cheetah+ can be 2-way or direct-mapped */
672 #define	CH_ECACHE_NWAY		1
673 #if defined(CHEETAH_PLUS)
674 #define	CHP_ECACHE_NWAY		2
675 #define	PN_ECACHE_NWAY		4
676 #endif	/* CHEETAH_PLUS */
677 #if defined(JALAPENO) || defined(SERRANO)
678 #define	JP_ECACHE_NWAY		4
679 #define	JP_ECACHE_NWAY_SHIFT	2
680 #endif /* JALAPENO || SERRANO */
681 
682 /* Maximum Ecache size */
683 #define	CH_ECACHE_MAX_SIZE	CH_ECACHE_8M_SIZE
684 
685 /* Minimum Ecache line size */
686 #define	CH_ECACHE_MIN_LSIZE	64
687 
688 /* Maximum Ecache line size - 8Mb Ecache has 512 byte linesize */
689 #define	CH_ECACHE_MAX_LSIZE	512
690 
691 /* Size of Ecache data staging register size (see Cheetah PRM 10.7.2) */
692 #define	CH_ECACHE_STGREG_SIZE	32
693 #define	CH_ECACHE_STGREG_TOTALSIZE	40	/* data regs + ecc */
694 
695 /* The number of staging registers containing data, for ASI_EC_DATA */
696 #define	CH_ECACHE_STGREG_NUM	(CH_ECACHE_STGREG_SIZE / sizeof (uint64_t))
697 
698 /* Size of Ecache data subblock which has state field in Ecache tag */
699 #define	CH_ECACHE_SUBBLK_SIZE	64
700 #define	CH_ECACHE_SUBBLK_SHIFT	6
701 
702 #if defined(JALAPENO) || defined(SERRANO)
703 #define	JP_ECACHE_MAX_LSIZE	CH_ECACHE_SUBBLK_SIZE
704 #define	JP_ECACHE_MAX_SIZE	0x400000
705 #endif /* JALAPENO || SERRANO */
706 
707 /*
708  * Maximum ecache setsize to support page coloring of heterogenous
709  * cheetah+ cpus. Max ecache setsize is calculated to be the max ecache size
710  * divided by the minimum associativity of the max ecache.
711  *
712  * NOTE: CHP_ECACHE_MAX_SIZE and CHP_ECACHE_MIN_NWAY need to be updated with
713  * new cheetah+ cpus. The maximum setsize may not necessarily be associated with
714  * the max ecache size if the cache associativity is large. If so, MAX_SETSIZE
715  * needs to be updated accordingly.
716  */
717 #if defined(CHEETAH_PLUS)
718 #define	CHP_ECACHE_MIN_NWAY	1	/* direct-mapped */
719 #define	CHP_ECACHE_MAX_SIZE	CH_ECACHE_MAX_SIZE
720 #define	CHP_ECACHE_MAX_SETSIZE	(CHP_ECACHE_MAX_SIZE / CHP_ECACHE_MIN_NWAY)
721 #endif	/* CHEETAH_PLUS */
722 
723 /*
724  * Bits to shift EC_tag field of E$ tag to form PA
725  * (See Cheetah PRM 10.7.4, Cheetah+ Delta PRM 10.7)
726  */
727 #if defined(JALAPENO) || defined(SERRANO)
728 #define	CH_ECTAG_PA_SHIFT	18
729 #elif defined(CHEETAH_PLUS)
730 #define	CH_ECTAG_PA_SHIFT	2
731 #else	/* CHEETAH_PLUS */
732 #define	CH_ECTAG_PA_SHIFT	1
733 #endif	/* CHEETAH_PLUS */
734 #define	PN_L3TAG_PA_SHIFT	1
735 #define	PN_L3TAG_PA_MASK	0xfffff000000	/* tag bits[43:24] */
736 #define	PN_L2TAG_PA_MASK	0x7fffff80000	/* tag bits[42:19] */
737 
738 #if defined(JALAPENO) || defined(SERRANO)
739 /*
740  * Macros for Jalapeno L2 Cache Tag/State/Parity
741  *
742  * +-----------+--------+--------+----------------------+
743  * |   -       | EC_par |EC_state|  EC_tag = PA[42:18]  |
744  * +-----------+--------+--------+----------------------+
745  *    63:29        28      27:25         24:0
746  */
747 /*
748  * Constants representing the complete Jalapeno Ecache tag state:
749  */
750 #define	JP_ECSTATE_SIZE		3		/* three bits */
751 #define	JP_ECSTATE_MASK		0x7		/* three bit field */
752 #define	JP_ECSTATE_INV		0x0		/* invalid */
753 #define	JP_ECSTATE_SHR		0x1		/* shared */
754 #define	JP_ECSTATE_RES1		0x2		/* reserved */
755 #define	JP_ECSTATE_EXL		0x3		/* exclusive */
756 #define	JP_ECSTATE_RES2		0x4		/* reserved */
757 #define	JP_ECSTATE_OWN		0x5		/* owner */
758 #define	JP_ECSTATE_MOD		0x7		/* modified */
759 #define	JP_ECSTATE_RES3		0x6		/* reserved */
760 #define	JP_ECTAG_STATE_SHIFT	25
761 
762 #define	CH_ECSTATE_SIZE		JP_ECSTATE_SIZE
763 #define	CH_ECSTATE_MASK		JP_ECSTATE_MASK
764 #define	CH_ECSTATE_INV		JP_ECSTATE_INV
765 #define	CH_ECSTATE_SHR		JP_ECSTATE_SHR
766 #define	CH_ECSTATE_EXL		JP_ECSTATE_EXL
767 #define	CH_ECSTATE_OWN		JP_ECSTATE_OWN
768 #define	CH_ECSTATE_MOD		JP_ECSTATE_MOD
769 #define	CH_ECSTATE_RES1		JP_ECSTATE_RES1
770 #define	CH_ECSTATE_OWS		JP_ECSTATE_RES3
771 #define	CH_ECSTATE_RES2		JP_ECSTATE_RES2
772 
773 /* Number of subblock states per Ecache line. */
774 #define	CH_ECTAG_NSUBBLKS(totalsize)	1
775 
776 /* Mask for Tag state(s) field, 3 bits per subblock state. */
777 #define	CH_ECTAG_STATE_SHIFT(subblk)	JP_ECTAG_STATE_SHIFT
778 #define	CH_ECTAG_STATE_MASK(totalsize)			\
779 	((uint64_t)(JP_ECSTATE_MASK<<JP_ECTAG_STATE_SHIFT))
780 
781 /* For a line to be invalid, all of its subblock states must be invalid. */
782 #define	CH_ECTAG_LINE_INVALID(totalsize, tag)		\
783 	(((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0)
784 
785 /* Build address mask for tag physical address bits. */
786 #define	CH_ECTAG_PA_MASK(setsize)	P2ALIGN(C_AFAR_PA, (int)(setsize))
787 
788 /* Get physical address bits from the EC_tag field of an E$ tag */
789 #define	CH_ECTAG_TO_PA(setsize, tag)	(((tag) << CH_ECTAG_PA_SHIFT) &	\
790 	CH_ECTAG_PA_MASK(setsize))
791 
792 /* Given a physical address, compute index for subblock tag state. */
793 #define	CH_ECTAG_PA_TO_SUBBLK(totalsize, pa)		1
794 
795 /* Given a physical address and assoc. tag, get the subblock state. */
796 #define	CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag)			\
797 	(((tag) >> JP_ECTAG_STATE_SHIFT) &	JP_ECSTATE_MASK)
798 
799 #else /* JALAPENO || SERRANO */
800 
801 /*
802  * Constants representing the complete Cheetah Ecache tag state:
803  */
804 #define	CH_ECSTATE_SIZE		3		/* three bits per subblock */
805 #define	CH_ECSTATE_MASK		0x7		/* three bit field */
806 #define	CH_ECSTATE_INV		0x0		/* invalid */
807 #define	CH_ECSTATE_SHR		0x1		/* shared */
808 #define	CH_ECSTATE_EXL		0x2		/* exclusive */
809 #define	CH_ECSTATE_OWN		0x3		/* owner */
810 #define	CH_ECSTATE_MOD		0x4		/* modified */
811 #define	CH_ECSTATE_RES1		0x5		/* reserved */
812 #define	CH_ECSTATE_OWS		0x6		/* owner/shared */
813 #define	CH_ECSTATE_RES2		0x7		/* reserved */
814 
815 /*
816  * Macros for Cheetah Ecache tags
817  */
818 
819 /* Number of subblock states per Ecache line. */
820 #define	CH_ECTAG_NSUBBLKS(totalsize)	((totalsize) / CH_ECACHE_1M_SIZE)
821 
822 /* Mask for Tag state(s) field, 3 bits per subblock state. */
823 #define	CH_ECTAG_STATE_SHIFT(subblk)	(subblk * CH_ECSTATE_SIZE)
824 #define	CH_ECTAG_STATE_MASK(totalsize)			\
825 	((uint64_t)					\
826 	((1 << (CH_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1))
827 
828 /* For a line to be invalid, all of its subblock states must be invalid. */
829 #define	CH_ECTAG_LINE_INVALID(totalsize, tag)		\
830 	(((tag) & CH_ECTAG_STATE_MASK(totalsize)) == 0)
831 
832 /* Build address mask for tag physical address bits. */
833 #define	CH_ECTAG_PA_MASK(setsize)	P2ALIGN(C_AFAR_PA, (int)(setsize))
834 
835 /* Get physical address bits from the EC_tag field of an E$ tag */
836 #define	CH_ECTAG_TO_PA(setsize, tag)	(((tag) >> CH_ECTAG_PA_SHIFT) &	\
837 	CH_ECTAG_PA_MASK(setsize))
838 
839 /* Given a physical address, compute index for subblock tag state. */
840 #define	CH_ECTAG_PA_TO_SUBBLK(totalsize, pa)		\
841 	(((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (CH_ECTAG_NSUBBLKS(totalsize) - 1))
842 
843 /* Given a physical address and assoc. tag, get the subblock state. */
844 #define	CH_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag)			\
845 	(((tag) >>							\
846 	(CH_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) &	\
847 	CH_ECSTATE_MASK)
848 #endif /* JALAPENO || SERRANO */
849 
850 /* Panther only has one EC_State field in the L3 tag */
851 #define	PN_L3_LINE_INVALID(tag)		(((tag) & CH_ECSTATE_MASK) == 0)
852 
853 /* Panther only has one State field in the L2 tag */
854 #define	PN_L2_LINE_INVALID(tag)		(((tag) & CH_ECSTATE_MASK) == 0)
855 
856 /* Get physical address bits from the EC_tag field of an L3$ tag */
857 #define	PN_L3TAG_TO_PA(tag)		(((tag) & PN_L3TAG_PA_MASK) >> \
858 	PN_L3TAG_PA_SHIFT)
859 
860 /* Get physical address bits from the tag field of an L2$ tag */
861 #define	PN_L2TAG_TO_PA(tag)		((tag) & PN_L2TAG_PA_MASK)
862 
863 #if defined(JALAPENO) || defined(SERRANO)
864 /*
865  * Jalapeno L2 Cache ASI_ECACHE_FLUSH:
866  * +-------+-----------------+--------+---+-----+-------------+------+
867  * |   -   | Port_ID |   -   | EC_Way | 1 |  -  | EC_Tag_Addr |   -  |
868  * +-------+-----------------+--------+---+-----+-------------+------+
869  *  63:41     40:36    35:34    33:32  31  30:18      17:6       5:0
870  */
871 
872 #define	JP_EC_TO_SET_SIZE_SHIFT		2
873 #define	JP_ECACHE_IDX_DISP_FLUSH	INT64_C(0x0000000080000000)
874 #define	JP_ECFLUSH_PORTID_SHIFT		36
875 #define	JP_ECFLUSH_EC_WAY_SHIFT		32
876 #define	JP_EC_TAG_DATA_WAY_SHIFT	JP_ECFLUSH_EC_WAY_SHIFT
877 #endif	/* JALAPENO || SERRANO */
878 
879 /*
880  * Macros for Jaguar Ecache tags
881  */
882 
883 /* Ecache sizes */
884 #define	JG_ECACHE_8M_SIZE	0x800000
885 #define	JG_ECACHE_4M_SIZE	0x400000
886 
887 /* Jaguar E$ tag LRU mask */
888 #define	JG_LRU_MASK UINT64_C(0x0000040000000000) /* PA<42> LRU bit */
889 
890 /*
891  * Note that Jaguar and Cheetah/Cheetah+ have the same subblock state size
892  * so rather than duplicating existing defn's we can use the Cheetah+ versions
893  * in the Jaguar defn's below.
894  */
895 /* Number of subblock states per Ecache line. */
896 #define	JG_ECTAG_NSUBBLKS(cachesize)	((cachesize) / JG_ECACHE_4M_SIZE)
897 
898 /* Mask for Tag state(s) field, 3 bits per subblock state. */
899 #define	JG_ECTAG_STATE_MASK(totalsize)			\
900 	((uint64_t)					\
901 	((1 << (JG_ECTAG_NSUBBLKS(totalsize) * CH_ECSTATE_SIZE)) - 1))
902 
903 /* For a line to be invalid, all of its subblock states must be invalid. */
904 #define	JG_ECTAG_LINE_INVALID(totalsize, tag)		\
905 	(((tag) & JG_ECTAG_STATE_MASK(totalsize)) == 0)
906 
907 /* Build address mask for tag physical address bits. */
908 #define	JG_ECTAG_PA_MASK(setsize)	P2ALIGN(((~JG_LRU_MASK) & C_AFAR_PA), \
909 							(int)(setsize))
910 
911 /* Get physical address bits from the EC_tag field of an E$ tag */
912 #define	JG_ECTAG_TO_PA(setsize, tag)	((tag & JG_ECTAG_PA_MASK(setsize)))
913 
914 /* Given a physical address, compute index for subblock tag state. */
915 #define	JG_ECTAG_PA_TO_SUBBLK(totalsize, pa)		\
916 	(((pa) >> CH_ECACHE_SUBBLK_SHIFT) & (JG_ECTAG_NSUBBLKS(totalsize) - 1))
917 
918 /* Given a physical address and assoc. tag, get the subblock state. */
919 #define	JG_ECTAG_PA_TO_SUBBLK_STATE(totalsize, pa, tag)			\
920 	(((tag) >>							\
921 	(JG_ECTAG_PA_TO_SUBBLK(totalsize, pa) * CH_ECSTATE_SIZE)) &	\
922 	CH_ECSTATE_MASK)
923 
924 
925 #if defined(CHEETAH_PLUS)
926 /*
927  * Cheetah+ Tag ECC Bit and Displacement Flush Bit in Ecache Tag Access.
928  * See Cheetah+ Delta PRM 10.7
929  */
930 #define	CHP_ECACHE_IDX_TAG_ECC		INT64_C(0x0000000000800000)
931 #define	CHP_ECACHE_IDX_DISP_FLUSH	INT64_C(0x0000000001000000)
932 #define	PN_L2_IDX_DISP_FLUSH		INT64_C(0x0000000000800000)
933 #define	PN_L3_IDX_DISP_FLUSH		INT64_C(0x0000000004000000)
934 #endif	/* CHEETAH_PLUS */
935 
936 /*
937  * Macros for Cheetah Dcache diagnostic accesses.
938  */
939 
940 /*
941  * Dcache Index Mask for bits from *AFAR*.  Note that Dcache is virtually
942  * indexed, so only bits [12:5] are valid from the AFAR.  This
943  * means we have to search through the 4 ways + bit 13 (i.e. we have
944  * to try 8 indexes).
945  */
946 #define	CH_DCACHE_IDX_MASK		0x01fe0
947 #define	CH_DCACHE_IDX_INCR		0x02000
948 #define	CH_DCACHE_IDX_LIMIT		0x10000
949 #define	CH_DCACHE_NWAY			4
950 #define	CH_DCACHE_WAY_MASK		0x0c000
951 #define	CH_DCACHE_WAY_SHIFT		14
952 #define	CH_DCIDX_TO_WAY(idx)		(((idx) & CH_DCACHE_WAY_MASK) >> \
953 						CH_DCACHE_WAY_SHIFT)
954 #define	CH_DCTAG_PA_MASK		INT64_C(0x000007ffffffe000)
955 #define	CH_DCTAG_PA_SHIFT		12
956 #define	CH_DCTAG_VALID_BIT		INT64_C(0x0000000000000001)
957 #define	CH_DCTAG_LINE_INVALID(tag)	(((tag) & CH_DCTAG_VALID_BIT) == 0)
958 #define	CH_DCIDX_TO_ADDR(idx)		((idx) & CH_DCACHE_IDX_MASK)
959 #define	CH_DCTAG_TO_PA(tag)		(((tag) << CH_DCTAG_PA_SHIFT) & \
960 					    CH_DCTAG_PA_MASK)
961 #define	CH_DCTAG_MATCH(tag, pa)		(!CH_DCTAG_LINE_INVALID(tag) && \
962 			    ((pa) & CH_DCTAG_PA_MASK) == CH_DCTAG_TO_PA(tag))
963 #define	CH_DCSNTAG_MASK			INT64_C(0x000007ffffffe000)
964 #define	CH_DCSNTAG_TO_PA(tag)		((tag << CH_DCTAG_PA_SHIFT) \
965 							& CH_DCSNTAG_MASK)
966 #define	CH_DCUTAG_TO_UTAG(tag)		((tag) & 0xff)
967 #define	CH_DCUTAG_TO_VA(tag)		((tag & 0xff) << 14)
968 #define	CH_DCUTAG_IDX_MASK		0x03fe0
969 #define	CH_DC_DATA_REG_SIZE		32
970 #define	CH_DC_UTAG_MASK			0xff
971 #if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO)
972 #define	CHP_DCTAG_PARMASK		INT64_C(0x000000007ffffffe)
973 #define	CHP_DCSNTAG_PARMASK		INT64_C(0x000000007ffffffe)
974 #define	CHP_DCTAG_MASK			INT64_C(0x000003ffffffe000)
975 #define	CHP_DCSNTAG_MASK		INT64_C(0x000003ffffffe000)
976 #define	CHP_DCWAY_MASK			INT64_C(0x0000000000003fe0)
977 #define	CHP_DCUTAG_TO_UTAG(tag)		((tag) & 0xffff)
978 #define	CHP_DCPATAG_TO_PA(tag)		((tag << CH_DCTAG_PA_SHIFT) \
979 							& CHP_DCTAG_MASK)
980 #define	CHP_DCSNTAG_TO_PA(tag)		((tag << CH_DCTAG_PA_SHIFT) \
981 							& CHP_DCSNTAG_MASK)
982 #define	CHP_DC_IDX(dcp)			((dcp->dc_idx & 0x1fc0) >> 5)
983 #define	CHP_DCTAG_PARITY(tag)		(tag & CHP_DC_TAG)
984 #define	CHP_DCSNTAG_PARITY(tag)		(tag & CHP_DC_SNTAG)
985 #define	CHP_DC_TAG			0x1
986 #define	CHP_DC_SNTAG			0x2
987 #define	PN_DC_DATA_PARITY_SHIFT    	8
988 #define	PN_DC_DATA_PARITY_MASK    	0xff
989 #define	PN_DC_DATA_ALL_PARITY_MASK    	0xffffffff
990 #endif	/* CHEETAH_PLUS || JALAPENO || SERRANO */
991 #define	PN_DC_DATA_PARITY_BIT_SHIFT    	16
992 
993 /*
994  * Macros for Cheetah Icache diagnostic accesses.
995  */
996 
997 /*
998  * Icache Index Mask for bits from *AFAR*. Note that the Icache is virtually
999  * indexed for Panther and physically indexed for other CPUs. For Panther,
1000  * we obtain an index by looking at bits[12:6] of the AFAR PA and we check
1001  * both lines associated with bit 13 = 0 or 1 (total of 8 entries to check).
1002  * For non-Panther CPUs we get our index by just looking at bits[12:5] of
1003  * the AFAR PA (total of 4 entries to check). The Icache index is also
1004  * confusing because we need to shift the virtual address bits left by one
1005  * for the index.
1006  */
1007 #define	CH_ICACHE_IDX_MASK		0x01fe0
1008 #define	PN_ICACHE_IDX_MASK		0x03fc0
1009 #define	PN_ICACHE_VA_IDX_MASK		0x01fc0
1010 #define	CH_ICACHE_IDX_SHIFT		1
1011 #define	CH_ICACHE_IDX_INCR		0x04000
1012 #define	PN_ICACHE_IDX_INCR		0x08000
1013 #define	CH_ICACHE_IDX_LIMIT		0x10000
1014 #define	PN_ICACHE_IDX_LIMIT		0x20000
1015 #define	CH_ICACHE_NWAY			4
1016 #define	CH_ICACHE_WAY_MASK		0x0c000
1017 #define	CH_ICACHE_WAY_SHIFT		14
1018 #define	PN_ICACHE_WAY_MASK		0x18000
1019 #define	PN_ICACHE_WAY_SHIFT		15
1020 #define	CH_ICTAG_PA			0x00
1021 #define	CH_ICTAG_UTAG			0x08
1022 #define	CH_ICTAG_UPPER			0x10
1023 #define	CH_ICTAG_LOWER			0x30
1024 #define	CH_ICTAG_TMASK			0x3f
1025 #define	CH_ICPATAG_MASK			INT64_C(0x000007ffffffe000)
1026 #define	CH_ICPATAG_LBITS		0xff	/* lower 8 bits undefined */
1027 #define	CH_ICPATAG_SHIFT		5
1028 #define	CH_ICIDX_TO_WAY(idx)		(((idx) & CH_ICACHE_WAY_MASK) >> \
1029 						CH_ICACHE_WAY_SHIFT)
1030 #define	PN_ICIDX_TO_WAY(idx)		(((idx) & PN_ICACHE_WAY_MASK) >> \
1031 						PN_ICACHE_WAY_SHIFT)
1032 #define	CH_ICIDX_TO_ADDR(idx)		(((idx) >> CH_ICACHE_IDX_SHIFT) & \
1033 						CH_ICACHE_IDX_MASK)
1034 #define	PN_ICIDX_TO_ADDR(idx)		(((idx) >> CH_ICACHE_IDX_SHIFT) & \
1035 						PN_ICACHE_IDX_MASK)
1036 #define	CH_ICPATAG_TO_PA(tag)		(((tag) << CH_ICPATAG_SHIFT) & \
1037 						CH_ICPATAG_MASK)
1038 #define	CH_ICPATAG_MATCH(tag, pa)	(CH_ICPATAG_TO_PA(tag) == \
1039 						((pa) & CH_ICPATAG_MASK))
1040 #define	CH_ICUTAG_MASK			INT64_C(0x00000000001fe000)
1041 #define	CH_ICUTAG_TO_UTAG(tag)		(((tag) >> 38) & 0xff)
1042 #define	CH_ICUTAG_TO_VA(tag)		(((tag) >> 25) & CH_ICUTAG_MASK)
1043 #define	CH_ICSNTAG_MASK			INT64_C(0x000007ffffffe000)
1044 #define	CH_ICSNTAG_TO_PA(tag)		(((tag) << 5) & CH_ICSNTAG_MASK)
1045 #define	CH_ICLOWER_VALID		INT64_C(0x0004000000000000)
1046 #define	CH_ICUPPER_VALID		INT64_C(0x0004000000000000)
1047 #define	CH_ICLOWER_TO_VPRED(lower)	(((lower) >> 46) & 0xf)
1048 #define	CH_ICUPPER_TO_VPRED(upper)	(((upper) >> 46) & 0xf)
1049 #if defined(CHEETAH_PLUS)
1050 #define	CH_ICTAG_MATCH(icp, pa)		(((icp->ic_lower | icp->ic_upper) & \
1051 					    CH_ICLOWER_VALID) && \
1052 					    CH_ICPATAG_MATCH(icp->ic_patag, pa))
1053 #define	PN_ICUTAG_TO_VA(tag)		((tag >> 24) & PN_ICUTAG_MASK)
1054 #else	/* CHEETAH_PLUS */
1055 #define	CH_ICTAG_MATCH(icp, pa)		((icp->ic_lower & CH_ICLOWER_VALID) &&\
1056 					    CH_ICPATAG_MATCH(icp->ic_patag, pa))
1057 #define	PN_ICUTAG_TO_VA(tag)		0
1058 #endif	/* CHEETAH_PLUS */
1059 
1060 #define	CH_IC_DATA_REG_SIZE		64
1061 #define	PN_IC_DATA_REG_SIZE		128
1062 #if defined(CHEETAH_PLUS) || defined(JALAPENO) || defined(SERRANO)
1063 #define	CHP_IC_IDX(icp)			((icp->ic_idx & 0x3fc0) >> 6)
1064 #define	PN_IC_IDX(icp)			((icp->ic_idx & 0x7f80) >> 7)
1065 #define	CHP_ICPATAG_MASK		INT64_C(0x000003ffffffe000)
1066 #define	CHP_ICSNTAG_MASK		INT64_C(0x000003ffffffe000)
1067 #define	CHP_ICUTAG_MASK			INT64_C(0x00000000001fe000)
1068 #define	PN_ICUTAG_MASK			INT64_C(0x00000000003fc000)
1069 #define	CHP_ICWAY_MASK			INT64_C(0x0000000000003fe0)
1070 #define	CHP_ICPATAG_TO_PA(tag)		((tag << 5) & CHP_ICPATAG_MASK)
1071 #define	CHP_ICSNTAG_TO_PA(tag)		((tag << 5) & CHP_ICSNTAG_MASK)
1072 #define	CHP_ICUTAG_TO_VA(tag)		((tag >> 25) & CHP_ICUTAG_MASK)
1073 #define	CHP_ICPATAG_PARMASK		INT64_C(0x0000003fffffff00)
1074 #define	CHP_ICSNTAG_PARMASK		INT64_C(0x0000003fffffff00)
1075 
1076 /*
1077  * Cheetah+ Icache data parity masks, see Cheetah+ Delta PRM 7.3
1078  * PC-relative instructions have different bits protected by parity.
1079  * Predecode bit 7 is not parity protected and indicates if the instruction
1080  * is PC-relative or not.
1081  */
1082 #define	CH_ICDATA_PRED_ISPCREL		INT64_C(0x0000008000000000)
1083 #define	CHP_ICDATA_PCREL_PARMASK	INT64_C(0x0000039ffffff800)
1084 #define	CHP_ICDATA_NPCREL_PARMASK	INT64_C(0x000003bfffffffff)
1085 #define	PN_ICDATA_PARITY_BIT_MASK	INT64_C(0x40000000000)
1086 #define	CHP_ICTAG_PARITY(tag)		(tag & CHP_IC_TAG)
1087 #define	CHP_ICSNTAG_PARITY(tag)		(tag & CHP_IC_SNTAG)
1088 #define	CHP_IC_TAG			0x1
1089 #define	CHP_IC_SNTAG			0x2
1090 #endif	/* CHEETAH_PLUS || JALAPENO || SERRANO */
1091 #if defined(CHEETAH_PLUS)
1092 #define	PN_IPB_TAG_ADDR_LINESIZE	0x40
1093 #define	PN_IPB_TAG_ADDR_MAX		0x3c0
1094 #endif	/* CHEETAH_PLUS */
1095 
1096 /*
1097  * Macros for Pcache diagnostic accesses.
1098  */
1099 #define	CH_PC_WAY_MASK			0x600
1100 #define	CH_PC_WAY_SHIFT			9
1101 #define	CH_PCIDX_TO_WAY(idx)		(((idx) & CH_PC_WAY_MASK) >> \
1102 						CH_PC_WAY_SHIFT)
1103 #define	CH_PC_DATA_REG_SIZE		64
1104 #define	CH_PCACHE_NWAY			4
1105 #define	PN_PC_PARITY_SHIFT		50
1106 #define	PN_PC_PARITY_MASK		0xff
1107 #define	PN_PC_PARITY_BITS(status)	\
1108 	(((status) >> PN_PC_PARITY_SHIFT) & PN_PC_PARITY_MASK)
1109 #define	CH_PC_IDX_ADR(pcp)		((pcp->pc_idx & 0x1c0) >> 6)
1110 #define	CH_PCTAG_ADDR_SHIFT		6
1111 #define	CH_PC_PA_MASK			0x7ffffffffc0
1112 #define	CH_PCTAG_TO_VA(tag)		((tag) << CH_PCTAG_ADDR_SHIFT)
1113 #define	CH_PCSTAG_TO_PA(tag)		(((tag) << CH_PCTAG_ADDR_SHIFT) & \
1114 					    CH_PC_PA_MASK)
1115 #define	CH_PCTAG_BNK0_VALID_MASK	0x2000000000000000
1116 #define	CH_PCTAG_BNK1_VALID_MASK	0x1000000000000000
1117 #define	CH_PCTAG_BNK0_INVALID(tag)	(((tag) & CH_PCTAG_BNK0_VALID_MASK) == \
1118 					    0)
1119 #define	CH_PCTAG_BNK1_INVALID(tag)	(((tag) & CH_PCTAG_BNK1_VALID_MASK) == \
1120 					    0)
1121 
1122 /*
1123  * CPU Log Out Structure parameters.
1124  * This structure is filled in by the Error Trap handlers and captures the
1125  * Ecache/Dcache/Icache line(s) associated with the AFAR.
1126  * For Cheetah Phase II, this structure is filled in at the TL=0 code.  For
1127  * Cheetah Phase III, this will be filled in at the trap handlers.
1128  */
1129 
1130 /*
1131  * We use this to mark the LOGOUT structure as invalid.  Note that
1132  * this cannot be a valid AFAR, as AFAR bits outside of [41:5] should always
1133  * be zero.
1134  */
1135 #define	LOGOUT_INVALID_U32	0xecc1ecc1
1136 #define	LOGOUT_INVALID_L32	0xecc1ecc1
1137 #define	LOGOUT_INVALID		UINT64_C(0xecc1ecc1ecc1ecc1)
1138 
1139 /*
1140  * Max number of TLs to support for Fast ECC or Cache Parity Errors
1141  * at TL>0.  Traps are OK from TL=1-2, at TL>=3, we will Red Mode.
1142  */
1143 #define	CH_ERR_TL1_TLMAX	2
1144 
1145 /*
1146  * Software traps used by TL>0 handlers.
1147  */
1148 #define	SWTRAP_0		0	/* Used by Fast ECC */
1149 #define	SWTRAP_1		1	/* Used by Dcache Parity */
1150 #define	SWTRAP_2		2	/* Used by Icache Parity */
1151 
1152 /*
1153  * Bit mask defines for various Cheetah Error conditions.
1154  */
1155 #define	CH_ERR_FECC	0x01	/* Data/Event is Fast ECC */
1156 #define	CH_ERR_IPE	0x02	/* Data/Event is Icache Parity Error */
1157 #define	CH_ERR_DPE	0x04	/* Data/Event is Dcache Parity Error */
1158 #define	CH_ERR_PANIC	0x08	/* Fatal error in TL>0 handler */
1159 #define	CH_ERR_TL	0x10	/* Error occured at TL>0 */
1160 #define	CH_ERR_ME_SHIFT	   8	/* If multiple errors, shift left newest */
1161 #define	CH_ERR_ME_FLAGS(x)	((x) >> CH_ERR_ME_SHIFT)
1162 
1163 /*
1164  * Defines for Bit8 (CH_ERR_TSTATE_IC_ON) and Bit9 (CH_ERR_TSTATE_DC_ON)
1165  * in %tstate, which is used to remember D$/I$ state on Fast ECC handler
1166  * at TL>0.  Note that DCU_IC=0x1, DCU_DC=0x2.
1167  */
1168 #define	CH_ERR_G2_TO_TSTATE_SHFT	10
1169 #define	CH_ERR_DCU_TO_TSTATE_SHFT	8
1170 #define	CH_ERR_TSTATE_IC_ON	(DCU_IC << CH_ERR_DCU_TO_TSTATE_SHFT)
1171 #define	CH_ERR_TSTATE_DC_ON	(DCU_DC << CH_ERR_DCU_TO_TSTATE_SHFT)
1172 
1173 /*
1174  * Multiple offset TL>0 handler structure elements
1175  */
1176 #define	CH_ERR_TL1_DATA		(CH_ERR_TL1_LOGOUT + CH_CLO_DATA)
1177 #define	CH_ERR_TL1_SDW_DATA	(CH_ERR_TL1_LOGOUT + CH_CLO_SDW_DATA)
1178 #define	CH_ERR_TL1_NEST_CNT	(CH_ERR_TL1_LOGOUT + CH_CLO_NEST_CNT)
1179 #define	CH_ERR_TL1_AFAR		(CH_ERR_TL1_DATA + CH_CHD_AFAR)
1180 #define	CH_ERR_TL1_AFSR		(CH_ERR_TL1_DATA + CH_CHD_AFSR)
1181 #define	CH_ERR_TL1_SDW_AFAR	(CH_ERR_TL1_SDW_DATA + CH_CHD_AFAR)
1182 #define	CH_ERR_TL1_SDW_AFSR	(CH_ERR_TL1_SDW_DATA + CH_CHD_AFSR)
1183 #define	CH_ERR_TL1_SDW_AFSR_EXT	(CH_ERR_TL1_SDW_DATA + CH_CHD_AFSR_EXT)
1184 
1185 /*
1186  * Interval for deferred CEEN reenable
1187  */
1188 #define	CPU_CEEN_DELAY_SECS		6
1189 
1190 /*
1191  * flags for flt_trapped_ce variable
1192  */
1193 #define	CE_CEEN_DEFER		0x1	/* no CEEN reenable in trap handler */
1194 #define	CE_CEEN_NODEFER		0x2	/* reenable CEEN in handler */
1195 #define	CE_CEEN_TIMEOUT		0x4	/* CE caught by timeout */
1196 #define	CE_CEEN_TRAPPED		0x8	/* CE caught by trap */
1197 
1198 /*
1199  * default value for cpu_ce_not_deferred
1200  */
1201 #if defined(JALAPENO) || defined(SERRANO)
1202 #define	CPU_CE_NOT_DEFERRED	(C_AFSR_CECC_ERRS & \
1203 		~(C_AFSR_CE | C_AFSR_FRC | C_AFSR_RCE | C_AFSR_EMC))
1204 #else /* JALAPENO || SERRANO */
1205 #if defined(CHEETAH_PLUS)
1206 #define	CPU_CE_NOT_DEFERRED	(C_AFSR_CECC_ERRS & \
1207 		~(C_AFSR_CE | C_AFSR_EMC | C_AFSR_THCE))
1208 #else /* CHEETAH_PLUS */
1209 #define	CPU_CE_NOT_DEFERRED	(C_AFSR_CECC_ERRS & \
1210 		~(C_AFSR_CE | C_AFSR_EMC))
1211 #endif /* CHEETAH_PLUS */
1212 #endif /* JALAPENO || SERRANO */
1213 
1214 #define	CPU_CE_NOT_DEFERRED_EXT	(C_AFSR_EXT_CECC_ERRS & \
1215 		~(C_AFSR_L3_THCE))
1216 
1217 #if defined(CHEETAH_PLUS)
1218 
1219 /*
1220  * VA for primary and shadow AFSR/AFAR/AFSR_EXT registers
1221  */
1222 #define	ASI_SHADOW_REG_VA	0x8
1223 #define	ASI_AFSR_EXT_VA		0x10
1224 #define	ASI_SHADOW_AFSR_EXT_VA	0x18
1225 
1226 /*
1227  * Bitmask for keeping track of core parking in ECC error handlers.
1228  * We share a register that also saves the DCUCR value so we use
1229  * one of the reserved bit positions of the DCUCR register to keep
1230  * track of whether or not we have parked our sibling core.
1231  */
1232 #define	PN_PARKED_OTHER_CORE	0x20
1233 #define	PN_BOTH_CORES_RUNNING	0x3
1234 
1235 /*
1236  * Panther EMU Activity Status Register Bits.
1237  */
1238 #define	ASI_EMU_ACT_STATUS_VA	0x18
1239 #define	MCU_ACT_STATUS		INT64_C(0x0000000000000001)
1240 #define	SIU_ACT_STATUS		INT64_C(0x0000000000000002)
1241 #endif	/* CHEETAH_PLUS */
1242 
1243 #define	ASI_CESR_ID_VA		0x40    /* ASI_CESRD_ID per-core registers */
1244 
1245 #define	ASR_DISPATCH_CONTROL		%asr18
1246 #define	ASR_DISPATCH_CONTROL_BPE	0x20
1247 
1248 /*
1249  * Max number of E$ sets logged in ch_diag_data structure
1250  */
1251 #define	CHD_EC_DATA_SETS	4	/* max 4 sets of E$ data */
1252 
1253 /*
1254  * Definitions for Panther TLB parity handling.
1255  */
1256 #define	PN_ITLB_NWAYS		2
1257 #define	PN_NUM_512_ITLBS	1
1258 #define	PN_DTLB_NWAYS		2
1259 #define	PN_NUM_512_DTLBS	2
1260 #define	PN_SFSR_PARITY_SHIFT	12
1261 #define	PN_ITLB_PGSZ_SHIFT	22
1262 #define	PN_ITLB_PGSZ_MASK	(7 << PN_ITLB_PGSZ_SHIFT)
1263 #define	PN_DTLB_PGSZ0_SHIFT	16
1264 #define	PN_DTLB_PGSZ0_MASK	(7 << PN_DTLB_PGSZ0_SHIFT)
1265 #define	PN_DTLB_PGSZ1_SHIFT	19
1266 #define	PN_DTLB_PGSZ1_MASK	(7 << PN_DTLB_PGSZ1_SHIFT)
1267 #define	PN_DTLB_PGSZ_MASK	(PN_DTLB_PGSZ1_MASK | PN_DTLB_PGSZ0_MASK)
1268 #define	PN_DTLB_T512_0		(2 << 16)
1269 #define	PN_DTLB_T512_1		(3 << 16)
1270 #define	PN_TLO_INFO_IMMU_SHIFT	14
1271 #define	PN_TLO_INFO_IMMU	(1 << PN_TLO_INFO_IMMU_SHIFT)
1272 #define	PN_TLO_INFO_TL1_SHIFT	13
1273 #define	PN_TLO_INFO_TL1		(1 << PN_TLO_INFO_TL1_SHIFT)
1274 #define	PN_ITLB_T512		(2 << 16)
1275 #define	PN_TLB_ACC_IDX_SHIFT	3
1276 #define	PN_TLB_ACC_WAY_BIT	(1 << 11)
1277 #define	PN_TLB_DIAGACC_OFFSET	0x40000	/* Diag Acc ASI VA offset */
1278 /*
1279  * tag parity = XOR(Size[2:0],Global,VA[63:21],Context[12:0])
1280  * which requires looking at both the tag and the data.
1281  */
1282 #define	PN_TLB_TAG_PARITY_TAG_MASK	0xffffffffffe01fff
1283 #define	PN_TLB_TAG_PARITY_DATA_MASK	0x6001400000000001
1284 /* data parity = XOR(NFO,IE,PA[42:13],CP,CV,E,P,W) */
1285 #define	PN_TLB_DATA_PARITY_DATA_MASK	0x180087ffffffe03e
1286 
1287 #ifdef _KERNEL
1288 
1289 #ifndef	_ASM
1290 
1291 #include <sys/kstat.h>
1292 
1293 /*
1294  * One Ecache data element, 32 bytes of data, 8 bytes of ECC.
1295  * See Cheetah PRM 10.7.2.
1296  */
1297 typedef struct ec_data_elm {
1298 	uint64_t ec_d8[CH_ECACHE_STGREG_NUM];
1299 	uint64_t ec_eccd;	/* EC_data_ECC field */
1300 } ec_data_elm_t;
1301 
1302 /*
1303  * L2 and L3 cache data captured by cpu log out code.
1304  * See Cheetah PRM 10.7.4.
1305  */
1306 typedef struct ch_ec_data {
1307 	uint64_t ec_logflag;	/* Flag indicates if data was logged */
1308 	uint64_t ec_idx;	/* Ecache index */
1309 	uint64_t ec_way;	/* Ecache way */
1310 	uint64_t ec_tag;	/* Ecache Tag */
1311 	uint64_t ec_tag_ecc;	/* Ecache Tag ECC (Cheetah+ only) */
1312 	ec_data_elm_t ec_data[CH_ECACHE_SUBBLK_SIZE/CH_ECACHE_STGREG_SIZE];
1313 } ch_ec_data_t;
1314 
1315 /*
1316  * Dcache data captured by cpu log out code and get_dcache_dtag.
1317  * See Cheetah PRM 10.6.[1-4].
1318  */
1319 typedef struct ch_dc_data {
1320 	uint64_t dc_logflag;	/* Flag indicates if data was logged */
1321 	uint64_t dc_idx;	/* Dcache index */
1322 	uint64_t dc_way;	/* Dcache way */
1323 	uint64_t dc_tag;	/* Tag/Valid Fields */
1324 	uint64_t dc_utag;	/* Microtag */
1325 	uint64_t dc_sntag;	/* Snoop Tag */
1326 	uint64_t dc_data[CH_DC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */
1327 	uint64_t dc_pn_data_parity;	/* Data parity bits for Panther */
1328 } ch_dc_data_t;
1329 
1330 /*
1331  * Icache data captured by cpu log out code and get_icache_dtag.
1332  * See Cheetah PRM 10.4.[1-3].
1333  */
1334 typedef struct ch_ic_data {
1335 	uint64_t ic_logflag;	/* Flag indicates if data was logged */
1336 	uint64_t ic_idx;	/* Icache index */
1337 	uint64_t ic_way;	/* Icache way */
1338 	uint64_t ic_patag;	/* Physical address tag */
1339 	uint64_t ic_utag;	/* Microtag */
1340 	uint64_t ic_upper;	/* Upper valid/predict tag */
1341 	uint64_t ic_lower;	/* Lower valid/predict tag */
1342 	uint64_t ic_sntag;	/* Snoop Tag */
1343 	uint64_t ic_data[PN_IC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */
1344 } ch_ic_data_t;
1345 
1346 /*
1347  * Pcache data captured by get_pcache_dtag
1348  */
1349 typedef struct ch_pc_data {
1350 	uint64_t pc_logflag;	/* Flag indicates if data was logged */
1351 	uint64_t pc_idx;	/* Pcache index */
1352 	uint64_t pc_way;	/* Pcache way */
1353 	uint64_t pc_status;	/* Pcache status data */
1354 	uint64_t pc_tag;	/* Tag/Valid Fields */
1355 	uint64_t pc_sntag;	/* Snoop Tag */
1356 	uint64_t pc_data[CH_PC_DATA_REG_SIZE/sizeof (uint64_t)]; /* Data */
1357 } ch_pc_data_t;
1358 
1359 /*
1360  * CPU Error State
1361  */
1362 typedef struct ch_cpu_errors {
1363 	uint64_t afsr;		/* AFSR */
1364 	uint64_t afar;		/* AFAR */
1365 	/*
1366 	 * The following registers don't exist on cheetah
1367 	 */
1368 	uint64_t shadow_afsr;	/* Shadow AFSR */
1369 	uint64_t shadow_afar;	/* Shadow AFAR */
1370 	uint64_t afsr_ext;	/* AFSR1_EXT */
1371 	uint64_t shadow_afsr_ext;	/* AFSR2_EXT */
1372 	uint64_t afar2;		/* AFAR2 - Serrano only */
1373 } ch_cpu_errors_t;
1374 
1375 /*
1376  * CPU logout structures.
1377  * NOTE: These structures should be the same for Cheetah, Cheetah+,
1378  *	 Jaguar, Panther, and Jalapeno since the assembler code relies
1379  *	 on one set of offsets. Panther is the only processor that
1380  *	 uses the chd_l2_data field since it has both L3 and L2 caches.
1381  */
1382 typedef struct ch_diag_data {
1383 	uint64_t chd_afar;				/* AFAR */
1384 	uint64_t chd_afsr;				/* AFSR */
1385 	uint64_t chd_afsr_ext;				/* AFSR_EXT */
1386 	uint64_t chd_afar2;			/* AFAR2 - Serrano only */
1387 	ch_ec_data_t chd_ec_data[CHD_EC_DATA_SETS];	/* Ecache data */
1388 	ch_ec_data_t chd_l2_data[PN_L2_NWAYS];		/* L2 cache data */
1389 	ch_dc_data_t chd_dc_data;			/* Dcache data */
1390 	ch_ic_data_t chd_ic_data;			/* Icache data */
1391 } ch_diag_data_t;
1392 
1393 
1394 /*
1395  * Top level CPU logout structure.
1396  * clo_flags is used to hold information such as trap type, trap level,
1397  * CEEN value, etc that is needed by the individual trap handlers. Not
1398  * all fields in this flag are used by all trap handlers but when they
1399  * are used, here's how they are laid out:
1400  *
1401  * |-------------------------------------------------------|
1402  * |        | trap type | trap level |  |UCEEN| |NCEEN|CEEN|
1403  * |-------------------------------------------------------|
1404  *  63       19       12 11         8      3   2   1    0
1405  *
1406  * Note that the *CEEN bits correspond exactly to the same bit positions
1407  * that are used in the error enable register.
1408  */
1409 typedef struct ch_cpu_logout {
1410 	uint64_t clo_flags;		/* Information about this trap */
1411 	uint64_t clo_nest_cnt;		/* To force an upper bound */
1412 	ch_diag_data_t clo_data;	/* Diag data for primary AFAR */
1413 	ch_diag_data_t clo_sdw_data;	/* Diag data for shadow AFAR */
1414 } ch_cpu_logout_t;
1415 
1416 typedef struct ch_tte_entry {
1417 	uint64_t ch_tte_tag;
1418 	uint64_t ch_tte_data;
1419 } ch_tte_entry_t;
1420 
1421 /*
1422  * Top level CPU logout structure for TLB parity errors.
1423  *
1424  * tlo_logflag  - Flag indicates if data was logged
1425  * tlo_info	- Used to keep track of a number of values:
1426  *   itlb pgsz	  - Page size of the VA whose lookup in the ITLB caused
1427  *		    the exception (from ASI_IMMU_TAG_ACCESS_EXT.)
1428  *   dtlb pgsz1	  - Page size of the VA whose lookup in the DTLB T512_1
1429  *		    caused the exception (from ASI_DMMU_TAG_ACCESS_EXT.).
1430  *   dtlb pgsz0	  - Page size of the VA whose lookup in the DTLB T512_0
1431  *		    caused the exception (from ASI_DMMU_TAG_ACCESS_EXT.).
1432  *   immu	  - Trap is the result of an ITLB exception if immu == 1.
1433  *		    Otherwise, for DTLB exceptions immu == 0.
1434  *   tl1	  - Set to 1 if the exception occured at TL>0.
1435  *   context	  - Context of the VA whose lookup in the TLB caused the
1436  *		    exception (from ASI_[I|D]MMU_TAG_ACCESS.)
1437  * |---------------------------------------------------------------------|
1438  * |...| itlb pgsz  | dtlb pgsz1 | dtlb pgsz0 |...| immu | tl1 | context |
1439  * |---------------------------------------------------------------------|
1440  *      24        22 21        19 18        16       14    13   12      0
1441  *
1442  * tlo_addr	- VA that cause the MMU exception trap.
1443  * tlo_pc	- PC where the exception occured.
1444  * tlo_itlb_tte	- TTEs that were in the ITLB after the trap at the index
1445  *		  specific to the VA and page size in question.
1446  * tlo_dtlb_tte	- TTEs that were in the DTLB after the trap at the index
1447  *		  specific to the VA and page size in question.
1448  */
1449 typedef struct pn_tlb_logout {
1450 	uint64_t tlo_logflag;
1451 	uint64_t tlo_info;
1452 	uint64_t tlo_addr;
1453 	uint64_t tlo_pc;
1454 	ch_tte_entry_t tlo_itlb_tte[PN_ITLB_NWAYS * PN_NUM_512_ITLBS];
1455 	ch_tte_entry_t tlo_dtlb_tte[PN_DTLB_NWAYS * PN_NUM_512_DTLBS];
1456 } pn_tlb_logout_t;
1457 
1458 #if defined(CPU_IMP_L1_CACHE_PARITY)
1459 /*
1460  * Parity error logging structure.
1461  */
1462 typedef union ch_l1_parity_log {
1463 	struct {
1464 		int cpl_way;				/* Faulty line way */
1465 		int cpl_off;				/* Faulty line offset */
1466 		int cpl_tag;				/* Faulty tags list */
1467 		int cpl_lcnt;				/* Faulty cache lines */
1468 		ch_dc_data_t cpl_dc[CH_DCACHE_NWAY];	/* D$ data nWays */
1469 		ch_pc_data_t cpl_pc[CH_PCACHE_NWAY];	/* P$ data nWays */
1470 		int cpl_cache;				/* error in D$ or P$? */
1471 	} dpe;	/* D$ parity error */
1472 	struct {
1473 		int cpl_way;				/* Faulty line way */
1474 		int cpl_off;				/* Faulty line offset */
1475 		int cpl_tag;				/* Faulty tags list */
1476 		int cpl_lcnt;				/* Faulty cache lines */
1477 		ch_ic_data_t cpl_ic[CH_ICACHE_NWAY];	/* I$ data nWays */
1478 	} ipe;	/* I$ parity error */
1479 } ch_l1_parity_log_t;
1480 
1481 #endif	/* CPU_IMP_L1_CACHE_PARITY */
1482 
1483 /*
1484  * Error at TL>0 CPU logout data.
1485  *   Needs some extra space to save %g registers and miscellaneous info.
1486  */
1487 typedef struct ch_err_tl1_data {
1488 	uint64_t ch_err_tl1_g1;		/* Saved %g1 */
1489 	uint64_t ch_err_tl1_g2;		/* Saved %g2 */
1490 	uint64_t ch_err_tl1_g3;		/* Saved %g3 */
1491 	uint64_t ch_err_tl1_g4;		/* Saved %g4 */
1492 	uint64_t ch_err_tl1_g5;		/* Saved %g5 */
1493 	uint64_t ch_err_tl1_g6;		/* Saved %g6 */
1494 	uint64_t ch_err_tl1_g7;		/* Saved %g7 */
1495 	uint64_t ch_err_tl1_tpc;	/* Trap PC */
1496 	uint64_t ch_err_tl1_flags;	/* miscellaneous flags */
1497 	uint64_t ch_err_tl1_tmp;	/* some handlers may use as tmp */
1498 	ch_cpu_logout_t ch_err_tl1_logout;	/* logout */
1499 } ch_err_tl1_data_t;
1500 
1501 /* Indices into chsm_outstanding and friends */
1502 #define	CACHE_SCRUBBER_INFO_E	0
1503 #define	CACHE_SCRUBBER_INFO_D	1
1504 #define	CACHE_SCRUBBER_INFO_I	2
1505 
1506 /* We define 3 scrubbers: E$, D$, and I$ */
1507 #define	CACHE_SCRUBBER_COUNT	3
1508 
1509 /*
1510  * The ch_scrub_misc structure contains miscellaneous bookkeeping
1511  * items for scrubbing the I$, D$, and E$.
1512  *
1513  * For a description of the use of chsm_core_state and why it's not needed
1514  * on Jaguar, see the comment above cpu_scrub_cpu_setup() in us3_cheetahplus.c.
1515  */
1516 typedef struct ch_scrub_misc {
1517 	uint32_t	chsm_outstanding[CACHE_SCRUBBER_COUNT];
1518 						/* outstanding requests */
1519 	int		chsm_flush_index[CACHE_SCRUBBER_COUNT];
1520 						/* next line to flush */
1521 	int		chsm_enable[CACHE_SCRUBBER_COUNT];
1522 				/* is this scrubber enabled on this core? */
1523 	int		chsm_ecache_nlines;	/* no. of E$ lines */
1524 	int		chsm_ecache_busy;	/* keeps track if cpu busy */
1525 	int		chsm_icache_nlines;	/* no. of I$ lines */
1526 	int		chsm_core_state;	/* which core the scrubber is */
1527 						/* running on (Panther only) */
1528 } ch_scrub_misc_t;
1529 
1530 /*
1531  * Cheetah module private data structure.  One of these is allocated for
1532  * each valid cpu at setup time and is pointed to by the machcpu
1533  * "cpu_private" pointer.  For Cheetah, we have the miscellaneous scrubber
1534  * variables and cpu log out structures for Fast ECC traps at TL=0,
1535  * Disrupting (correctable) traps and Deferred (asynchronous) traps.  For
1536  * Disrupting traps only one log out structure is needed because we cannot
1537  * get a TL>0 disrupting trap since it obeys IE.  For Deferred traps we
1538  * cannot get a TL>0 because we turn off NCEEN during log out capture.  E$
1539  * set size (E$ size / nways) is saved here to avoid repeated calculations.
1540  * NB: The ch_err_tl1_data_t structures cannot cross a page boundary
1541  *      because we use physical addresses to access them.  We ensure this
1542  *      by allocating them near the front of cheetah_private_t, which is
1543  *      aligned on PAGESIZE (8192) via kmem_cache_create, and by ASSERTing
1544  *	sizeof (chpr_tl1_err_data) <= CH_ECACHE_MAX_LSIZE in the
1545  *	cpu_init_private routines.
1546  * NB:  chpr_icache_size and chpr_icache_linesize need to be at the front
1547  *	of cheetah_private_t because putting them after chpr_tl1_err_data
1548  *	would make their offsets > 4195.
1549  */
1550 typedef struct cheetah_private {
1551 	int			chpr_icache_size;
1552 	int			chpr_icache_linesize;
1553 	ch_err_tl1_data_t	chpr_tl1_err_data[CH_ERR_TL1_TLMAX];
1554 	ch_scrub_misc_t		chpr_scrub_misc;
1555 	int			chpr_ec_set_size;
1556 	ch_cpu_logout_t		chpr_fecctl0_logout;
1557 	ch_cpu_logout_t		chpr_cecc_logout;
1558 	ch_cpu_logout_t		chpr_async_logout;
1559 	pn_tlb_logout_t		chpr_tlb_logout;
1560 	uint64_t		chpr_fpras_timestamp[FPRAS_NCOPYOPS];
1561 	hrtime_t		chpr_ceptnr_seltime;
1562 	int			chpr_ceptnr_id;
1563 } cheetah_private_t;
1564 
1565 #endif /* _ASM */
1566 
1567 #endif /* _KERNEL */
1568 
1569 #ifdef	__cplusplus
1570 }
1571 #endif
1572 
1573 #endif	/* _SYS_CHEETAHREGS_H */
1574